| Line 57... |
Line 57... |
i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
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// UART control
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o_uart_setup,
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o_uart_setup,
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// GPIO lines
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// GPIO lines
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i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
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parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
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BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
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ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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input i_clk, i_rst;
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input i_clk, i_rst;
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// The bus commander, via an external JTAG port
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input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output reg o_tx_stb;
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output reg o_tx_stb;
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output reg [7:0] o_tx_data;
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output reg [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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| Line 258... |
Line 257... |
wire [31:0] pic_data;
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wire [31:0] pic_data;
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icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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wb_data, pic_data, int_vector, w_interrupt);
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wb_data, pic_data, int_vector, w_interrupt);
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|
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initial bus_err_addr = `DATESTAMP;
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initial bus_err_addr = 0; // `DATESTAMP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
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|
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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| Line 288... |
Line 287... |
always @(posedge i_clk)
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always @(posedge i_clk)
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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assign rtc_ack = r_rtc_ack;
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assign rtc_ack = r_rtc_ack;
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|
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rtclight
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rtclight
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#(32'h35afe5,23,0,0) // 80 MHz clock
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#(23'h35afe5,23,0,0) // 80 MHz clock
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thetime(i_clk, wb_cyc,
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thetime(i_clk, wb_cyc,
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((wb_stb)&&(rtc_sel)), wb_we,
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((wb_stb)&&(rtc_sel)), wb_we,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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rtc_interrupt, ppd);
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rtc_interrupt, ppd);
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`else
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`else
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