OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.h] - Diff between revs 8 and 11

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 8 Rev 11
Line 100... Line 100...
#define R_CKALARM       0x00000803
#define R_CKALARM       0x00000803
 
 
// RAM memory space
// RAM memory space
#define RAMBASE         0x00002000
#define RAMBASE         0x00002000
#define MEMWORDS        (1<<12)
#define MEMWORDS        (1<<12)
 
#define RAMLEN          MEMWORDS
 
 
// Flash memory space
// Flash memory space
#define SPIFLASH        0x00040000
#define SPIFLASH        0x00400000
#define FLASHWORDS      (1<<18)
#define FLASHWORDS      (1<<22)
// SDRAM memory space
#define CONFIG_ADDRESS  0x00400000 // Main Xilinx configuration (ZipCPU)
#define SDRAMBASE       0x00400000
#define ALTCONFIG_ADDRESS 0x440000 // Alternate Xilinx configuration (Debug)
#define SDRAMWORDS      (1<<24)
#define RESET_ADDRESS   0x00480000 // ZipCPU Reset address
 
 
// Interrupt control constants
// Interrupt control constants
// #define      GIE             0x80000000      // Enable all interrupts
#define GIE             0x80000000      // Enable all interrupts
// #define      SCOPEN          0x80080008      // Enable WBSCOPE interrupts
#define SCOPEN          0x80040004      // Enable WBSCOPE interrupts
// #define      ISPIF_EN        0x80040004      // Enable SPI Flash interrupts
#define ISPIF_EN        0x90001000      // Enable SPI Flash interrupts
// #define      ISPIF_DIS       0x00040000      // Disable SPI Flash interrupts
#define ISPIF_DIS       0x10000000      // Disable SPI Flash interrupts
// #define      ISPIF_CLR       0x00000004      // Clear pending SPI Flash interrupt
#define ISPIF_CLR       0x10001000      // Clear pending SPI Flash interrupt
 
 
// Flash control constants
// Flash control constants
#define ERASEFLAG       0x80000000
#define ERASEFLAG       0x80000000
#define DISABLEWP       0x10000000
#define DISABLEWP       0x10000000
 
 
#define SZPAGE          64
// Sectors are defined as 64 kB (16 kW)
#define PGLEN           64
#define SZPAGE          64      // 256 bytes
#define NPAGES          32
#define PGLEN           64      // 256 bytes
 
#define NPAGES          256     // 64 kB sectors / 256 bytes is ...
#define SECTORSZ        (NPAGES * SZPAGE)
#define SECTORSZ        (NPAGES * SZPAGE)
#define NSECTORS        256
#define NSECTORS        (FLASHWORDS/SECTORSZ)   // 256 sectors
#define SECTOROF(A)     ((A) & (-1<<10))
#define SECTOROF(A)     ((A) & (-1<<14))        // 64 kB ea
#define PAGEOF(A)       ((A) & (-1<<6))
#define PAGEOF(A)       ((A) & (-1<<6))
 
 
#define RAMLEN          MEMWORDS
 
 
 
// Scop definition/sequences
// Scop definition/sequences
#define SCOPE_NO_RESET  0x80000000
#define SCOPE_NO_RESET  0x80000000
#define SCOPE_TRIGGER   (0x08000000|SCOPE_NO_RESET)
#define SCOPE_TRIGGER   (0x08000000|SCOPE_NO_RESET)
#define SCOPE_DISABLE   (0x04000000)
#define SCOPE_DISABLE   (0x04000000)
 
 
Line 150... Line 151...
// #include "ttybus.h"
// #include "ttybus.h"
// #include "portbus.h"
// #include "portbus.h"
// #include "deppbus.h"
// #include "deppbus.h"
 
 
// typedef      DEPPBUS FPGA;
// typedef      DEPPBUS FPGA;
 
#include "ttybus.h"
 
typedef TTYBUS  FPGA;
 
 
#endif
#endif
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.