| Line 41... |
Line 41... |
%%%% %%%%
|
%%%% %%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\section{Software interface}
|
\section{Software interface}
|
\label{sec:sw_if}
|
\label{sec:sw_if}
|
|
|
Access to IP core registers is provided through Wishbone slave interface.
|
Access to IP core registers is provided through a Wishbone slave interface.
|
|
|
\subsection{IP Core registers}
|
\subsection{IP Core registers}
|
\label{sec:regs}
|
\label{sec:regs}
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
| Line 58... |
Line 58... |
\texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
|
\texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
|
\texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
|
\texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
|
\texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
|
\texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
|
\texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
|
\texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
|
\texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
|
\texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
|
\texttt{clock\_devider} & \texttt{0x24} & RW & MMC/SD interface clock devider \\ \hline
|
\texttt{clock\_divider} & \texttt{0x24} & RW & MMC/SD interface clock divider \\ \hline
|
\texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
|
\texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
|
\texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
|
\texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
|
\texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
|
\texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
|
\texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
|
\texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
|
\texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
|
\texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
|
| Line 77... |
Line 77... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Argument register}
|
\subsubsection{Argument register}
|
\label{sec:arg_reg}
|
\label{sec:arg_reg}
|
|
|
Write operation to this register triggers command transaction (command register has to be configured before writing to this register).
|
A write operation to this register triggers a command transaction (The command register has to be configured before writing to this register).
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Argument register}
|
\caption{Argument register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| Line 92... |
Line 92... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Command register}
|
\subsubsection{Command register}
|
\label{sec:cmd_reg}
|
\label{sec:cmd_reg}
|
|
|
This register configures all aspects of command to be sent.
|
This register configures all aspects of the command to be sent.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Command register}
|
\caption{Command register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| Line 104... |
Line 104... |
\texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
|
\texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
|
\texttt{[7]} & & & reserved \\ \hline
|
\texttt{[7]} & & & reserved \\ \hline
|
\texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
|
\texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
|
0x2 - triggers write data transaction after command transaction\\ \hline
|
0x2 - triggers write data transaction after command transaction\\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & check response crc \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & check response CRC \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,
|
\texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,
|
core will wait for as long as busy signal remains) \\ \hline
|
the core will wait for as long as the busy signal remains) \\ \hline
|
\texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
|
\texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
|
0x2 - wait for long response (136-bits) \\ \hline
|
0x2 - wait for long response (136-bits) \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:cmd_reg}
|
\label{tab:cmd_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Response register 0-3}
|
\subsubsection{Response register 0-3}
|
\label{sec:resp_reg}
|
\label{sec:resp_reg}
|
|
|
Response registers 0-3 contains response data bits after end of succesful command transaction (if bits 1-0 of command register were configured to wait for response).
|
Response registers 0-3 contain response data bits after a successful command transaction (if bits 1-0 of command register were configured to wait for response).
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Response register 0-3}
|
\caption{Response register 0-3}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
| Line 147... |
Line 147... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Timeout register}
|
\subsubsection{Timeout register}
|
\label{sec:timeout_reg}
|
\label{sec:timeout_reg}
|
|
|
Timeout register configures transaction watchdog counter. If any transaction will last longer than configured timeout, interrupt will be generated.
|
The timeout register configures the transaction watchdog counter. If any transaction lasts longer than the configured timeout, an interrupt will be generated.
|
Value in timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cyckles. Register value is calculated by following formula:
|
The value in the timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cycles. The register value is calculated by the following formula:
|
\begin{equation}
|
\begin{equation}
|
REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_devider} + 1))}
|
REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_divider} + 1))}
|
\end{equation}
|
\end{equation}
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Timeout register}
|
\caption{Timeout register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| Line 164... |
Line 164... |
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:timeout_reg}
|
\label{tab:timeout_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Clock devider register}
|
\subsubsection{Clock divider register}
|
\label{sec:div_reg}
|
\label{sec:div_reg}
|
|
|
Clock devider register control division of \texttt{sd\_clk\_i\_pad} signal frequency. Output of this devider is routed to MMC/SD interface clock domain.
|
The clock divider register controls division of the \texttt{sd\_clk\_i\_pad} signal frequency. The output of this divider is routed to the MMC/SD interface clock domain.
|
Register value is calculated by following formula:
|
The register value is calculated by following formula:
|
\begin{equation}
|
\begin{equation}
|
REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
|
REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
|
\end{equation}
|
\end{equation}
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Clock devider register}
|
\caption{Clock divider register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:8]} & & & reserved \\ \hline
|
\texttt{[31:8]} & & & reserved \\ \hline
|
\texttt{[7:0]} & \texttt{0x0} & RW & devider ratio \\ \hline
|
\texttt{[7:0]} & \texttt{0x0} & RW & divider ratio \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:div_reg}
|
\label{tab:div_reg}
|
\end{table}
|
\end{table}
|
|
|
| Line 201... |
Line 201... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Voltage information register}
|
\subsubsection{Voltage information register}
|
\label{sec:voltage_reg}
|
\label{sec:voltage_reg}
|
|
|
This register contains the value of power supply voltage expressed in mV. It is read-only register and its
|
This register contains the value of the card power supply voltage expressed in mV. It is a read-only register and its
|
value is configured in HDL.
|
value is configured in HDL.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Software reset register}
|
\caption{Software reset register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
| Line 230... |
Line 230... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Command events status register}
|
\subsubsection{Command events status register}
|
\label{sec:cmd_evt_reg}
|
\label{sec:cmd_evt_reg}
|
|
|
This register holds all pending event flags related to command transactions. Write operation to this register
|
This register holds all pending event flags related to command transactions. Any write operation to this register
|
clears all flags.
|
clears all flags.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Command events status register}
|
\caption{Command events status register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:5]} & & & reserved \\ \hline
|
\texttt{[31:5]} & & & reserved \\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & crc error event \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & CRC error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
| Line 251... |
Line 251... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{Command transaction events enable register}
|
\subsubsection{Command transaction events enable register}
|
\label{sec:cmd_ena_reg}
|
\label{sec:cmd_ena_reg}
|
|
|
This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
|
This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Command transaction events enable register}
|
\caption{Command transaction events enable register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:5]} & & & reserved \\ \hline
|
\texttt{[31:5]} & & & reserved \\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
|
\texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & enable crc error event \\ \hline
|
\texttt{[3]} & \texttt{0x0} & RW & enable CRC error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & enable command transaction succesful completion event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & enable command transaction successful completion event \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:cmd_ena_reg}
|
\label{tab:cmd_ena_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Data transaction events status register}
|
\subsubsection{Data transaction events status register}
|
\label{sec:data_evt_reg}
|
\label{sec:data_evt_reg}
|
|
|
This register holds all pending event flags related to data transactions. Write operation to this register
|
This register holds all pending event flags related to data transactions. Any write operation to this register
|
clears all flags.
|
clears all flags.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Data transaction events status register}
|
\caption{Data transaction events status register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:3]} & & & reserved \\ \hline
|
\texttt{[31:3]} & & & reserved \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & crc error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & CRC error event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & data transaction succesful completion event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & data transaction successful completion event \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:data_evt_reg}
|
\label{tab:data_evt_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Data transaction events enable register}
|
\subsubsection{Data transaction events enable register}
|
\label{sec:data_ena_reg}
|
\label{sec:data_ena_reg}
|
|
|
This register acts as event \textit{and} mask. To enable given event, corresponding bit must be set to 1.
|
This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Data transaction events enable register}
|
\caption{Data transaction events enable register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:3]} & & & reserved \\ \hline
|
\texttt{[31:3]} & & & reserved \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
|
\texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & enable crc error event \\ \hline
|
\texttt{[1]} & \texttt{0x0} & RW & enable CRC error event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & enable data transaction succesful completion event \\ \hline
|
\texttt{[0]} & \texttt{0x0} & RW & enable data transaction successful completion event \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:data_ena_reg}
|
\label{tab:data_ena_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Block size register}
|
\subsubsection{Block size register}
|
\label{sec:blocksize_reg}
|
\label{sec:blocksize_reg}
|
|
|
This register controls the number of bytes to write/read in a single block. Data transaction will transmit number of bytes equal to size of block times blocks count.
|
This register controls the number of bytes to write/read in a single block. A data transaction will transmit a number of bytes equal to the block size times the block count.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{Block size register}
|
\caption{Block size register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\texttt{[31:12]} & & & reserved \\ \hline
|
\texttt{[31:12]} & & & reserved \\ \hline
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of byes in a single block \\ \hline
|
\texttt{[11:0]} & \texttt{0x200} & RW & number of bytes in a single block \\ \hline
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\label{tab:blocksize_reg}
|
\label{tab:blocksize_reg}
|
\end{table}
|
\end{table}
|
|
|
\subsubsection{Block count register}
|
\subsubsection{Block count register}
|
\label{sec:blockcnt_reg}
|
\label{sec:blockcnt_reg}
|
|
|
This register controls the number of blocks to write/read in data transaction. Data transaction will transmit number of bytes equal to value blocks count times block size.
|
This register controls the number of blocks to write/read in a data transaction. A data transaction will transmit a number of bytes equal to the block count times block size.
|
Register value is calculated by following formula:
|
The register value is calculated by following formula:
|
\begin{equation}
|
\begin{equation}
|
REG = number\_of\_blocks - 1
|
REG = number\_of\_blocks - 1
|
\end{equation}
|
\end{equation}
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
| Line 344... |
Line 344... |
\end{table}
|
\end{table}
|
|
|
\subsubsection{DMA destination / source register}
|
\subsubsection{DMA destination / source register}
|
\label{sec:dst_src_reg}
|
\label{sec:dst_src_reg}
|
|
|
This registers configures the DMA source / destination address. For write transactions, this address points to the begining of data block to be sent.
|
This registers configures the DMA source / destination address. For write transactions, this address points to the begining of the data block to be sent.
|
For read transactions, this address points to the begining of data block to be written.
|
For read transactions, this address points to the begining of data block to be received and written to RAM.
|
|
|
\begin{table}[H]
|
\begin{table}[H]
|
\caption{DMA destination / source register}
|
\caption{DMA destination / source register}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
|
