| Line 72... |
Line 72... |
.4 run.
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.4 run.
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.4 src.
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.4 src.
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}
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}
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|
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\begin{description}
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\begin{description}
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\item[\texttt{bench/verilog}] - verilog testbench sources,
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\item[\texttt{bench/verilog}] - Verilog testbench sources,
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\item[\texttt{doc}] - documentation files,
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\item[\texttt{doc}] - documentation files,
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\item[\texttt{doc/src}] - documentation \LaTeX sources,
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\item[\texttt{doc/src}] - documentation \LaTeX sources,
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\item[\texttt{rtl/verilog}] - ip core verilog sources,
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\item[\texttt{rtl/verilog}] - IP core Verilog sources,
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\item[\texttt{sim/rtl\_sim/bin}] - simulation makefile and modelsim scripts,
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\item[\texttt{sim/rtl\_sim/bin}] - simulation makefile and modelsim scripts,
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\item[\texttt{sim/rtl\_sim/log}] - log files created during simulation,
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\item[\texttt{sim/rtl\_sim/log}] - log files created during simulation,
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\item[\texttt{sim/rtl\_sim/run}] - simulation execution directory,
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\item[\texttt{sim/rtl\_sim/run}] - simulation execution directory,
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\item[\texttt{sw/example}] - baremetal example application for or1k,
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\item[\texttt{sw/example}] - baremetal example application for or1k,
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\item[\texttt{syn/quartus/bin}] - synthesis makefile and scripts for quartus example project,
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\item[\texttt{syn/quartus/bin}] - synthesis makefile and scripts for Quartus example project,
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\item[\texttt{syn/quartus/run}] - synthesis execution directory,
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\item[\texttt{syn/quartus/run}] - synthesis execution directory,
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\item[\texttt{syn/quartus/src}] - example project sources.
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\item[\texttt{syn/quartus/src}] - example project sources.
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\end{description}
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\end{description}
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|
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\subsection{Simulation}
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\subsection{Simulation}
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\label{sec:simulation}
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\label{sec:simulation}
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|
|
To start simulation just enter to \path{sim/rtl_sim/run} directory and type \texttt{make}:
|
To start the simulation just change to the \path{sim/rtl_sim/run} directory and type \texttt{make}:
|
\begin{verbatim}
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\begin{verbatim}
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#> cd sim/rtl_sim/run
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#> cd sim/rtl_sim/run
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#> make
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#> make
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\end{verbatim}
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\end{verbatim}
|
|
|
Every testbench is written in SystemVerilog (mostly due to use of \texttt{assert} keyword). Every testbench is self checking. Test error are represented by
|
Every testbench is written in SystemVerilog (mostly due to use of \texttt{assert} keyword). Every testbench is self checking. Test errors are represented by
|
assert failures. Every testbench starts by displaying:
|
assert failures. Every testbench starts by displaying:
|
\begin{verbatim}
|
\begin{verbatim}
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# testbench_name start ...
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# testbench_name start ...
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\end{verbatim}
|
\end{verbatim}
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and ends by displaying:
|
and ends by displaying:
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\begin{verbatim}
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\begin{verbatim}
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# testbench_name finish ...
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# testbench_name finish ...
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\end{verbatim}
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\end{verbatim}
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If no asserts are displayed between these lines, the test passes. Below is an example of passing test:
|
If no asserts are displayed between these lines, the test passed. Below is an example of passing test:
|
\begin{verbatim}
|
\begin{verbatim}
|
...
|
...
|
some compilation output
|
some compilation output
|
...
|
...
|
# sd_cmd_master_tb start ...
|
# sd_cmd_master_tb start ...
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| Line 130... |
Line 130... |
\end{verbatim}
|
\end{verbatim}
|
|
|
\subsubsection{Simulation makefile targets}
|
\subsubsection{Simulation makefile targets}
|
\label{sec:sim_make_targ}
|
\label{sec:sim_make_targ}
|
|
|
The default simulation target is to run all testbenches from \path{bench/verilog} directory that ends with \path{_.sv}. Other simulation targets are:
|
The default simulation target is to run all testbenches from \path{bench/verilog} directory that end with \path{_.sv}. Other simulation targets are:
|
\begin{description}
|
\begin{description}
|
\item[\texttt{clean}] - remove all simulation output files,
|
\item[\texttt{clean}] - remove all simulation output files,
|
\item[\texttt{print\_testbenches}] - lists all availible testbenches,
|
\item[\texttt{print\_testbenches}] - lists all available testbenches,
|
\item[\texttt{modelsim}] - compiles all sources and launches modelsim (see \ref{sec:sim_make_var}),
|
\item[\texttt{modelsim}] - compiles all sources and launches modelsim (see \ref{sec:sim_make_var}),
|
\item[\texttt{*\_tb}] - compiles and executes given testbench. All items listed by the \path{print_testbenches} target can be executed this way,
|
\item[\texttt{*\_tb}] - compiles and executes the given testbench. All items listed by the \path{print_testbenches} target can be executed this way,
|
\item[\texttt{*\_tb\_gui}] - same as \path{*_tb} target, only instead of executing simulation in command-line, launches modelsim.
|
\item[\texttt{*\_tb\_gui}] - same as \path{*_tb} target, only instead of executing the simulation via command-line, launches modelsim.
|
\end{description}
|
\end{description}
|
|
|
\subsubsection{Simulation makefile environment variables}
|
\subsubsection{Simulation makefile environment variables}
|
\label{sec:sim_make_var}
|
\label{sec:sim_make_var}
|
|
|
Simulation makefile uses couple of environment variables to setup simulation:
|
The simulation makefile uses a couple of environment variables to setup the simulation:
|
\begin{description}
|
\begin{description}
|
\item[\texttt{MODELSIM\_DIR}] - modelsim installation directory (\path{\$(MODELSIM_DIR)/bin/vsim} should be a valid path),
|
\item[\texttt{MODELSIM\_DIR}] - modelsim installation directory (\path{\$(MODELSIM_DIR)/bin/vsim} should be a valid path),
|
\item[\texttt{VCD}] - when set to 1 - all waveforms are dumped to \path{sim/rtl_sim/out/*.vcd} files; when set to 0 - no waveforms are dumped (0 is default),
|
\item[\texttt{VCD}] - when set to 1 - all waveforms are dumped to \path{sim/rtl_sim/out/*.vcd} files; when set to 0 - no waveforms are dumped (0 is default),
|
\item[\texttt{V}] - when set to 1 - enables verbose output; when set to 0 - normal simulation output (0 is default).
|
\item[\texttt{V}] - when set to 1 - enables verbose output; when set to 0 - normal simulation output (0 is default).
|
\end{description}
|
\end{description}
|
| Line 159... |
Line 159... |
To start synthesis just enter to \path{syn/quartus/run} directory and type \texttt{make}:
|
To start synthesis just enter to \path{syn/quartus/run} directory and type \texttt{make}:
|
\begin{verbatim}
|
\begin{verbatim}
|
#> cd syn/quartus/run
|
#> cd syn/quartus/run
|
#> make
|
#> make
|
\end{verbatim}
|
\end{verbatim}
|
Example project consist of all verilog sources from \path{rtl/verilog} directory and \path{syn/quartus/src/sdc_controller_top.v} source file.
|
The example project consists of all Verilog sources from the \path{rtl/verilog} directory and \path{syn/quartus/src/sdc_controller_top.v} source file.
|
The purpose of the additional verilog file is to instantiate the \textit{Wishbone SD Card Controller IP Core} and register all inputs/outputs to/from the core.
|
The purpose of the additional Verilog file is to instantiate the \textit{Wishbone SD Card Controller IP Core} and register all inputs/outputs to/from the core.
|
This makes timing verification more accurate.
|
This makes timing verification more accurate.
|
|
|
\subsubsection{Synthesis makefile targets}
|
\subsubsection{Synthesis makefile targets}
|
\label{sec:syn_make_targ}
|
\label{sec:syn_make_targ}
|
|
|
The default synthesis target is to synthesize the project and create .sof file in \path{syn/quartus/run} directory. Other synthesis targets are:
|
The default synthesis target is to synthesize the project and create a .sof file in the \path{syn/quartus/run} directory. Other synthesis targets are:
|
\begin{description}
|
\begin{description}
|
\item[\texttt{clean}] - remove all synthesis output files,
|
\item[\texttt{clean}] - remove all synthesis output files,
|
\item[\texttt{print\_config}] - prints projects configuration of FPGA device,
|
\item[\texttt{print\_config}] - prints project configuration of FPGA device,
|
\item[\texttt{project}] - creates quartus project files (.qpf and .qsf),
|
\item[\texttt{project}] - creates Quartus project files (.qpf and .qsf),
|
\item[\texttt{quartus}] - creates quartus project files and launches quartus IDE.
|
\item[\texttt{quartus}] - creates Quartus project files and launches the Quartus IDE.
|
\end{description}
|
\end{description}
|
|
|
\subsubsection{Synthesis makefile environment variables}
|
\subsubsection{Synthesis makefile environment variables}
|
\label{sec:syn_make_var}
|
\label{sec:syn_make_var}
|
|
|
Synthesis makefile uses couple of environment variables to setup synthesis:
|
The synthesis makefile uses a couple of environment variables to setup synthesis:
|
\begin{description}
|
\begin{description}
|
\item[\texttt{QUARTUS\_DIR}] - quartus installation directory (\path{\$(QUARTUS_DIR)/bin/quartus} should be a valid path),
|
\item[\texttt{QUARTUS\_DIR}] - Quartus installation directory (\path{\$(QUARTUS_DIR)/bin/quartus} should be a valid path),
|
\item[\texttt{FPGA\_FAMILY}] - name of the FPGA device family,
|
\item[\texttt{FPGA\_FAMILY}] - name of the FPGA device family,
|
\item[\texttt{FPGA\_PART}] - name of the FPGA device,
|
\item[\texttt{FPGA\_PART}] - name of the FPGA device,
|
\item[\texttt{V}] - when set to 1 - enables verbose output; when set to 0 - normal simulation output (0 is default).
|
\item[\texttt{V}] - when set to 1 - enables verbose output; when set to 0 - normal simulation output (0 is default).
|
\end{description}
|
\end{description}
|
|
|
No newline at end of file
|
No newline at end of file
|
