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-------------------------------------------------------------------------------
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-- Title:
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-- Project: FH-Hagenberg/HSSE: Sandbox X general use IP
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-- Author: Copyright 2006 by Markus Pfaff, Linz/Austria/Europe
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-------------------------------------------------------------------------------
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-- $LastChangedDate: 2007-01-09 08:40:02 +0100 (Di, 09 Jän 2007) $
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-- $LastChangedRevision: 415 $
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-- $LastChangedBy: pfaff $
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-- $HeadURL: file:///C:/pfaff/rpySvn/rpySvnSet5/trunk/Uebung/W06Jg04/Uebung03/unitIcs307Configurator/src/Ics307Configurator-Rtl-a.vhd $
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-- LoginNames: pfaff - Markus Pfaff, Linz/Austria/Europe
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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architecture Rtl of Ics307Configurator is
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-----------------------------------------------------------------------------
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-- register definition
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-----------------------------------------------------------------------------
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type aActivity is (Transmitting, LatchingIn, Completed);
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type aRegion is (RegionC, RegionTTL, RegionF, RegionS, RegionV, RegionR);
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subtype aBitIdx is integer range 0 to 8;
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subtype aCycleCtr is integer range 0 to 7;
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type aRegSet is record
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Activity : aActivity;
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Region : aRegion;
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BitIdx : aBitIdx;
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CycleCtr : aCycleCtr;
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Sclk : std_ulogic;
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Data : std_ulogic;
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end record aRegSet;
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signal R, NxR : aRegSet;
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constant cRinitVal : aRegSet := (
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Activity => Transmitting,
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Region => RegionC,
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BitIdx => aBitIdx'low,
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CycleCtr => aCycleCtr'low,
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Sclk => '0',
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Data => '0'
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);
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begin
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------------
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-- Registers
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------------
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Registers : process(iClk, inResetAsync)
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begin
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if (inResetAsync = cnActivated) then
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R <= cRinitVal;
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elsif ((iClk'event) and (iClk = '1')) then
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R <= NxR;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Nx State and Output Logic: Combinatorial
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-----------------------------------------------------------------------------
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NxStateAndOutput : process (
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R
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)
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begin
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---------------------------------------------------------------------------
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-- Set Nx State Defaults
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---------------------------------------------------------------------------
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NxR <= R;
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---------------------------------------------------------------------------
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-- Set Output Defaults
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---------------------------------------------------------------------------
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oStrobe <= cInactivated;
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---------------------------------------------------------------------------
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-- Consider Actual States and Inputs
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---------------------------------------------------------------------------
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case R.Activity is
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when Transmitting =>
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-- Generating Sclk
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if R.CycleCtr /= aCycleCtr'high then
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NxR.CycleCtr <= R.CycleCtr + 1;
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else
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NxR.CycleCtr <= 0;
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if R.Sclk = '0' then
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-- rising edge of Sclk
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NxR.Sclk <= '1';
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else
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-- falling edge of Sclk
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NxR.Sclk <= '0';
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-- Adjust Region and BitIdx
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if R.BitIdx = 0 then
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-- The order of regions is given in the data sheet on page 5.
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case R.Region is
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when RegionC =>
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NxR.Region <= RegionTTL;
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when RegionTTL =>
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NxR.BitIdx <= gClkFunctionSelect_R'left;
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NxR.Region <= RegionF;
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when RegionF =>
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NxR.BitIdx <= gOutputDivide_S'left;
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NxR.Region <= RegionS;
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when RegionS =>
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NxR.BitIdx <= gVcoDividerWord_VDW'left;
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NxR.Region <= RegionV;
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when RegionV =>
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NxR.BitIdx <= gReferenceDivider_RDW'left;
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NxR.Region <= RegionR;
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when RegionR =>
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NxR.Activity <= LatchingIn;
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end case;
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else
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NxR.BitIdx <= R.BitIdx - 1;
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end if;
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end if;
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end if;
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when LatchingIn =>
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oStrobe <= cActivated;
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if R.CycleCtr /= aCycleCtr'high then
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NxR.CycleCtr <= R.CycleCtr +1;
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else
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NxR.Activity <= Completed;
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end if;
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when Completed =>
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null;
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end case;
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-- Determine data output
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case R.Region is
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-- The order of regions is given in the data sheet on page 5.
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when RegionC =>
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oData <= gCrystalLoadCapacitance_C (R.BitIdx);
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when RegionTTL =>
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oData <= gOutputDutyCycleVoltage_TTL;
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when RegionF =>
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oData <= gClkFunctionSelect_R(R.BitIdx);
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when RegionS =>
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oData <= gOutputDivide_S (R.BitIdx);
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when RegionV =>
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oData <= gVcoDividerWord_VDW (R.BitIdx);
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when RegionR =>
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oData <= gReferenceDivider_RDW (R.BitIdx);
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end case;
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end process NxStateAndOutput;
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oSclk <= R.Sclk;
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end Rtl;
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