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-------------------------------------------------------------------------------
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-- Title : Programmer for ICS307
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-- Project : General IP
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-------------------------------------------------------------------------------
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-- Author : Copyright 2006: Markus Pfaff, Linz
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-- Standard : Using VHDL'93
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-------------------------------------------------------------------------------
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-- Description: Configures an ICS Serially Programmable Clock
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-- Synthesizer immediately after FPGA configuration.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.global.all;
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entity Ics307Configurator is
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generic(
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-- Default settings for 25 MHz input clk and 48 MHz on clk1
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-- Parameters in the order implied by the block diagramm on title
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-- page of data sheet. The data word given by online calculator
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-- (see data sheet page 3) is "001001000000100000000011". This
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-- data word contains the following parameters:
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-- Set for lowest crystal load capacitance,
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gCrystalLoadCapacitance_C : std_ulogic_vector(1 downto 0) := "00";
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-- divide by (3+2),
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gReferenceDivider_RDW : std_ulogic_vector(6 downto 0) := "0000011";
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-- multiply by (16+8),
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gVcoDividerWord_VDW : std_ulogic_vector(8 downto 0) := "000010000";
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-- divide by 5,
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gOutputDivide_S : std_ulogic_vector(2 downto 0) := "100";
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-- set source of Clk2 to REF clk (i.e. input clk),
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gClkFunctionSelect_R : std_ulogic_vector(1 downto 0) := "00";
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-- CMOS voltage levels for 3.3V.
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gOutputDutyCycleVoltage_TTL : std_ulogic := '1'
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);
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port(
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iClk : in std_ulogic;
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inResetAsync : in std_ulogic;
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-- 3 wire SPI interface for configuration
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oSclk : out std_ulogic;
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oData : out std_ulogic;
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oStrobe : out std_ulogic
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);
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end entity Ics307Configurator;
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