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-------------------------------------------------------------------------------
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-- Project: FH-Hagenberg/HSSE: Sandbox X general use IP
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-- Author: Copyright 2006 by Markus Pfaff, Linz/Austria/Europe
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-------------------------------------------------------------------------------
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-- $LastChangedDate: 2007-01-09 08:40:02 +0100 (Di, 09 Jän 2007) $
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-- $LastChangedRevision: 415 $
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-- $LastChangedBy: pfaff $
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-- $HeadURL: file:///C:/pfaff/rpySvn/rpySvnSet5/trunk/Uebung/W06Jg04/Uebung03/unitIcs307Configurator/src/tbIcs307Configurator-Bhv-a.vhd $
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-- LoginNames: pfaff - Markus Pfaff, Linz/Austria/Europe
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.Global.all;
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--------------------------------------------------------------------------------
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architecture Bhv of tbIcs307Configurator is
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-- component generics
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constant cClkFrequency : natural := 25E6;
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constant cIsLowPercentageOfDutyCycle : natural := 65;
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constant cInResetDuration : time := 140 ns;
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constant cStrobeFrequency : natural := 12E6;
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-- component ports
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signal Clk : std_ulogic;
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signal nResetAsync : std_ulogic;
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signal Strobe : std_ulogic;
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signal Sclk : std_ulogic;
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signal Data : std_ulogic;
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begin -- architecture Behavioral
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Ics307Configurator_1 : entity work.Ics307Configurator
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--generic map (
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-- gCrystalLoadCapacitance_C => gCrystalLoadCapacitance_C,
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-- gReferenceDivider_RDW => gReferenceDivider_RDW,
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-- gVcoDividerWord_VDW => gVcoDividerWord_VDW,
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-- gOutputDivide_S => gOutputDivide_S,
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-- gClkFunctionSelect_R => gClkFunctionSelect_R,
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-- gOutputDutyCycleVoltage_TTL => gOutputDutyCycleVoltage_TTL)
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port map (
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iClk => Clk,
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inResetAsync => nResetAsync,
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oSclk => Sclk,
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oData => Data,
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oStrobe => Strobe);
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-- reset generation
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PwrOnResetSource : entity work.PwrOnReset
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generic map (
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gInResetDuration => cInResetDuration)
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port map (
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onResetAsync => nResetAsync);
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ICS307_1: entity work.ICS307
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port map (
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iSclk => Sclk,
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iData => Data,
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iStrobe => Strobe,
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oClk1 => Clk);
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StopSim : process is
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begin
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wait for 6 ms;
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assert false
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report "MP: Simulation stopped intenionally!"
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severity failure;
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wait;
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end process StopSim;
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end architecture Bhv;
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