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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : tbCrc-bhv-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Testbench
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-- Links : Crc-Rtl-ea.vhdl
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.CRCs.all;
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entity tbCrc is
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end entity tbCrc;
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architecture bhv of tbCrc is
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signal Clk, ResetSync : std_ulogic := '1';
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signal CRC_7 : std_ulogic_vector(6 downto 0);
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signal CRC_16 : std_ulogic_vector(15 downto 0);
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signal DataToCrc_7, DataToCrc_16 : std_ulogic;
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signal CRCDataIn_7,CRCClear_7 : std_ulogic;
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signal CRCDataIn_16,CRCClear_16 : std_ulogic;
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signal SerialCRC_7, SerialCRC_16 : std_ulogic;
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signal EndOfSim : boolean := false; -- stop clock generation when true
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-- Use the negative clock edge to setup the signals in front of the positive
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-- edge. Therefore no extra clock cycle is needed.
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procedure Test (
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Data : in std_ulogic_vector;
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Valid : in std_ulogic_vector;
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signal CRC : in std_ulogic_vector;
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signal SerialCRC : in std_ulogic;
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signal CRCDataIn : out std_ulogic;
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signal DataToCrc : out std_ulogic;
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signal CRCClear : out std_ulogic) is
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variable counter : natural := 0;
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begin
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wait until Clk = '0';
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-- shift data in
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CRCClear <= '0';
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CRCDataIn <= '1';
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while (counter <= Data'high) loop
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DataToCrc <= Data(counter);
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counter := counter + 1;
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wait until Clk = '0';
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end loop;
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-- compare parallel output
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CRCDataIn <= '0';
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assert (Valid = CRC) report "CRC error." severity error;
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-- compare serial output
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counter := 0;
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while (counter <= CRC'high) loop
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assert (Valid(counter) = SerialCRC) report "Serial CRC error"
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severity error;
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counter := counter + 1;
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wait until clk = '0';
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end loop;
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-- clear the registers, not needed after shifting the serial data out
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CRCClear <= '1';
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wait until Clk = '0';
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CRCClear <= '0';
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end procedure;
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begin
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Clk <= not Clk after 10 ns when EndOfSim = false else '0';
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ResetSync <= '0' after 100 ns;
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generate_and_test7 : process is
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procedure Test7(
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Data : in std_ulogic_vector;
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Valid : in std_ulogic_vector) is
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begin
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Test(Data, Valid, CRC_7, SerialCRC_7, CRCDataIn_7, DataToCrc_7,
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CRCClear_7);
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end procedure;
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procedure Test16(
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Data : in std_ulogic_vector;
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Valid : in std_ulogic_vector) is
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begin
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Test(Data, Valid, CRC_16, SerialCRC_16, CRCDataIn_16, DataToCrc_16,
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CRCClear_16);
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end procedure;
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variable data : std_ulogic_vector(0 to (512*8)-1) := (others => '1');
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begin
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wait until (ResetSync = '0');
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Test7("0100000000000000000000000000000000000000","1001010");
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Test7("01000000000000000000000000000000000000001001010","0000000");
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Test7("0101000100000000000000000000000000000000","0101010");
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Test7("01010001000000000000000000000000000000000101010","0000000");
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Test7("0001000100000000000000000000100100000000","0110011");
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Test7("00010001000000000000000000001001000000000110011","0000000");
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Test7("000010000000000000000000000000000110101010", "0000111");
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Test7("0001110100101001011100000000111011000110000010110100101101011001001010110010101110100011101100001111001000000001100101110001000",
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"0000000");
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Test16(data, X"7FA1");
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Test16(X"1234567890ABCDEF", X"2FBC");
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Test16(X"1234567890ABCDEF2FBC", X"0000");
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Test16(X"F0F0F0F0F0F0F0F0F0F0", X"63E2");
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Test16(X"F0F0F0F0F0F0F0F0F0F063E2", X"0000");
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EndOfSim <= true;
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report "Simulation finished." severity note;
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end process;
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duv7: entity work.crc
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port map (iClk => Clk,
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iRstSync => ResetSync,
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iDataIn => CRCDataIn_7,
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iStrobe => '1',
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iClear => CRCClear_7,
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iData => DataToCrc_7,
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oParallel => CRC_7,
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oSerial => SerialCRC_7);
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duv16: entity work.crc
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generic map (gPolynom => crc16)
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port map (iClk => Clk,
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iRstSync => ResetSync,
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iDataIn => CRCDataIn_16,
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iStrobe => '1',
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iClear => CRCClear_16,
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iData => DataToCrc_16,
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oParallel => CRC_16,
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oSerial => SerialCRC_16);
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end architecture bhv;
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