Subversion Repositories sdhc-sc-core

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2010 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

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# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition

# Date created = 21:01:43  April 16, 2010

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               CRCsyn_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C35F484C8

set_global_assignment -name TOP_LEVEL_ENTITY crc

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:01:43  APRIL 16, 2010"

set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8

set_global_assignment -name VHDL_FILE "../../pkgCRCs/src/CRCs-p.vhdl"

set_global_assignment -name VHDL_FILE "../src/Crc-Rtl-ea.vhdl"

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock

set_instance_assignment -name CLOCK_SETTINGS Clock -to iClk

set_global_assignment -name ENABLE_DRC_SETTINGS OFF

set_global_assignment -name MISC_FILE "Z:/SD-CORE/src/grpCrc/unitCrc/syn/CRCsyn.dpf"

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF

set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF

set_global_assignment -name USE_CONFIGURATION_DEVICE ON

set_global_assignment -name GENERATE_RBF_FILE ON

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top