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Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpCyclone2/] [unitWriteDataFifo/] [src/] [WriteDataFifo_waveforms.html] - Diff between revs 123 and 185

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	`<html>`
	`<head>`
	`<title>Sample Waveforms for "WriteDataFifo.vhd" </title>`
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	`<body>`
	`<h2><CENTER>Sample behavioral waveforms for design file "WriteDataFifo.vhd" </CENTER></h2>`
	`<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "WriteDataFifo.vhd". The design "WriteDataFifo.vhd" has a depth of 512 words of 32 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>`
	`<CENTER><img src=WriteDataFifo_wave0.jpg> </CENTER>`
	`<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>`
	`<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>`
	`<CENTER><img src=WriteDataFifo_wave1.jpg> </CENTER>`
	`<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>`
	`<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>`
	`<P></P>`
	`</body>`
	`</html>`

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