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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : tbRs232Tx-Bhv-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Testbench for Rs232 Transmitter
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-- Links : Rs232Tx-Rtl-ea.vhdl
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Global.all;
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use work.Rs232.all;
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entity tbRs232Tx is
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end entity tbRs232Tx;
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architecture Bhv of tbRs232Tx is
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constant cClkFrequency : natural := 25E6;
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constant cBaudRate : natural := 9600;
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constant cResetTime : time := 1 sec / cClkFrequency * 3;
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signal Clk : std_ulogic := cActivated;
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signal nResetAsync : std_ulogic := cnActivated;
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signal iRs232Tx : aiRs232Tx;
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signal oRs232Tx : aoRs232Tx;
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signal Finished : std_ulogic := cInactivated;
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begin
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Clk <= not Clk after 1 sec / cClkFrequency / 2 when Finished = cInactivated;
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nResetAsync <= cnInactivated after cResetTime;
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Stimuli : process is
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begin
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iRs232Tx.Transmit <= cActivated;
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iRs232Tx.Data <= (others => '-');
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iRs232Tx.DataAvailable <= cInactivated;
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wait for cResetTime;
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wait for 1 us;
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iRs232Tx.Data <= X"5A";
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iRs232Tx.DataAvailable <= cActivated;
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wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
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iRs232Tx.DataAvailable <= cInactivated;
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wait until Clk = cActivated;
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wait until Clk = cActivated;
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iRs232Tx.Data <= X"7E";
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iRs232Tx.DataAvailable <= cActivated;
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wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
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iRs232Tx.Data <= X"96";
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wait until Clk = cActivated;
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wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
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iRs232Tx.DataAvailable <= cInactivated;
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wait for 500 us;
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iRs232Tx.Data <= X"97";
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iRs232Tx.DataAvailable <= cActivated;
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wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
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iRs232Tx.DataAvailable <= cInactivated;
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iRs232Tx.Transmit <= cInactivated;
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wait for 5 ms;
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Finished <= cActivated;
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wait;
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end process Stimuli;
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StrobeGen_Rs232 : entity work.StrobeGen
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generic map (
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gClkFrequency => cClkFrequency,
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gStrobeCycleTime => 1 sec / cBaudRate)
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port map (
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iClk => Clk,
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inResetAsync => nResetAsync,
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oStrobe => iRs232Tx.BitStrobe);
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DUT: entity work.Rs232Tx
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generic map (
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gDataBitWidth => 8
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)
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port map (
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iClk => Clk,
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inResetAsync => nResetAsync,
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iRs232Tx => iRs232Tx,
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oRs232Tx => oRs232Tx
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);
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end architecture Bhv;
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