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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdCardSynchronizer-Rtl-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Synchronizes SD Bus inputs
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.global.all;
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entity SdCardSynchronizer is
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generic (
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gSyncCount : natural := 1
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);
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port (
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iClk : in std_ulogic;
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iRstSync : in std_ulogic;
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iStrobe : in std_ulogic;
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iCmd : in std_logic;
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iData : in std_logic_vector(3 downto 0);
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oCmdSync : out std_ulogic;
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oDataSync : out std_ulogic_vector(3 downto 0)
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);
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end entity SdCardSynchronizer;
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architecture Rtl of SdCardSynchronizer is
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type aDataSync is array (0 to gSyncCount - 1) of std_ulogic_vector(3 downto 0);
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signal CmdSync : std_ulogic_vector(gSyncCount - 1 downto 0);
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signal DataSync : aDataSync;
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begin
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-- Registers
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Reg : process (iClk, iRstSync)
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begin
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if (rising_edge(iClk)) then
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-- synchronous reset
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if (iRstSync = cActivated) then
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CmdSync <= (others => '0');
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DataSync <= (others => (others => '0'));
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else
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if (iStrobe = cActivated) then
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-- register input data
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CmdSync(0) <= iCmd;
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DataSync(0) <= std_ulogic_vector(iData);
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-- additional synchronization FFs
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for i in 1 to gSyncCount - 1 loop
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CmdSync(i) <= CmdSync(i - 1);
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DataSync(i) <= DataSync(i - 1);
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end loop;
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end if;
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end if;
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end if;
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end process Reg;
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-- output the last registers
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oCmdSync <= CmdSync(gSyncCount - 1);
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oDataSync <= DataSync(gSyncCount - 1);
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end architecture Rtl;
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