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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdClockMaster-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description : Generation of SDClk and internal strobes
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-- Links :
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--
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architecture Rtl of SdClockMaster is
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subtype aCounter is unsigned(1 downto 0); -- maximal division through 4
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type aRegSet is record
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Counter : aCounter;
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Clk : std_ulogic;
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Strobe : std_ulogic;
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InStrobe : std_ulogic;
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HighSpeed : std_ulogic;
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end record aRegSet;
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signal R,NxR : aRegSet;
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begin
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-- connect outputs with registers
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oSdCardClk <= R.Clk;
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oSdStrobe <= R.Strobe;
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oSdInStrobe <= R.InStrobe;
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Regs : process (iClk, iRstSync)
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begin
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if (rising_edge(iClk)) then
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-- synchronous reset
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if (iRstSync = cActivated) then
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R.Counter <= to_unsigned(0, R.Counter'length);
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R.Clk <= cInactivated;
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R.Strobe <= cInactivated;
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R.InStrobe <= cInactivated;
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R.HighSpeed <= cInactivated;
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else
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R <= NxR;
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end if;
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end if;
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end process Regs;
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Comb : process (R, iHighSpeed, iDisable)
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begin
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-- defaults
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NxR <= R;
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case iDisable is
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when cInactivated =>
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NxR.Counter <= R.Counter + 1;
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-- generate clock and strobe
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case R.HighSpeed is
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when cInactivated => -- default mode
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NxR.Clk <= R.Counter(1);
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case R.Counter is
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when "00" | "11" =>
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NxR.Strobe <= cInactivated;
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NxR.InStrobe <= cInactivated;
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when "10" =>
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NxR.Strobe <= cActivated;
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NxR.InStrobe <= cInactivated;
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when "01" =>
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NxR.InStrobe <= cActivated;
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NxR.Strobe <= cInactivated;
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when others =>
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NxR.Strobe <= 'X';
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NxR.InStrobe <= 'X';
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end case;
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when cActivated => -- High-Speed mode
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NxR.Clk <= R.Counter(0);
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NxR.Strobe <= R.Counter(0);
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NxR.InStrobe <= R.Counter(0);
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when others =>
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NxR.Clk <= 'X';
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end case;
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-- switch speeds and increment counter
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case R.HighSpeed is
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when cInactivated =>
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if (R.Counter = 3) then
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NxR.HighSpeed <= iHighSpeed;
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end if;
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when cActivated =>
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if (R.Counter(0) = '1') then
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NxR.HighSpeed <= iHighSpeed;
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NxR.Counter <= "00";
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end if;
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when others =>
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NxR.HighSpeed <= 'X';
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end case;
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when cActivated =>
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-- disable strobes and do not increment the counter
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NxR.Strobe <= cInactivated;
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NxR.InStrobe <= cInactivated;
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when others =>
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NxR.Clk <= 'X';
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NxR.Strobe <= 'X';
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NxR.InStrobe <= 'X';
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end case;
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end process Comb;
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end architecture Rtl;
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