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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdCmd-Rtl-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : FSM for low level sending of SD commands and receiving responses
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-- Links : SD Spec 2.00
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.Global.all;
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use work.Sd.all;
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use work.CRCs.all;
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entity SdCmd is
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port (
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iClk : in std_ulogic; -- Clk, rising edge
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iRstSync : in std_ulogic; -- Reset, synchronous active high
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iStrobe : in std_ulogic; -- Strobe to send data
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iFromController : in aSdCmdFromController;
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oToController : out aSdCmdToController;
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-- SDCard
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iCmd : in aiSdCmd;
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oCmd : out aoSdCmd
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);
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end entity SdCmd;
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architecture Rtl of SdCmd is
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type aSdCmdState is (idle, sending, receiving);
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type aRegion is (startbit, transbit, cmdid, arg, cid, crc, endbit, waitstate);
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subtype aCounter is unsigned(integer(log2(real(128))) - 1 downto 0);
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type aRegSet is record
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State : aSdCmdState;
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Region : aRegion;
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Counter : aCounter;
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ReceivedToken : aSdCmdToken;
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Cid : aSdRegCID;
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end record aRegSet;
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constant cDefaultRegSet : aRegSet := (
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State => idle,
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Region => startbit,
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Counter => to_unsigned(0, aCounter'length),
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ReceivedToken => cDefaultSdCmdToken,
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Cid => cDefaultSdRegCID);
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type aOutputRegSet is record
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Controller : aSdCmdToController;
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Cmd : aoSdCmd;
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end record aOutputRegSet;
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constant cDefaultOutputRegSet : aOutputRegSet := (
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Controller => cDefaultSdCmdToController,
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Cmd => (Cmd => '0',
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En => '0'));
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type aCrcOut is record
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Clear : std_ulogic;
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DataIn : std_ulogic;
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Data : std_ulogic;
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end record aCrcOut;
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constant cDefaultCrcOut : aCrcOut := (
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Clear => cInactivated,
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DataIn => cInactivated,
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Data => cInactivated);
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signal SerialCrc, CrcCorrect : std_ulogic;
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signal CrcOut : aCrcOut;
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signal R, NextR : aRegSet;
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signal O, NextO : aOutputRegSet;
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begin
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oToController <= O.Controller;
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oCmd <= O.Cmd;
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-- State register
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CmdStateReg : process (iClk)
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begin
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if iClk'event and iClk = cActivated then
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if iRstSync = cActivated then
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R <= cDefaultRegSet;
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O <= cDefaultOutputRegSet;
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else
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if (iStrobe = cActivated) then
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R <= NextR;
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O <= NextO;
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end if;
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end if;
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end if;
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end process CmdStateReg;
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-- Comb. process
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NextStateAndOutput : process (iFromController, iCmd.Cmd, SerialCrc, CrcCorrect, iStrobe, R)
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procedure NextStateWhenAllSent (constant nextlength : in natural; constant toRegion : in aRegion) is
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begin
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if (R.Counter > 0) then
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NextR.Counter <= R.Counter - 1;
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else
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NextR.Counter <= to_unsigned(nextlength, NextR.Counter'length);
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NextR.Region <= toRegion;
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end if;
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end procedure NextStateWhenAllSent;
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procedure ShiftIntoCrc(constant data : in std_ulogic) is
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begin
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CrcOut.DataIn <= cActivated;
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CrcOut.Data <= data;
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end procedure;
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procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
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begin
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NextO.Cmd.En <= cActivated;
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NextO.Cmd.Cmd <= container(to_integer(R.Counter));
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ShiftIntoCrc(container(to_integer(R.Counter)));
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NextStateWhenAllSent(nextlength, toRegion);
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end procedure SendBitsAndCalcCrc;
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procedure RecvBitsAndCalcCrc (signal container : out std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
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begin
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container(to_integer(R.Counter)) <= iCmd.Cmd;
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ShiftIntoCrc(iCmd.Cmd);
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NextStateWhenAllSent(nextlength, toRegion);
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end procedure RecvBitsAndCalcCrc;
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begin
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-- defaults
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NextR <= R;
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NextO <= cDefaultOutputRegSet;
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NextO.Controller.Content <= R.ReceivedToken.content;
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NextO.Controller.Cid <= R.Cid;
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CrcOut <= cDefaultCrcOut;
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case R.State is
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when idle =>
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-- Start receiving or start transmitting
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if (iCmd.Cmd = cSdStartBit) then
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-- Start receiving
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ShiftIntoCrc(iCmd.Cmd);
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NextR.ReceivedToken.startbit <= iCmd.Cmd;
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NextR.State <= receiving;
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NextR.Region <= transbit;
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elsif (iFromController.Valid = cActivated) then
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-- Start sending
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NextR.State <= sending;
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NextR.Region <= startbit;
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end if;
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when sending =>
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NextO.Cmd.En <= cActivated;
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case R.Region is
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when startbit =>
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NextO.Cmd.Cmd <= cSdStartBit;
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NextR.Region <= transbit;
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ShiftIntoCrc(cSdStartBit);
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when transbit =>
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NextO.Cmd.Cmd <= cSdTransBitHost;
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NextR.Counter <= to_unsigned(iFromController.Content.id'high, aCounter'length);
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NextR.Region <= cmdid;
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ShiftIntoCrc(cSdTransBitHost);
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when cmdid =>
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SendBitsAndCalcCrc(iFromController.Content.id, arg, iFromController.Content.arg'high);
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when arg =>
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SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);
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when crc =>
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NextO.Cmd.Cmd <= SerialCrc;
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if (R.Counter > 0) then
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NextR.Counter <= R.Counter - 1;
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else
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NextR.Region <= endbit;
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NextO.Controller.Ack <= cActivated;
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end if;
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when endbit =>
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NextO.Cmd.Cmd <= cSdEndBit;
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NextR.Region <= waitstate;
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when waitstate =>
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NextO.Cmd.En <= cInactivated;
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NextR.State <= idle;
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NextR.Region <= startbit;
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when others =>
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report "SdCmd: Region not handled" severity error;
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end case;
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when receiving =>
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NextO.Controller.Receiving <= cActivated;
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case R.Region is
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when transbit =>
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NextR.ReceivedToken.transbit <= iCmd.Cmd;
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NextR.Counter <= to_unsigned(NextR.ReceivedToken.Content.id'high, NextR.Counter'length);
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NextR.Region <= cmdid;
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ShiftIntoCrc(iCmd.Cmd);
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when cmdid =>
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if (iFromController.ExpectCID = cInactivated) then
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RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, arg, NextR.ReceivedToken.Content.arg'high);
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elsif (iFromController.ExpectCID = cActivated) then
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RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, cid, cCIDLength-8);
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CrcOut.Clear <= cActivated;
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end if;
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when arg =>
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RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.arg, crc, crc7'high-1);
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when cid =>
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NextR.Cid <= UpdateCID(R.Cid, iCmd.Cmd, to_integer(R.Counter)+8);
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ShiftIntoCrc(iCmd.Cmd);
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NextStateWhenAllSent(crc7'high-1, crc);
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when crc =>
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NextR.ReceivedToken.crc7(to_integer(R.Counter)) <= iCmd.Cmd;
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ShiftIntoCrc(iCmd.Cmd);
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if (R.Counter > 0) then
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NextR.Counter <= R.Counter - 1;
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else
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NextR.Region <= endbit;
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end if;
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when endbit =>
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NextR.ReceivedToken.endbit <= iCmd.Cmd;
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-- check
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if (iFromController.CheckCrc = cActivated) then
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if (CrcCorrect = cActivated and R.ReceivedToken.transbit = cSdTransBitSlave) then
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NextO.Controller.Valid <= cActivated;
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else
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NextO.Controller.Err <= cActivated;
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end if;
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else
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NextO.Controller.Valid <= cActivated;
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end if;
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NextR.State <= idle;
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NextR.Region <= startbit;
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when others =>
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report "SdCmd : Region not handled" severity error;
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end case;
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when others =>
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report "SdCmd: State not handled" severity error;
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end case;
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end process NextStateAndOutput;
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CRC7_inst: entity work.Crc
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generic map(
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gPolynom => crc7)
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port map(
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iClk => iClk,
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iRstSync => iRstSync,
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iClear => CrcOut.Clear,
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iStrobe => iStrobe,
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iDataIn => CrcOut.DataIn,
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iData => CrcOut.Data,
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oIsCorrect => CrcCorrect,
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oSerial => SerialCrc);
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end architecture Rtl;
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No newline at end of file
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No newline at end of file
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