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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdData-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description : FSM for sending and receiving data via the SD Bus
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-- Links : SD Spec 2.00
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--
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architecture Rtl of SdData is
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type aState is (idle, send, receive, crcstatus, checkbusy); -- overall states
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type aRegion is (startbit, data, crc, endbit); -- regions in send and receive state
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subtype aCounter is unsigned(LogDualis(512*8)-1 downto 0); -- bit counter
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subtype aCrcStatus is std_ulogic_vector(2 downto 0);
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-- all registers
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type aReg is record
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State : aState;
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Region : aRegion;
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Counter : aCounter;
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Mode : aSdDataBusMode; -- standard or wide SD mode
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Word : aWord; -- temporary save for data to write to the read fifo
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WordInvalid : std_ulogic; -- after starting receiving we have to wait for the word to be valid before it can be written to the read fifo
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-- outputs
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Data : aoSdData;
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Controller : aSdDataToController;
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ReadWriteFifo : aoReadFifo;
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WriteReadFifo : aoWriteFifo;
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DisableSdClk : std_ulogic;
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CrcStatus : aCrcStatus;
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end record aReg;
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-- default value for registers
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constant cDefaultReg : aReg := (
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State => idle,
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Region => startbit,
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Counter => (others => '0'),
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Mode => standard,
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WordInvalid => cInactivated,
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Word => (others => '0'),
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Data => cDefaultSdData,
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Controller => cDefaultSdDataToController,
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ReadWriteFifo => cDefaultoReadFifo,
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WriteReadFifo => cDefaultoWriteFifo,
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DisableSdClk => cInactivated,
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CrcStatus => (others => '0'));
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type aCrcOut is record
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DataIn : std_ulogic;
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Data : std_ulogic_vector(3 downto 0);
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end record aCrcOut;
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constant cDefaultCrcOut : aCrcOut := (
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DataIn => cInactivated,
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Data => (others => '0'));
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type aCrcIn is record
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Correct : std_ulogic_vector(3 downto 0);
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Serial : std_ulogic_vector(3 downto 0);
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end record aCrcIn;
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signal CrcIn : aCrcIn;
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signal CrcOut : aCrcOut;
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signal CrcDataIn : std_ulogic_vector(3 downto 0);
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signal R, NextR : aReg;
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-- aliases for bits, bytes and words from the bit counter
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alias RBitC is R.Counter(LogDualis(8)-1 downto 0);
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alias RByteC is R.Counter(LogDualis(4)+LogDualis(8)-1 downto LogDualis(8));
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alias RWordC is R.Counter(R.Counter'high downto LogDualis(4)+LogDualis(8));
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alias RBitInWordC is R.Counter(LogDualis(32)-1 downto 0);
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begin
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-- registered outputs
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oData <= R.Data;
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oSdDataToController <= R.Controller;
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oReadWriteFifo <= R.ReadWriteFifo;
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oWriteReadFifo <= R.WriteReadFifo;
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oDisableSdClk <= R.DisableSdClk;
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Regs : process (iClk)
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begin
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-- clock event
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if (iClk'event and iClk = cActivated) then
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if (iRstSync = cActivated) then
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R <= cDefaultReg;
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else
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-- synchronous enable
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if (iStrobe = cActivated) then
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R <= NextR;
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end if;
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-- rdreq and wrreq have to be exactly one clock cycle wide
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R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe;
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R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe;
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-- Clock has to be disabled before the next strobe is generated
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R.DisableSdClk <= NextR.DisableSdClk;
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end if;
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end if;
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end process Regs;
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-- Calculate the next state and output
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Comb : process (iData, iSdDataFromController, CrcIn, iReadWriteFifo, iWriteReadFifo, R)
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--------------------------------------------------------------------------------
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-- Handle accessing the fifo
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--------------------------------------------------------------------------------
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procedure HandleFifoAccess (signal status : in std_ulogic; signal req : out std_ulogic) is
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begin
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if (status = cActivated) then
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-- stop data transfer to card and wait for a change of the fifo status
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report "Fifo not ready, waiting" severity note;
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NextR.DisableSdClk <= cActivated;
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NextR.Counter <= R.Counter;
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req <= cInactivated;
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else
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-- enable request and continue transfer with the sd card
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NextR.DisableSdClk <= cInactivated;
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req <= cActivated;
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end if;
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end procedure HandleFifoAccess;
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--------------------------------------------------------------------------------
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-- Set crc outputs so data is shifted in
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--------------------------------------------------------------------------------
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procedure ShiftIntoCrc (constant data : in aSdData) is
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begin
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CrcOut.Data <= data;
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CrcOut.DataIn <= cActivated;
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end procedure ShiftIntoCrc;
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--------------------------------------------------------------------------------
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-- Send data to card and calculate crc
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--------------------------------------------------------------------------------
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procedure SendBitsAndShiftIntoCrc (constant data : in aSdData) is
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begin
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ShiftIntoCrc(data);
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NextR.Data.Data <= data;
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end procedure SendBitsAndShiftIntoCrc;
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--------------------------------------------------------------------------------
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-- Calculate the next counter and region
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-- Handles loading next data from fifo or writing data to fifo as well
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--------------------------------------------------------------------------------
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procedure CalcNextAndHandleData (constant send : boolean) is
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-- End and decrement values for standard mode
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variable BitEnd : integer := 0;
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variable BitDec : integer := 1;
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begin
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-- reset variables if wide mode is used
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if R.Mode = wide then
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BitEnd := 3;
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BitDec := 4;
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end if;
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if (RBitC = BitEnd) then
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-- Byte finished, switch to next byte starting with MSBit
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NextR.Counter <= R.Counter + (16 - BitDec);
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if (RByteC = 3) then
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-- Word finished
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NextR.WordInvalid <= cInactivated; -- received words are no longer invalid
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if (RWordC = 127) then
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-- whole block finished, send crc next
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NextR.Region <= crc;
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NextR.Counter <= to_unsigned(0, aCounter'length);
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else
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if (send = true) then
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-- save next word to send from fifo
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NextR.Word <= iReadWriteFifo.q;
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end if;
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end if;
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end if;
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else
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NextR.Counter <= R.Counter - BitDec; -- switch to next bits (MSBit to LSBit)
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end if;
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if (send = true) then
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if ((RBitC = BitEnd + BitDec and RByteC = 3 and RWordC < 127)) then
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-- current word almost sent, request next word to send from fifo
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HandleFifoAccess(iReadWriteFifo.rdempty, NextR.ReadWriteFifo.rdreq);
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end if;
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else
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if (RByteC = 0 and RBitC = 7 and R.WordInvalid = cInactivated and iSdDataFromController.DisableRb = cInactivated) then
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-- received word is valid, save it to ram
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NextR.WriteReadFifo.data <= R.Word;
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HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
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end if;
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end if;
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end procedure CalcNextAndHandleData;
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--------------------------------------------------------------------------------
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-- Calculate the bit address in widewidth mode
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--------------------------------------------------------------------------------
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impure
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function IsBitAddrInRangeWideWidth (constant addr : in natural) return boolean is
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variable curHighAddr : integer;
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begin
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-- calculate current address (of the high bit in case of wide mode)
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-- widewidth receiving counts from an offset to 4096
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-- and the bit counter is reversed
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curHighAddr := (127 - to_integer(RWordC)) * 32 + (3 - to_integer(RByteC)) * 8 + to_integer(RBitC);
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if (R.Mode = standard) then
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return curHighAddr = addr;
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else
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return curHighAddr >= addr and curHighAddr - 3 <= addr;
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end if;
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end function IsBitAddrInRangeWideWidth;
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--------------------------------------------------------------------------------
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-- Get specific bit from data vector
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--------------------------------------------------------------------------------
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impure
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function GetBitFromData (constant addr : in natural) return std_ulogic is
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begin
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if (R.Mode = standard) then
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return iData.Data(0);
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else
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return iData.Data(addr mod 4);
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end if;
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end function GetBitFromData;
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variable temp : std_ulogic_vector(3 downto 0) := "0000";
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begin
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-- default assignments
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NextR <= R;
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NextR.Data.En <= (others => cInactivated);
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NextR.Controller <= cDefaultSdDataToController;
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NextR.Controller.WideMode <= R.Controller.WideMode;
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NextR.Controller.SpeedBits.HighSpeedSupported <= R.Controller.SpeedBits.HighSpeedSupported;
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NextR.Controller.SpeedBits.SwitchFunctionOK <= R.Controller.SpeedBits.SwitchFunctionOK;
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NextR.ReadWriteFifo <= cDefaultoReadFifo;
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NextR.WriteReadFifo <= cDefaultoWriteFifo;
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CrcOut <= cDefaultCrcOut;
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case R.State is
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when idle =>
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-- check if card signals that it is busy (the controller has to enable this check)
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if (iSdDataFromController.CheckBusy = cActivated) then
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NextR.State <= crcstatus;
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NextR.Region <= startbit;
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NextR.Counter <= (others => '0');
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elsif (R.Mode = wide and iData.Data = cSdStartBits) or (R.Mode = standard and iData.Data(0) = cSdStartBit) then
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-- start receiving
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NextR.Region <= data;
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NextR.State <= receive;
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NextR.Counter <= to_unsigned(7,aCounter'length);
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NextR.WordInvalid <= cActivated;
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-- which kind of response is expected?
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if (iSdDataFromController.DataMode = widewidth) then
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if (iSdDataFromController.ExpectBits = ScrBits) then
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NextR.Counter <= to_unsigned(cScrBitsCount, aCounter'length);
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elsif (iSdDataFromController.ExpectBits = SwitchFunctionBits) then
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NextR.Counter <= to_unsigned(cSwitchFunctionBitsCount, aCounter'length);
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end if;
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end if;
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elsif (iSdDataFromController.Valid = cActivated) then
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-- sending requested by controller
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case iReadWriteFifo.rdempty is
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when cActivated =>
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-- no data is available to send -> stall
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report "Fifo empty, waiting for data" severity note;
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NextR.DisableSdClk <= cActivated;
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when cInactivated =>
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-- data is available, start sending
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NextR.State <= send;
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NextR.Region <= startbit;
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NextR.ReadWriteFifo.rdreq <= cActivated;
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NextR.DisableSdClk <= cInactivated;
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NextR.Counter <= to_unsigned(7, aCounter'length);
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when others =>
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report "rdempty invalid" severity error;
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end case;
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else
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-- switch between standard and wide mode only if nothing else is going on
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NextR.Mode <= iSdDataFromController.Mode;
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end if;
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when crcstatus =>
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case R.Region is
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when startbit =>
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if (iData.Data(0) = cSdStartBit) then
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NextR.Region <= data;
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end if;
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when data =>
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NextR.CrcStatus(to_integer(R.Counter)) <= iData.Data(0);
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NextR.Counter <= R.Counter + 1;
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if (R.Counter = 2) then
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NextR.Region <= endbit;
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end if;
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when endbit =>
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if (R.CrcStatus /= "010") then
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NextR.Controller.Err <= cActivated;
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NextR.State <= idle;
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else
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NextR.State <= checkbusy;
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end if;
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when others =>
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report "Invalid state reached" severity error;
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end case;
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when checkbusy =>
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NextR.Controller.Busy <= cActivated;
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if (iData.Data(0) = cActivated) then
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NextR.Controller.Valid <= cActivated;
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NextR.State <= idle;
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end if;
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when send =>
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-- Handle the data enable signal
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case R.Mode is
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when wide =>
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NextR.Data.En <= (others => cActivated);
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when standard =>
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NextR.Data.En <= "0001";
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when others =>
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report "Invalid SDData mode" severity error;
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NextR.Data.En <= (others => 'X');
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end case;
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case R.Region is
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when startbit =>
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SendBitsAndShiftIntoCrc(cSdStartBits);
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NextR.Region <= data;
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-- save data to send from fifo
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NextR.Word <= iReadWriteFifo.q;
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when data =>
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case R.Mode is
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when wide =>
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for i in 0 to 3 loop
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temp(3 - i) := R.Word(to_integer(RBitInWordC) - i);
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end loop;
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when standard =>
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temp := "---" & R.Word(to_integer(RBitInWordC));
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when others =>
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temp := "XXXX";
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end case;
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SendBitsAndShiftIntoCrc(temp);
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CalcNextAndHandleData(true);
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when crc =>
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NextR.Data.Data <= CrcIn.Serial;
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if (R.Counter = 15) then
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-- all crc bits sent
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NextR.Counter <= to_unsigned(0, aCounter'length);
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NextR.Region <= endbit;
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NextR.Controller.Ack <= cActivated;
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else
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NextR.Counter <= R.Counter + 1;
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end if;
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when endbit =>
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NextR.Data.Data <= cSdEndBits;
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NextR.State <= idle;
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when others =>
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report "Region not handled" severity error;
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end case;
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when receive =>
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case R.Region is
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when data =>
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-- save received data to temporary word register
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case R.Mode is
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when standard =>
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NextR.Word(to_integer(RBitInWordC)) <= iData.Data(0);
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when wide =>
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for i in 0 to 3 loop
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NextR.Word(to_integer(RBitInWordC) - i) <= iData.Data(3 - i);
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end loop;
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when others =>
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report "Unhandled mode" severity error;
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end case;
|
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|
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ShiftIntoCrc(std_ulogic_vector(iData.Data));
|
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CalcNextAndHandleData(false);
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-- check responses
|
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if (iSdDataFromController.DataMode = widewidth) then
|
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if (iSdDataFromController.ExpectBits = ScrBits) then
|
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if (IsBitAddrInRangeWideWidth(cWideModeBitAddr)) then
|
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NextR.Controller.WideMode <= GetBitFromData(cWideModeBitAddr);
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end if;
|
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end if;
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|
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if (iSdDataFromController.ExpectBits = SwitchFunctionBits) then
|
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if (IsBitAddrInRangeWideWidth(cHighSpeedBitAddr)) then
|
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NextR.Controller.SpeedBits.HighSpeedSupported <= GetBitFromData(cHighSpeedBitAddr);
|
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elsif (IsBitAddrInRangeWideWidth(cSwitchFunctionBitLowAddr)) then
|
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NextR.Controller.SpeedBits.SwitchFunctionOK <= iData.Data;
|
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end if;
|
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end if;
|
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end if;
|
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|
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when crc =>
|
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-- save last word to ram
|
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ShiftIntoCrc(std_ulogic_vector(iData.Data));
|
|
|
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if (R.Counter = 15) then
|
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-- all 16 crc bits received
|
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NextR.Region <= endbit;
|
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else
|
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NextR.Counter <= R.Counter + 1;
|
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|
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if (R.Counter = 0 and iSdDataFromController.DisableRb = cInactivated) then
|
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HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
|
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NextR.WriteReadFifo.data <= R.Word;
|
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end if;
|
|
end if;
|
|
|
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when endbit =>
|
|
-- in standard mode all unused crcs are correct, because no data was shifted in
|
|
if (CrcIn.Correct = "1111") then
|
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NextR.Controller.Valid <= cActivated;
|
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else
|
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NextR.Controller.Err <= cActivated;
|
|
end if;
|
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|
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NextR.Region <= startbit;
|
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NextR.State <= idle;
|
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|
|
when others =>
|
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report "Region not handled" severity error;
|
|
end case;
|
|
|
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when others =>
|
|
report "State not handled" severity error;
|
|
end case;
|
|
|
|
end process Comb;
|
|
|
|
CrcDataIn <= (others => CrcOut.DataIn) when R.Mode = wide else "000" & CrcOut.DataIn;
|
|
|
|
crcs: for idx in 3 downto 0 generate
|
|
|
|
CRC_inst : entity work.Crc
|
|
generic map (
|
|
gPolynom => crc16
|
|
)
|
|
port map (
|
|
iClk => iClk,
|
|
iRstSync => iRstSync,
|
|
iStrobe => iStrobe,
|
|
iClear => cInactivated,
|
|
iDataIn => CrcDataIn(idx),
|
|
iData => CrcOut.Data(idx),
|
|
oIsCorrect => CrcIn.Correct(idx),
|
|
oSerial => CrcIn.Serial(idx)
|
|
);
|
|
|
|
end generate crcs;
|
|
|
|
end architecture Rtl;
|
|
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No newline at end of file
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No newline at end of file
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