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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdWbSlave-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description : Wishbone interface of SDHC-SC-Core
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-- Links :
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--
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architecture Rtl of SdWbSlave is
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type aWbState is (idle, ClassicWrite, ClassicRead);
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type aSdIntState is (idle, newOperation);
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type aReadBufferState is (invalid, readreq, latchdata, valid);
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type aRegs is record
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WbState : aWbState; -- state of the wb interface
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SdIntState : aSdIntState; -- state of the sd controller interface
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OperationBlock : aOperationBlock; -- Operation for the SdController
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ReqOperation : std_ulogic; -- Register for catching edges on the SdController ReqOperationEdge line
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ReadBuffer : aData;
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ReadBufferState : aReadBufferState;
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-- Register outputs
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oWbDat : aSdWbSlaveDataOutput;
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oWbCtrl : aWbSlaveCtrlOutput;
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oController : aSdWbSlaveToSdController;
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oWriteFifo : aoWriteFifo;
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oReadFifo : aoReadFifo;
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end record aRegs;
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constant cDefaultRegs : aRegs := (
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WbState => idle,
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SdIntState => idle,
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OperationBlock => cDefaultOperationBlock,
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ReqOperation => cInactivated,
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oWbDat => (Dat => (others => 'X')),
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oWbCtrl => cDefaultWbSlaveCtrlOutput,
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oController => cDefaultSdWbSlaveToSdController,
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oWriteFifo => cDefaultoWriteFifo,
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oReadFifo => cDefaultoReadFifo,
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ReadBuffer => (others => '0'),
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ReadBufferState => invalid);
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signal R, NxR : aRegs;
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begin
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oWbDat <= R.oWbDat;
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oWbCtrl <= R.oWbCtrl;
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oController <= R.oController;
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oWriteFifo <= R.oWriteFifo;
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oReadFifo <= R.oReadFifo;
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WbStateReg : process (iClk, iRstSync)
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begin
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if (iClk'event and iClk = cActivated) then
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if (iRstSync = cActivated) then -- sync. reset
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R <= cDefaultRegs;
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else
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R <= NxR;
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end if;
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end if;
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end process WbStateReg ;
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WbStateAndOutputs : process (iWbCtrl, iWbDat, iController, iWriteFifo, iReadFifo, R)
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begin
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-- Default Assignments
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NxR <= R;
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NxR.oWbDat.Dat <= (others => 'X');
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NxR.oWbCtrl <= cDefaultWbSlaveCtrlOutput;
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NxR.oWriteFifo <= cDefaultoWriteFifo;
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case R.ReadBufferState is
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when invalid =>
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-- is new data available?
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if (iReadFifo.rdempty = cInactivated) then
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NxR.oReadFifo.rdreq <= cActivated;
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NxR.ReadBufferState <= readreq;
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end if;
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when readreq =>
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-- readreq was sent, data is available next cycle
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NxR.oReadFifo.rdreq <= cInactivated;
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NxR.ReadBufferState <= latchdata;
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when latchdata =>
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NxR.ReadBuffer <= iReadFifo.q;
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NxR.ReadBufferState <= valid;
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when valid =>
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-- do nothing, wishbone statemachine sets the state to invalid when it used it
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null;
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when others =>
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report "Error: Invalid ReadBufferState" severity error;
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end case;
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-- Determine next state
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case R.WbState is
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when idle =>
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if iWbCtrl.Cyc = cActivated and iWbCtrl.Stb = cActivated then
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case iWbCtrl.Cti is
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when cCtiClassicCycle =>
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case iWbCtrl.We is
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when cInactivated =>
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-- perform a ClassicRead
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NxR.oWbCtrl.Ack <= cActivated;
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NxR.WbState <= ClassicRead;
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if (iWbDat.Sel = "1") then
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case iWbDat.Adr is
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when cOperationAddr =>
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NxR.oWbDat.Dat <= R.OperationBlock.Operation;
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when cStartAddrAddr =>
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NxR.oWbDat.Dat <= R.OperationBlock.StartAddr;
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when cEndAddrAddr =>
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NxR.oWbDat.Dat <= R.OperationBlock.EndAddr;
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when cReadDataAddr =>
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-- check if data is available
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case R.ReadBufferState is
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when valid =>
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-- use buffered data
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NxR.oWbDat.Dat <= R.ReadBuffer;
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NxR.ReadBufferState <= invalid;
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when latchdata =>
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-- use input directly
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NxR.oWbDat.Dat <= iReadFifo.q;
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NxR.ReadBufferState <= invalid;
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when readreq =>
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-- no data available, insert a waitstate
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NxR.oWbCtrl.Ack <= cInactivated;
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NxR.WbState <= idle;
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when invalid =>
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-- no data available, insert a waitstate
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NxR.oWbCtrl.Ack <= cInactivated;
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NxR.WbState <= idle;
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when others =>
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report "Invalid ReadBufferState" severity error;
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end case;
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when others =>
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report "Read to an invalid address" severity warning;
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NxR.oWbCtrl.Err <= cActivated;
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NxR.oWbCtrl.Ack <= cInactivated;
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end case;
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end if;
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when cActivated =>
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--perform a ClassicWrite
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NxR.oWbCtrl.Ack <= cActivated;
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NxR.WbState <= ClassicWrite;
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if (iWbDat.Sel = "1") then
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if (iWbDat.Adr = cOperationAddr or iWbDat.Adr = cStartAddrAddr or iWbDat.Adr = cEndAddrAddr) and
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R.SdIntState = newOperation then
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-- insert waitstates until we can notify the SdController again
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NxR.oWbCtrl.Ack <= cInactivated;
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NxR.WbState <= idle;
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end if;
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if (iWbDat.Adr = cWriteDataAddr and iWriteFifo.wrfull = cActivated) then
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NxR.oWbCtrl.Ack <= cInactivated;
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NxR.oWbCtrl.Err <= cActivated;
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NxR.WbState <= idle;
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end if;
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end if;
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when others =>
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report "iWbCtrl.We is invalid" severity warning;
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end case;
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when others => null;
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end case;
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end if;
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when ClassicRead =>
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NxR.WbState <= idle;
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when ClassicWrite =>
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NxR.WbState <= idle;
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if (iWbDat.Sel = "1") then
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case iWbDat.Adr is
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when cOperationAddr =>
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NxR.OperationBlock.Operation <= iWbDat.Dat;
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NxR.SdIntState <= newOperation;
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when cStartAddrAddr =>
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NxR.OperationBlock.StartAddr <= iWbDat.Dat;
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when cEndAddrAddr =>
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NxR.OperationBlock.EndAddr <= iWbDat.Dat;
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when cWriteDataAddr =>
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NxR.oWriteFifo.data <= iWbDat.Dat;
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NxR.oWriteFifo.wrreq <= cActivated;
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when others =>
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report "Write to an invalid address" severity warning;
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NxR.oWbCtrl.Err <= cActivated;
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NxR.oWbCtrl.Ack <= cInactivated;
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end case;
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end if;
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when others =>
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report "Invalid state" severity error;
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end case;
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-- send operations to SdController
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case R.SdIntState is
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when idle =>
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-- save edges on the ReqOperationEdge line which would be missed otherwise
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if (iController.ReqOperation = cActivated) then
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NxR.ReqOperation <= cActivated;
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end if;
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when newOperation =>
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-- send a new operation, when the controller requested it
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if (R.ReqOperation = cActivated or iController.ReqOperation = cActivated) then
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NxR.oController.OperationBlock <= R.OperationBlock;
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NxR.oController.AckOperation <= not R.oController.AckOperation;
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-- go to idle state, the next request will come only after the SdController received this block
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NxR.ReqOperation <= cInactivated;
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NxR.SdIntState <= idle;
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end if;
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when others =>
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report "Invalid state" severity error;
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end case;
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end process WbStateAndOutputs;
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end architecture Rtl;
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