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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : TestWbMaster-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description : Wishbone master for testing SDHC-SC-Core on the SbX
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-- Links :
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--
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architecture Rtl of TestWbMaster is
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type aState is (startAddr, writeBuffer, write, readbuffer, read, done);
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subtype aCounter is unsigned(7 downto 0); -- 128 * 32 bit = 512 byte
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type aWbState is (idle, write, read);
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type aReg is record
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State : aState;
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Counter : aCounter;
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WbState : aWbState;
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Err : std_ulogic;
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ReadData : unsigned(31 downto 0);
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StartAddr: unsigned(31 downto 0);
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end record aReg;
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signal R, NxR : aReg;
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begin
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LEDBANK_O(7) <= R.Err;
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LEDBANK_O(2 downto 0) <= std_ulogic_vector(R.StartAddr(2 downto 0));
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Regs : process (CLK_I)
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begin
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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-- sync. reset
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R.State <= startAddr;
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R.Counter <= (others => '0');
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R.WbState <= write;
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R.Err <= '0';
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R.ReadData <= (others => '0');
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R.StartAddr <= X"00000000";
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else
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R <= NxR;
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end if;
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end if;
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end process Regs;
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StateMachine : process (R, ERR_I, RTY_I, ACK_I, DAT_I)
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begin
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-- default assignment
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NxR <= R;
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CTI_O <= "000";
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CYC_O <= '0';
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WE_O <= '0';
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SEL_O <= "0";
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STB_O <= '0';
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ADR_O <= "000";
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DAT_O <= (others => '0');
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BTE_O <= "00";
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LEDBANK_O(6 downto 3) <= (others => '0');
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-- we donĀ“t care for errors or retrys
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if (ERR_I = '1' or RTY_I = '1') then
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NxR.Err <= '1';
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end if;
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case R.WbState is
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when idle =>
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null;
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when write =>
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-- write data
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CTI_O <= "000";
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CYC_O <= '1';
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WE_O <= '1';
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SEL_O <= "1";
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STB_O <= '1';
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if (ACK_I = '1') then
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if (R.Counter = 128) then
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NxR.Counter <= (others => '0');
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else
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NxR.Counter <= R.Counter + 1;
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end if;
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end if;
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when read =>
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-- read data
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CTI_O <= "000";
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CYC_O <= '1';
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WE_O <= '0';
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SEL_O <= "1";
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STB_O <= '1';
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when others =>
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report "Invalid wbState" severity error;
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end case;
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case R.State is
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when startAddr =>
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ADR_O <= "001";
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DAT_O <= std_ulogic_vector(R.startAddr);
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if (ACK_I = '1') then
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NxR.State <= read;
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NxR.Counter <= (others => '0');
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NxR.WbState <= write;
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end if;
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when writeBuffer =>
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ADR_O <= "100"; -- write data
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DAT_O <= std_ulogic_vector(R.ReadData + 1);
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if (ACK_I = '1') then
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if (R.Counter = 128) then
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NxR.State <= write;
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NxR.Counter <= to_unsigned(128, aCounter'length);
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NxR.WbState <= write;
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else
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NxR.State <= readBuffer;
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NxR.WbState <= read;
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end if;
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end if;
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when write =>
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LEDBANK_O(3) <= '1';
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ADR_O <= "000";
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DAT_O <= X"00000010"; -- start write operation
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if (ACK_I = '1') then
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NxR.State <= startAddr;
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NxR.WbState <= write;
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NxR.startAddr <= R.startAddr + 1;
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end if;
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if (R.StartAddr = 22) then
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NxR.State <= done;
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NxR.WbState <= idle;
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end if;
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when read =>
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LEDBANK_O(4) <= '1';
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ADR_O <= "000";
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DAT_O <= X"00000001"; -- start read operation
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if (ACK_I = '1') then
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NxR.State <= readBuffer;
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NxR.WbState <= read;
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end if;
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when readBuffer =>
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LEDBANK_O(5) <= '1';
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ADR_O <= "011"; -- read data
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if (ACK_I = '1') then
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NxR.ReadData <= unsigned(DAT_I);
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NxR.State <= writeBuffer;
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NxR.WbState <= write;
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end if;
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when done =>
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LEDBANK_O(6) <= '1';
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report "End of Simulation" severity failure;
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when others =>
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report "Invalid state" severity error;
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end case;
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end process StateMachine;
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end architecture Rtl;
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