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// SDHC-SC-Core
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// Secure Digital High Capacity Self Configuring Core
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//
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// (C) Copyright 2010, Rainer Kastl
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// File : SdVerificationTestbench.sv
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// Owner : Rainer Kastl
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// Description : Testbench for verification of SDHC-SC-Core
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// Links :
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//
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`ifndef SDVERIFICATIONTESTBENCH
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`define SDVERIFICATIONTESTBENCH
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`define cWishboneWidth 32
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const integer cWishboneWidth = 32;
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const logic cAsserted = 1;
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const logic cNegated = 0;
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const logic cDontCare = 'X;
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typedef logic [2:0] aCTI;
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const aCTI ClassicCycle = "000";
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`include "Harness.sv";
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`include "SdCardModel.sv";
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program Test(ISdBus SdBus, IWishboneBus WbBus);
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initial begin
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SdCardModel card;
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Harness harness;
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Logger log;
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log = new();
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card = new();
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harness = new(SdBus, WbBus);
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harness.Card = card;
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harness.start();
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#20ms;
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log.terminate();
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end
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endprogram
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module Testbed();
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logic Clk = 0;
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logic RstSync = 1;
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ISdBus CardInterface();
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IWishboneBus IWbBus();
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SdTop top(
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IWbBus.CLK_I,
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IWbBus.RST_I,
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IWbBus.CYC_O,
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IWbBus.LOCK_O,
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IWbBus.STB_O,
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IWbBus.WE_O,
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IWbBus.CTI_O,
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IWbBus.BTE_O,
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IWbBus.SEL_O,
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IWbBus.ADR_O,
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IWbBus.DAT_O,
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IWbBus.DAT_I,
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IWbBus.ACK_I,
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IWbBus.ERR_I,
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IWbBus.RTY_I,
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Clk,
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RstSync,
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CardInterface.Cmd,
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CardInterface.SClk,
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CardInterface.Data);
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always #5 Clk <= ~Clk;
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always #7 IWbBus.CLK_I <= ~IWbBus.CLK_I;
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initial begin
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#20 RstSync <= 0;
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#28 IWbBus.RST_I <= 0;
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end
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Test tb(CardInterface, IWbBus);
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endmodule
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`endif
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