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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : StrobeGen-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description :
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-- Links : See EDS at FH Hagenberg
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--
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architecture Rtl of StrobeGen is
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constant max : natural := gClkFrequency/(1 sec/ gStrobeCycleTime);
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constant cBitWidth : natural := LogDualis(max); -- Bitwidth
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signal Counter : unsigned (cBitWidth - 1 downto 0) := (others => '0');
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begin -- architecture Rtl
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StateReg : process (iClk, inResetAsync) is
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begin -- process StateReg
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if inResetAsync = cnActivated then -- asynchronous reset (active low)
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Counter <= (others => '0');
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oStrobe <= cInactivated;
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elsif iClk'event and iClk = cActivated then -- rising clock edge
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if (iRstSync = cActivated) then
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Counter <= (others => '0');
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oStrobe <= cInactivated;
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else
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Counter <= Counter + 1;
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if Counter < max - 1 then
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oStrobe <= cInactivated;
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else
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oStrobe <= cActivated;
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Counter <= TO_UNSIGNED(0, cBitWidth);
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end if;
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end if;
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end if;
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end process StateReg;
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end architecture Rtl;
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