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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : tbTimeoutGenerator-Bhv-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Testbench
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Global.all;
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entity tbTimeoutGenerator is
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end entity tbTimeoutGenerator;
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architecture Bhv of tbTimeoutGenerator is
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constant cClkFrequency : natural := 25E6;
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constant cClkPeriod : time := 1 sec / cClkFrequency;
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constant cResetTime : time := 4 * cClkPeriod;
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constant cTimeoutTime : time := 10 us;
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signal Clk : std_ulogic := '1';
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signal ResetSync : std_ulogic := cActivated;
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signal Done : std_ulogic := cInactivated;
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signal Timeout : std_ulogic;
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signal Enable : std_ulogic := cInactivated;
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begin
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Clk <= not Clk after (cClkPeriod / 2) when Done = cInactivated else '0';
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ResetSync <= cInactivated after cResetTime;
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DUT : entity work.TimeoutGenerator
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generic map (
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gClkFrequency => cClkFrequency,
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gTimeoutTime => cTimeoutTime
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)
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port map (
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iClk => Clk,
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iRstSync => ResetSync,
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iDisable => cInactivated,
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iEnable => Enable,
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oTimeout => Timeout
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);
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Stimuli : process
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begin
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wait for cResetTime;
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wait for cTimeoutTime;
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Enable <= cActivated,
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cInactivated after 2 * cClkPeriod;
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wait for 2*cTimeoutTime;
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Enable <= cActivated;
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wait;
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end process Stimuli;
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Checker : process (Timeout)
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begin
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if (Timeout = cActivated or Timeout = cInactivated) then -- first 'U'
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if (now = cResetTime + 2 * cTimeoutTime or
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now = cResetTime + 4 * cTimeoutTime) then
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assert (Timeout = cActivated)
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report "Timeout was not activated at the right time"
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severity error;
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elsif (now = cResetTime + 5 * cTimeoutTime) then
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assert (Timeout = cActivated)
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report "Timeout was not activated at the right time"
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severity error;
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Done <= cActivated;
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else
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assert (Timeout = cInactivated)
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report "Timeout was activated at a wrong time"
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severity error;
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end if;
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end if;
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end process Checker;
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end architecture Bhv;
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