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// SDHC-SC-Core
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// Secure Digital High Capacity Self Configuring Core
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//
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// (C) Copyright 2010, Rainer Kastl
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// File : IWishboneBus.sv
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// Owner : Rainer Kastl
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// Description : Wishbone bus
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// Links : Wishbone Spec R.3B
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//
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`ifndef IWISHBONEBUS
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`define IWISHBONEBUS
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interface IWishboneBus;
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logic ERR_I;
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logic RTY_I;
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logic CLK_I = 1;
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logic RST_I = 1;
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logic ACK_I;
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logic [`cWishboneWidth-1 : 0] DAT_I;
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logic CYC_O;
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logic [6:4] ADR_O;
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logic [`cWishboneWidth-1 : 0] DAT_O;
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logic [`cWishboneWidth/`cWishboneWidth-1 : 0] SEL_O;
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logic STB_O;
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logic [`cWishboneWidth-1 : 0] TGA_O;
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logic [`cWishboneWidth-1 : 0] TGC_O;
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logic TGD_O;
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logic WE_O;
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logic LOCK_O;
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aCTI CTI_O;
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logic [1 : 0] BTE_O;
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// Masters view of the interface
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clocking cbMaster @(posedge CLK_I);
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input ERR_I, RTY_I, ACK_I, DAT_I;
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output CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O, RST_I;
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endclocking
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modport Master (
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input CLK_I, clocking cbMaster
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);
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// Slaves view of the interface
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modport Slave (
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input CLK_I, RST_I, CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O,
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output ERR_I, RTY_I, ACK_I, DAT_I
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);
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endinterface;
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`endif
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