| Line 55... |
Line 55... |
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type DRAM_DRIVER_STATES is ( STATE0, STATE1, STATE2, STATE3, STATE4, STATE5 );
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type DRAM_DRIVER_STATES is ( STATE0, STATE1, STATE2, STATE3, STATE4, STATE5 );
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signal dram_driver_state : DRAM_DRIVER_STATES := STATE0;
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signal dram_driver_state : DRAM_DRIVER_STATES := STATE0;
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signal clk_bufd : std_logic;
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signal clk_bufd : std_logic;
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signal clk100mhz : std_logic;
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signal dcm_locked : std_logic;
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signal dcm_clk_000 : std_logic;
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signal dcm_clk_raw_000 : std_logic;
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signal op : std_logic_vector(1 downto 0);
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signal op : std_logic_vector(1 downto 0);
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signal addr : std_logic_vector(25 downto 0);
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signal addr : std_logic_vector(25 downto 0);
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signal op_ack : std_logic;
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signal op_ack : std_logic;
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signal busy_n : std_logic;
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signal busy_n : std_logic;
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| Line 71... |
Line 75... |
port map(
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port map(
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O => clk_bufd,
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O => clk_bufd,
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I => clk
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I => clk
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);
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);
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TB_DCM : DCM_SP
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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CLKFX_DIVIDE => 2, -- Can be any integer from 1 to 32
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CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => 10.0, -- Specify period of input clock
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CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
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CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
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DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
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-- an integer from 0 to 15
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DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
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STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
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port map (
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CLK0 => dcm_clk_raw_000, -- 0 degree DCM CLK ouptput
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CLK90 => open, -- 90 degree DCM CLK output
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => open, -- 270 degree DCM CLK output
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CLK2X => clk100mhz, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => open, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => dcm_locked, -- DCM LOCK status output (means feedback is in phase with main clock)
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PSDONE => open, -- Dynamic phase adjust done output
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STATUS => open, -- 8-bit DCM status bits output
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CLKFB => dcm_clk_000, -- DCM clock feedback
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CLKIN => clk_bufd, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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DCM_BUF_000: BUFG
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port map(
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O => dcm_clk_000,
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I => dcm_clk_raw_000
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);
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SDRAM: entity work.sdram_controller
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SDRAM: entity work.sdram_controller
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port map(
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port map(
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clk50mhz => clk_bufd,
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clk100mhz => clk100mhz,
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en => '1',
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en => '1',
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reset => rst,
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reset => rst,
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op => op,
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op => op,
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addr => addr,
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addr => addr,
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op_ack => op_ack,
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op_ack => op_ack,
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| Line 111... |
Line 158... |
if (busy_n = '1') then
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if (busy_n = '1') then
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dram_driver_state <= STATE1;
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dram_driver_state <= STATE1;
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end if;
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end if;
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when STATE1 =>
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when STATE1 =>
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addr <= "01000000000000000000000111";
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addr <= "0000000000"& x"6001";
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data_i <= "11111111";
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data_i <= "11110001";
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op <= "10";
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op <= "10";
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if (op_ack = '1') then
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if (op_ack = '1') then
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dram_driver_state <= STATE2;
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dram_driver_state <= STATE2;
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end if;
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end if;
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| Line 125... |
Line 172... |
if (busy_n = '1') then
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if (busy_n = '1') then
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dram_driver_state <= STATE3;
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dram_driver_state <= STATE3;
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end if;
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end if;
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when STATE3 =>
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when STATE3 =>
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addr <= "01000000000000000000000111";
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addr <= "0000000000" & x"6001";
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op <= "01";
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op <= "01";
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if (op_ack = '1') then
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if (op_ack = '1') then
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dram_driver_state <= STATE4;
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dram_driver_state <= STATE4;
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end if;
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end if;
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