| Line 1... |
Line 1... |
//IP Functional Simulation Model
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//IP Functional Simulation Model
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//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:15:41:SJ cbx_simgen 2012:01:25:21:13:53:SJ VERSION_END
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//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:10:19:19:54:28:SJ cbx_simgen 2012:10:19:19:52:08:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// altera message_off 10463
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// Copyright (C) 1991-2011 Altera Corporation
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// Copyright (C) 1991-2012 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// associated documentation or information are expressly subject
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| Line 24... |
Line 24... |
// event Altera disclaims all warranties of any kind).
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// event Altera disclaims all warranties of any kind).
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//synopsys translate_off
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//synopsys translate_off
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//synthesis_resources = altera_std_synchronizer 7 altera_std_synchronizer_bundle 3 altpll 1 altsyncram 2 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 lut 937 mux21 1092 oper_add 27 oper_decoder 4 oper_less_than 11 oper_mux 16 oper_selector 42
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//synthesis_resources = altera_std_synchronizer 8 altera_std_synchronizer_bundle 3 altpll 1 altsyncram 2 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 lut 942 mux21 1096 oper_add 27 oper_decoder 4 oper_less_than 11 oper_mux 16 oper_selector 42
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module sgmii
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module sgmii
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(
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(
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address,
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address,
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clk,
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clk,
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| Line 107... |
Line 107... |
output pcs_pwrdn_out;
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output pcs_pwrdn_out;
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input read;
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input read;
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output [15:0] readdata;
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output [15:0] readdata;
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input reconfig_busy;
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input reconfig_busy;
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input reconfig_clk;
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input reconfig_clk;
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output [16:0] reconfig_fromgxb;
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output [4:0] reconfig_fromgxb;
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input [3:0] reconfig_togxb;
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input [3:0] reconfig_togxb;
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input ref_clk;
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input ref_clk;
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input reset;
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input reset;
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input reset_rx_clk;
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input reset_rx_clk;
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input reset_tx_clk;
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input reset_tx_clk;
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| Line 127... |
Line 127... |
output txp;
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output txp;
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output waitrequest;
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output waitrequest;
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input write;
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input write;
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input [15:0] writedata;
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input [15:0] writedata;
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|
|
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wire wire_n1i10i_dout;
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wire wire_n1i10O_dout;
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wire wire_n1i11O_dout;
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wire wire_n1i1ii_dout;
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wire wire_n1i1ii_dout;
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wire wire_n1i1il_dout;
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wire wire_nlili0O_dout;
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wire wire_n1i1li_dout;
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wire wire_nliliii_dout;
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wire wire_n1i1ll_dout;
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wire wire_nliliil_dout;
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wire wire_nliliOl_dout;
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wire wire_nliliiO_dout;
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wire wire_nliliOO_dout;
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wire [1:0] wire_n01ill_dout;
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wire wire_nlill1i_dout;
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wire [1:0] wire_n01ilO_dout;
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wire [1:0] wire_n01l0O_dout;
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wire [15:0] wire_n1i10l_dout;
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wire [1:0] wire_n01lii_dout;
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wire [5:0] wire_nl01O_clk;
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wire [15:0] wire_n1i1iO_dout;
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wire wire_nl01O_fref;
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wire [5:0] wire_nl11O_clk;
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wire wire_nl01O_icdrclk;
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wire wire_nl11O_fref;
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wire wire_nl01O_locked;
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wire wire_nl11O_icdrclk;
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wire wire_nl11O_locked;
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wire [9:0] wire_n00OOO_q_b;
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wire [9:0] wire_n00OOO_q_b;
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wire [9:0] wire_ni1O0i_q_b;
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wire [9:0] wire_ni1O0i_q_b;
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wire wire_nl1iO_nonusertocmu;
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wire wire_nl0iO_nonusertocmu;
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wire wire_nl1il_dpriodisableout;
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wire wire_nl0il_dpriodisableout;
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wire wire_nl1il_dprioout;
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wire wire_nl0il_dprioout;
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wire wire_nl1il_quadresetout;
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wire wire_nl0il_quadresetout;
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wire [3:0] wire_nl1il_rxanalogresetout;
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wire [3:0] wire_nl0il_rxanalogresetout;
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wire [3:0] wire_nl1il_rxcrupowerdown;
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wire [3:0] wire_nl0il_rxcrupowerdown;
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wire [3:0] wire_nl1il_rxdigitalresetout;
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wire [3:0] wire_nl0il_rxdigitalresetout;
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wire [3:0] wire_nl1il_rxibpowerdown;
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wire [3:0] wire_nl0il_rxibpowerdown;
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wire [1599:0] wire_nl1il_rxpcsdprioout;
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wire [1599:0] wire_nl0il_rxpcsdprioout;
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wire [1199:0] wire_nl1il_rxpmadprioout;
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wire [1199:0] wire_nl0il_rxpmadprioout;
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wire [3:0] wire_nl1il_txanalogresetout;
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wire [3:0] wire_nl0il_txanalogresetout;
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wire [3:0] wire_nl1il_txdetectrxpowerdown;
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wire [3:0] wire_nl0il_txdetectrxpowerdown;
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wire [3:0] wire_nl1il_txdigitalresetout;
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wire [3:0] wire_nl0il_txdigitalresetout;
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wire [3:0] wire_nl1il_txdividerpowerdown;
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wire [3:0] wire_nl0il_txdividerpowerdown;
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wire [3:0] wire_nl1il_txobpowerdown;
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wire [3:0] wire_nl0il_txobpowerdown;
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wire [599:0] wire_nl1il_txpcsdprioout;
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wire [599:0] wire_nl0il_txpcsdprioout;
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wire [1199:0] wire_nl1il_txpmadprioout;
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wire [1199:0] wire_nl0il_txpmadprioout;
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wire wire_nl1ii_cdrctrllocktorefclkout;
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wire wire_nl0ii_cdrctrllocktorefclkout;
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wire wire_nl1ii_clkout;
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wire wire_nl0ii_clkout;
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wire [1:0] wire_nl1ii_ctrldetect;
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wire [1:0] wire_nl0ii_ctrldetect;
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wire [19:0] wire_nl1ii_dataout;
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wire [19:0] wire_nl0ii_dataout;
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wire [1:0] wire_nl1ii_disperr;
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wire [1:0] wire_nl0ii_disperr;
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wire [399:0] wire_nl1ii_dprioout;
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wire [399:0] wire_nl0ii_dprioout;
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wire [1:0] wire_nl1ii_errdetect;
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wire [1:0] wire_nl0ii_errdetect;
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wire [1:0] wire_nl1ii_patterndetect;
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wire [1:0] wire_nl0ii_patterndetect;
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wire wire_nl1ii_rlv;
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wire wire_nl0ii_rlv;
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wire [1:0] wire_nl1ii_runningdisp;
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wire [1:0] wire_nl0ii_runningdisp;
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wire [1:0] wire_nl1ii_syncstatus;
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wire [1:0] wire_nl0ii_syncstatus;
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wire wire_nl10O_clockout;
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wire wire_nl00O_clockout;
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wire wire_nl10O_diagnosticlpbkout;
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wire wire_nl00O_diagnosticlpbkout;
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wire [299:0] wire_nl10O_dprioout;
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wire [299:0] wire_nl00O_dprioout;
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wire wire_nl10O_freqlocked;
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wire wire_nl00O_freqlocked;
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wire [9:0] wire_nl10O_recoverdataout;
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wire [9:0] wire_nl00O_recoverdataout;
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wire wire_nl10O_reverselpbkout;
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wire wire_nl00O_reverselpbkout;
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wire wire_nl10O_signaldetect;
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wire wire_nl00O_signaldetect;
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wire wire_nl10l_clkout;
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wire wire_nl00l_clkout;
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wire [9:0] wire_nl10l_dataout;
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wire [9:0] wire_nl00l_dataout;
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wire [149:0] wire_nl10l_dprioout;
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wire [149:0] wire_nl00l_dprioout;
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wire wire_nl10l_txdetectrx;
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wire wire_nl00l_txdetectrx;
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wire wire_nl10i_clockout;
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wire wire_nl00i_clockout;
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wire wire_nl10i_dataout;
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wire wire_nl00i_dataout;
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wire [299:0] wire_nl10i_dprioout;
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wire [299:0] wire_nl00i_dprioout;
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wire wire_nl10i_seriallpbkout;
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wire wire_nl00i_seriallpbkout;
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reg nli00Oi61;
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reg nli000i55;
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reg nli00Oi62;
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reg nli000i56;
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reg nli00Ol59;
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reg nli001O57;
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reg nli00Ol60;
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reg nli001O58;
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reg nli00OO57;
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reg nli010i59;
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reg nli00OO58;
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reg nli010i60;
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reg nli010l71;
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reg nli011l63;
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reg nli010l72;
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reg nli011l64;
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reg nli010O69;
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reg nli011O61;
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reg nli010O70;
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reg nli011O62;
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reg nli011i73;
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reg nli0l0i53;
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reg nli011i74;
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reg nli0l0i54;
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reg nli01li67;
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reg nli0lii51;
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reg nli01li68;
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reg nli0lii52;
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reg nli01ll65;
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reg nli0liO49;
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reg nli01ll66;
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reg nli0liO50;
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reg nli01Ol63;
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reg nli0lll47;
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reg nli01Ol64;
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reg nli0lll48;
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reg nli0iOO55;
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reg nli0lOi45;
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reg nli0iOO56;
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reg nli0lOi46;
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reg nli0llO53;
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reg nli0O0i41;
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reg nli0llO54;
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reg nli0O0i42;
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reg nli0lOO51;
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reg nli0O1l43;
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reg nli0lOO52;
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reg nli0O1l44;
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reg nli0O0i47;
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reg nli0Oii39;
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reg nli0O0i48;
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reg nli0Oii40;
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reg nli0O1l49;
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reg nli0OiO37;
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reg nli0O1l50;
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reg nli0OiO38;
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reg nli0Oii45;
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reg nli0OlO35;
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reg nli0Oii46;
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reg nli0OlO36;
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reg nli0Oli43;
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reg nli0OOl33;
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reg nli0Oli44;
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reg nli0OOl34;
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reg nli0OlO41;
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reg nli1llO79;
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reg nli0OlO42;
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reg nli1llO80;
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reg nli0OOO39;
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reg nli1lOi77;
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reg nli0OOO40;
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reg nli1lOi78;
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reg nli1OiO79;
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reg nli1O0O75;
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reg nli1OiO80;
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reg nli1O0O76;
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reg nli1Oli77;
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reg nli1Oii73;
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reg nli1Oli78;
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reg nli1Oii74;
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reg nli1OOO75;
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reg nli1Oil71;
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reg nli1OOO76;
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reg nli1Oil72;
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reg nlii00i23;
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reg nli1OlO69;
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reg nlii00i24;
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reg nli1OlO70;
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reg nlii01l25;
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reg nli1OOi67;
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reg nlii01l26;
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reg nli1OOi68;
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reg nlii0ii21;
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reg nli1OOl65;
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reg nlii0ii22;
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reg nli1OOl66;
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reg nlii0il19;
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reg nlii00l13;
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reg nlii0il20;
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reg nlii00l14;
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reg nlii0iO17;
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reg nlii01i19;
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reg nlii0iO18;
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reg nlii01i20;
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reg nlii0ll15;
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reg nlii01l17;
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reg nlii0ll16;
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reg nlii01l18;
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reg nlii0Ol13;
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reg nlii01O15;
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reg nlii0Ol14;
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reg nlii01O16;
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reg nlii0OO11;
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reg nlii0ii11;
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reg nlii0OO12;
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reg nlii0ii12;
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reg nlii10l35;
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reg nlii0il10;
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reg nlii10l36;
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reg nlii0il9;
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reg nlii11O37;
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reg nlii0Oi7;
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reg nlii11O38;
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reg nlii0Oi8;
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reg nlii1il33;
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reg nlii0Ol5;
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reg nlii1il34;
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reg nlii0Ol6;
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reg nlii1li31;
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reg nlii0OO3;
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reg nlii1li32;
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reg nlii0OO4;
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reg nlii1lO29;
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reg nlii10i29;
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reg nlii1lO30;
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reg nlii10i30;
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reg nlii1OO27;
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reg nlii10O27;
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reg nlii1OO28;
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reg nlii10O28;
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reg nliii0O7;
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reg nlii11l31;
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reg nliii0O8;
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reg nlii11l32;
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reg nliii1i10;
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reg nlii1iO25;
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reg nliii1i9;
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reg nlii1iO26;
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reg nliiiii5;
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reg nlii1ll23;
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reg nliiiii6;
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reg nlii1ll24;
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reg nliiiil3;
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reg nlii1Ol21;
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reg nliiiil4;
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reg nlii1Ol22;
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reg nliiili1;
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reg nliii1l1;
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reg nliiili2;
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reg nliii1l2;
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reg n000l;
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reg n00iO;
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reg n00ii;
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reg n011l;
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wire wire_n000O_PRN;
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reg n011O;
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reg n00Oii;
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reg n00Oll;
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reg n00OOl;
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reg n01l0l;
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reg n01l1O;
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reg n011i;
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reg n01iO;
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reg n01ll;
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reg n01ll;
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reg n101l;
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reg n01Ol;
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reg n01OO;
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reg n10ii;
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reg n10ii;
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reg n10ll;
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reg n10il;
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reg n10Ol;
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reg n11OO;
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reg n110l;
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reg n1i1l;
|
reg n110O;
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reg n1l1i;
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reg n11lO;
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reg n1O0i;
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reg n11Oi;
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reg n00ll;
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reg n1i0l;
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reg n01lO;
|
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reg n101i;
|
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reg n10lO;
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reg n1i0O;
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reg n1i0O;
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reg n1i1i;
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reg n1iiO;
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reg n1ill;
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reg n1ill;
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reg n1ilO;
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reg n1iOO;
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reg n1l0i;
|
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reg n1l0l;
|
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reg n1l0O;
|
reg n1l0O;
|
reg n1l1l;
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reg n1lii;
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reg n1l1O;
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reg n1llO;
|
reg n1lOi;
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reg n1O1i;
|
reg n1O0i;
|
reg n1O1l;
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reg n1O1O;
|
reg n1O1O;
|
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reg n1Oll;
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reg n1OlO;
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reg n1OlO;
|
reg n1OOi;
|
reg n00Oii;
|
reg n1OOO;
|
reg n00Oll;
|
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reg n00OOl;
|
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reg n01iil;
|
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reg n01ili;
|
reg n0i01l;
|
reg n0i01l;
|
reg n0i10i;
|
reg n0i10i;
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reg n0i10l;
|
reg n0i10l;
|
reg n0i11i;
|
reg n0i11i;
|
reg n0i11l;
|
reg n0i11l;
|
| Line 312... |
Line 311... |
reg n0i1iO;
|
reg n0i1iO;
|
reg n0i1li;
|
reg n0i1li;
|
reg n0i1ll;
|
reg n0i1ll;
|
reg n0i1Ol;
|
reg n0i1Ol;
|
reg n0i1OO;
|
reg n0i1OO;
|
|
reg n0i0l;
|
|
reg n0iii;
|
reg n0i1Oi;
|
reg n0i1Oi;
|
reg n0ii0O;
|
reg n0ii0O;
|
reg n0i0iO;
|
reg n0i0iO;
|
reg n0i0li;
|
reg n0i0li;
|
reg n0i0ll;
|
reg n0i0ll;
|
| Line 330... |
Line 331... |
reg n0iOii;
|
reg n0iOii;
|
reg n0iO0i;
|
reg n0iO0i;
|
reg n0010i;
|
reg n0010i;
|
reg n0010l;
|
reg n0010l;
|
reg n0010O;
|
reg n0010O;
|
reg n0011O;
|
reg n0011i;
|
reg n001ii;
|
reg n001ii;
|
reg n001il;
|
reg n001il;
|
reg n001iO;
|
reg n001iO;
|
reg n001li;
|
reg n001li;
|
reg n00lOO;
|
reg n00lOO;
|
| Line 343... |
Line 344... |
reg n00O1i;
|
reg n00O1i;
|
reg n00Oil;
|
reg n00Oil;
|
reg n00OiO;
|
reg n00OiO;
|
reg n00Oli;
|
reg n00Oli;
|
reg n00OlO;
|
reg n00OlO;
|
|
reg n01l0l;
|
|
reg n01l0O;
|
|
reg n01lOi;
|
|
reg n01lOl;
|
reg n01lOO;
|
reg n01lOO;
|
reg n01O0i;
|
reg n01O0i;
|
reg n01O0l;
|
reg n01O0l;
|
reg n01O0O;
|
reg n01O0O;
|
reg n01O1i;
|
reg n01O1i;
|
reg n01O1l;
|
reg n01O1l;
|
reg n01O1O;
|
reg n01O1O;
|
reg n01Oii;
|
reg n01Oii;
|
reg n01Oil;
|
|
reg n01OiO;
|
reg n01OiO;
|
reg n01Oli;
|
|
reg n01OOO;
|
reg n01OOO;
|
reg n0ilOi;
|
reg n0ilOi;
|
reg n0ilOO;
|
reg n0ilOO;
|
reg n0iO1i;
|
reg n0iO1i;
|
reg n0iO1l;
|
reg n0iO1l;
|
| Line 405... |
Line 408... |
reg n0O1ll;
|
reg n0O1ll;
|
reg n0O1Oi;
|
reg n0O1Oi;
|
reg n0O0ll;
|
reg n0O0ll;
|
reg n0O0Oi;
|
reg n0O0Oi;
|
reg n0Oiil;
|
reg n0Oiil;
|
reg n101OO;
|
reg n101ll;
|
reg nlOi00O;
|
reg nlOi01l;
|
reg n0lO0O;
|
reg n0lO0O;
|
reg n0lO1i;
|
reg n0lO1i;
|
reg n0O0iO;
|
reg n0O0iO;
|
reg n0O11i;
|
reg n0O11i;
|
reg n0Oi1i;
|
reg n0Oi1i;
|
reg n0Oili;
|
reg n0Oili;
|
reg nlil00i;
|
reg nlil01i;
|
reg nlil00l;
|
reg nlil01l;
|
reg nlil00O;
|
|
reg nlil01O;
|
reg nlil01O;
|
reg nlil0ii;
|
reg nlil10i;
|
reg nlil0il;
|
reg nlil1li;
|
reg nlil0iO;
|
reg nlil1ll;
|
reg nlil0li;
|
|
reg nlil0ll;
|
|
reg nlil1lO;
|
reg nlil1lO;
|
reg nliliiO;
|
reg nlil1Oi;
|
|
reg nlil1Ol;
|
|
reg nlil1OO;
|
|
reg nlili1i;
|
reg n0O0li;
|
reg n0O0li;
|
reg n0O0lO;
|
reg n0O0lO;
|
reg n0OilO;
|
reg n0OilO;
|
reg nlil01i;
|
reg nlil0OO;
|
reg nliliil;
|
reg nlil1il;
|
reg nlilili;
|
reg nlili1l;
|
reg n01l1i;
|
reg n01i0O;
|
reg n01l1l;
|
reg n01iii;
|
reg n0OiOi;
|
reg n0OiOi;
|
reg n0OiOl;
|
reg n0OiOl;
|
reg n0OiOO;
|
reg n0OiOO;
|
reg n0Ol1l;
|
reg n0Ol1l;
|
reg n0Ol0i;
|
reg n0Ol0i;
|
| Line 446... |
Line 449... |
reg n0Olil;
|
reg n0Olil;
|
reg n0OliO;
|
reg n0OliO;
|
reg n0Olli;
|
reg n0Olli;
|
reg n0Olll;
|
reg n0Olll;
|
reg n0OO1l;
|
reg n0OO1l;
|
|
reg n110l;
|
|
reg n11ii;
|
|
reg nl010i;
|
|
reg nllllO;
|
|
reg nlOOll;
|
|
reg n11il;
|
|
reg n11iO;
|
|
reg n11li;
|
|
reg n11ll;
|
|
reg n11lO;
|
|
reg n11Ol;
|
|
wire wire_n11Oi_CLRN;
|
reg ni00ll;
|
reg ni00ll;
|
reg ni001i;
|
reg ni001i;
|
reg ni001l;
|
reg ni001l;
|
reg ni001O;
|
reg ni001O;
|
reg ni00ii;
|
reg ni00ii;
|
| Line 523... |
Line 538... |
reg nil1OO;
|
reg nil1OO;
|
reg ni0lii;
|
reg ni0lii;
|
reg nil00l;
|
reg nil00l;
|
reg nil01i;
|
reg nil01i;
|
reg nil0iO;
|
reg nil0iO;
|
reg n0l1i;
|
reg n011il;
|
reg nil0O;
|
reg n1i00i;
|
reg niliO;
|
reg n1i00l;
|
reg nilil_clk_prev;
|
reg n1i00O;
|
wire wire_nilil_CLRN;
|
reg n1i0ii;
|
wire wire_nilil_PRN;
|
|
reg n0101O;
|
|
reg n1i01i;
|
|
reg n1i0il;
|
|
reg n1i0iO;
|
reg n1i0iO;
|
reg n1i0li;
|
reg n1i1il;
|
reg n1i0ll;
|
|
reg n1i0Oi;
|
|
reg n1i1lO;
|
reg n1i1lO;
|
reg nili0i;
|
reg nili0i;
|
reg nili0l;
|
reg nili0l;
|
reg niO00i;
|
reg niO00i;
|
reg niO01l;
|
reg niO01l;
|
reg niO0ii;
|
reg niO0ii;
|
reg niO1ll;
|
reg niO1ll;
|
reg niO1Oi;
|
reg niO1Oi;
|
reg niO1OO;
|
reg niO1OO;
|
reg nliilOi;
|
reg nliil0l;
|
reg nlil10l;
|
reg nliiOlO;
|
reg nlil1ii;
|
reg nliiOOl;
|
reg n0OllO;
|
reg n0OllO;
|
reg n0OlOl;
|
reg n0OlOl;
|
reg n0OlOO;
|
reg n0OlOO;
|
reg n0OO0i;
|
reg n0OO0i;
|
reg n0OO0l;
|
reg n0OO0l;
|
| Line 604... |
Line 613... |
reg niO10l;
|
reg niO10l;
|
reg niO10O;
|
reg niO10O;
|
reg niO11i;
|
reg niO11i;
|
reg niO11l;
|
reg niO11l;
|
reg niO11O;
|
reg niO11O;
|
|
reg n0O1i;
|
|
reg niO0O;
|
|
reg niOiO;
|
|
wire wire_niOil_PRN;
|
reg nl00ii;
|
reg nl00ii;
|
wire wire_nl000O_ENA;
|
wire wire_nl000O_ENA;
|
|
reg n0lil;
|
|
reg niO1i;
|
|
reg niOii;
|
|
reg niOli;
|
|
reg niOll;
|
|
reg niOlO;
|
|
reg niOOi;
|
|
reg niOOl;
|
|
reg niOOO;
|
|
reg nl01l;
|
|
reg nl10i;
|
|
reg nl10l;
|
|
reg nl10O;
|
|
reg nl11i;
|
|
reg nl11l;
|
|
reg nl11O;
|
|
reg nl1ii;
|
|
reg nl1il;
|
|
reg nl1iO;
|
|
reg nl1li;
|
|
reg nl1ll;
|
|
reg nl1lO;
|
|
reg nl1Oi;
|
|
reg nl1Ol;
|
|
reg nl1OO;
|
|
wire wire_nl01i_CLRN;
|
reg nl00ll;
|
reg nl00ll;
|
reg nl00Oi;
|
reg nl00Oi;
|
reg nl00Ol;
|
reg nl00Ol;
|
reg nl00OO;
|
reg nl00OO;
|
reg nl0i1i;
|
reg nl0i1i;
|
reg nl0i1O;
|
reg nl0i1O;
|
reg n000i;
|
|
reg n110i;
|
|
reg n111i;
|
|
reg n111l;
|
|
reg n111O;
|
|
reg nl00O;
|
|
reg nl01l;
|
|
reg nl0il;
|
|
reg nlOOOl;
|
|
reg nlOOOO;
|
|
reg nl0ii_clk_prev;
|
|
wire wire_nl0ii_CLRN;
|
|
wire wire_nl0ii_PRN;
|
|
reg nl0i0i;
|
reg nl0i0i;
|
reg nl0i0O;
|
reg nl0i0O;
|
reg nl0iii;
|
reg nl0iii;
|
reg nl0iiO;
|
reg nl0iiO;
|
reg nl0ilO;
|
reg nl0ilO;
|
| Line 640... |
Line 666... |
reg nl0iil;
|
reg nl0iil;
|
reg nl0ili;
|
reg nl0ili;
|
reg nl0ill;
|
reg nl0ill;
|
reg nl0iOi;
|
reg nl0iOi;
|
reg nl0l1l;
|
reg nl0l1l;
|
|
reg nl0li;
|
|
reg nl0lO;
|
|
wire wire_nl0ll_PRN;
|
reg nl0liO;
|
reg nl0liO;
|
reg nl0lll;
|
reg nl0lll;
|
reg nl0lli_clk_prev;
|
|
wire wire_nl0lli_PRN;
|
|
reg nl0lii;
|
reg nl0lii;
|
reg nl0lil;
|
reg nl0lil;
|
reg nl0lOi;
|
reg nl0lOi;
|
reg nl0llO_clk_prev;
|
reg nl0llO_clk_prev;
|
wire wire_nl0llO_CLRN;
|
wire wire_nl0llO_CLRN;
|
reg nl00l;
|
wire wire_nl0llO_PRN;
|
reg nl0Oi;
|
|
reg nl0lO_clk_prev;
|
|
wire wire_nl0lO_CLRN;
|
|
wire wire_nl0lO_PRN;
|
|
reg n0iil;
|
|
reg nil1i;
|
|
reg nilii;
|
|
reg nilli;
|
|
reg nilll;
|
|
reg nillO;
|
|
reg nilOi;
|
|
reg nilOl;
|
|
reg nilOO;
|
|
reg niO0i;
|
|
reg niO0l;
|
|
reg niO0O;
|
|
reg niO1i;
|
|
reg niO1l;
|
|
reg niO1O;
|
|
reg niOii;
|
|
reg niOil;
|
|
reg niOiO;
|
|
reg niOli;
|
|
reg niOll;
|
|
reg niOlO;
|
|
reg niOOi;
|
|
reg niOOl;
|
|
reg niOOO;
|
|
reg nl11l;
|
|
reg nl111i;
|
reg nl111i;
|
reg nl1i0l;
|
reg nl1i0l;
|
reg nl1i0O;
|
reg nl1i0O;
|
reg nl1iii;
|
reg nl1iii;
|
reg nl1iil;
|
reg nl1iil;
|
| Line 695... |
Line 693... |
reg nl1iOO;
|
reg nl1iOO;
|
reg nl1l0l;
|
reg nl1l0l;
|
reg nl1l1i;
|
reg nl1l1i;
|
reg nl1l1l;
|
reg nl1l1l;
|
reg nl1l1O;
|
reg nl1l1O;
|
reg nl1li;
|
reg nli0O;
|
reg nl1lO;
|
reg nli0l_clk_prev;
|
wire wire_nl1ll_CLRN;
|
wire wire_nli0l_CLRN;
|
|
wire wire_nli0l_PRN;
|
reg nl0lOl;
|
reg nl0lOl;
|
reg nl0O0i;
|
reg nl0O0i;
|
reg nl0O0l;
|
reg nl0O0l;
|
reg nl0O0O;
|
reg nl0O0O;
|
reg nl0O1l;
|
reg nl0O1l;
|
| Line 714... |
Line 713... |
reg nl0OlO;
|
reg nl0OlO;
|
reg nl0OOi;
|
reg nl0OOi;
|
reg nl0OOl;
|
reg nl0OOl;
|
reg nl0OOO;
|
reg nl0OOO;
|
reg nli11l;
|
reg nli11l;
|
reg nli11i_clk_prev;
|
|
wire wire_nli11i_CLRN;
|
|
wire wire_nli11i_PRN;
|
|
reg nli00i;
|
reg nli00i;
|
reg nli00l;
|
reg nli00l;
|
reg nli00O;
|
reg nli00O;
|
reg nli01O;
|
reg nli01O;
|
reg nli0ii;
|
reg nli0ii;
|
| Line 733... |
Line 729... |
reg nli0Ol;
|
reg nli0Ol;
|
reg nli0OO;
|
reg nli0OO;
|
reg nli1OO;
|
reg nli1OO;
|
reg nlii1i;
|
reg nlii1i;
|
reg nlii1O;
|
reg nlii1O;
|
reg nliiiOl;
|
wire wire_nlii1l_CLRN;
|
reg nliil1i;
|
reg nliii0O;
|
reg nliil0i;
|
reg nliiiil;
|
reg nliil1l;
|
reg nliiiiO;
|
|
reg nliiill;
|
|
reg nli0i;
|
|
reg nlili;
|
|
reg nliiO_clk_prev;
|
|
wire wire_nliiO_CLRN;
|
|
wire wire_nliiO_PRN;
|
reg nlii0i;
|
reg nlii0i;
|
reg nliilO;
|
reg nliilO;
|
reg nliiOl;
|
reg nliiOl;
|
reg nliiOi_clk_prev;
|
|
wire wire_nliiOi_CLRN;
|
|
reg nliill;
|
reg nliill;
|
reg nliiOO;
|
reg nliiOO;
|
reg nlil1l;
|
reg nlil1l;
|
|
reg nlil1i_clk_prev;
|
wire wire_nlil1i_CLRN;
|
wire wire_nlil1i_CLRN;
|
reg nlilill;
|
wire wire_nlil1i_PRN;
|
reg nliliOi;
|
reg nlili0l;
|
reg nliOOi;
|
reg nlili1O;
|
reg nliOlO_clk_prev;
|
reg n010li;
|
wire wire_nliOlO_CLRN;
|
reg n010ll;
|
reg nliOli;
|
|
reg nliOll;
|
|
reg nliOOO;
|
|
wire wire_nliOOl_CLRN;
|
|
reg n0101i;
|
|
reg n0101l;
|
|
reg n0110i;
|
reg n0110i;
|
reg n0110l;
|
reg n0110l;
|
reg n0110O;
|
reg n0110O;
|
|
reg n0111i;
|
|
reg n0111l;
|
|
reg n0111O;
|
reg n011ii;
|
reg n011ii;
|
reg n011il;
|
reg n01i0i;
|
reg n011iO;
|
|
reg n011li;
|
|
reg n011ll;
|
|
reg n011lO;
|
|
reg n011Oi;
|
|
reg n011Ol;
|
|
reg n011OO;
|
|
reg n01i0l;
|
reg n01i0l;
|
reg n01i0O;
|
reg n01i1i;
|
reg n01ill;
|
reg n01i1O;
|
reg n01iOi;
|
reg n1i01i;
|
reg n01iOl;
|
reg n1i01l;
|
reg n01iOO;
|
reg n1i01O;
|
reg n1i00l;
|
reg n1i0il;
|
reg n1i00O;
|
reg n1i0li;
|
reg n1i0ii;
|
reg n1OOiO;
|
reg n1i0lO;
|
reg n1OOli;
|
reg n1i0Ol;
|
reg n1OOll;
|
|
reg n1OOlO;
|
|
reg n1OOOi;
|
|
reg n1OOOl;
|
|
reg n1OOOO;
|
reg nili1l;
|
reg nili1l;
|
reg nili1O;
|
reg nili1O;
|
reg niliil;
|
reg niliil;
|
reg nilill;
|
reg nilill;
|
reg nililO;
|
reg nililO;
|
| Line 810... |
Line 805... |
reg niOiOi;
|
reg niOiOi;
|
reg niOiOl;
|
reg niOiOl;
|
reg niOiOO;
|
reg niOiOO;
|
reg niOl1i;
|
reg niOl1i;
|
reg niOl1l;
|
reg niOl1l;
|
|
reg nliil1i;
|
|
reg nliilii;
|
|
reg nliilil;
|
reg nliiliO;
|
reg nliiliO;
|
|
reg nliilli;
|
|
reg nliilll;
|
|
reg nliillO;
|
|
reg nliilOi;
|
|
reg nliilOl;
|
reg nliilOO;
|
reg nliilOO;
|
reg nliiO0i;
|
reg nliiOOi;
|
reg nliiO0l;
|
reg nll0iO;
|
reg nliiO0O;
|
reg nll0li;
|
reg nliiO1i;
|
reg nll0ll;
|
reg nliiO1l;
|
reg nll0Oi;
|
reg nliiO1O;
|
wire wire_nll0lO_CLRN;
|
reg nliiOii;
|
reg nll10l;
|
reg nliiOil;
|
reg nll10i_clk_prev;
|
reg nlil10O;
|
wire wire_nll10i_CLRN;
|
reg nll00i;
|
wire wire_nll10i_PRN;
|
reg nll00O;
|
reg nliOiO;
|
reg nll01l;
|
reg nll11l;
|
reg nll01O;
|
reg nll11O;
|
|
reg nll1ii;
|
|
reg nll10O_clk_prev;
|
|
wire wire_nll10O_PRN;
|
reg n0O11l;
|
reg n0O11l;
|
reg n0Oi0i;
|
reg n0Oi0i;
|
reg n1010i;
|
reg n1010i;
|
reg n1010l;
|
reg n1010l;
|
reg n1010O;
|
reg n1010O;
|
| Line 837... |
Line 843... |
reg n1011O;
|
reg n1011O;
|
reg n101ii;
|
reg n101ii;
|
reg n101il;
|
reg n101il;
|
reg n101iO;
|
reg n101iO;
|
reg n101li;
|
reg n101li;
|
reg n101ll;
|
reg n10l0i;
|
reg n101lO;
|
reg n10l0l;
|
reg n101Oi;
|
reg n10l0O;
|
reg n101Ol;
|
reg n10lii;
|
reg n10lil;
|
reg n10lil;
|
reg n10liO;
|
reg n10liO;
|
reg n10lli;
|
reg n10lli;
|
reg n10lll;
|
reg n10lll;
|
reg n10llO;
|
reg n10llO;
|
reg n10lOi;
|
reg n10lOi;
|
reg n10lOl;
|
reg n10lOl;
|
reg n10lOO;
|
reg n10lOO;
|
reg n10O0i;
|
reg n10OlO;
|
reg n10O1i;
|
reg n10OOi;
|
reg n10O1l;
|
reg n11OiO;
|
reg n10O1O;
|
reg n11Oli;
|
|
reg n11Oll;
|
|
reg n11OlO;
|
reg n11OOi;
|
reg n11OOi;
|
reg n11OOl;
|
reg n11OOl;
|
reg n11OOO;
|
reg n11OOO;
|
reg n1i10O;
|
|
reg n1i11i;
|
|
reg n1i11l;
|
reg n1i11l;
|
reg nl011i;
|
reg nl011i;
|
reg nl1l0O;
|
reg nl1l0O;
|
reg nl1Oil;
|
reg nl1Oil;
|
reg nl1OiO;
|
reg nl1OiO;
|
| Line 872... |
Line 878... |
reg nl1OOl;
|
reg nl1OOl;
|
reg nl1OOO;
|
reg nl1OOO;
|
reg nli1lO;
|
reg nli1lO;
|
reg nli1Oi;
|
reg nli1Oi;
|
reg nli1Ol;
|
reg nli1Ol;
|
|
reg nliOlOi;
|
reg nliOO0l;
|
reg nliOO0l;
|
|
reg nliOOiO;
|
|
reg nliOOli;
|
|
reg nliOOll;
|
reg nliOOlO;
|
reg nliOOlO;
|
reg nll000i;
|
reg nliOOOi;
|
reg nll00ii;
|
reg nliOOOl;
|
reg nll00il;
|
reg nliOOOO;
|
reg nll00iO;
|
reg nll001i;
|
|
reg nll001l;
|
|
reg nll010l;
|
|
reg nll010O;
|
|
reg nll01il;
|
reg nll01lO;
|
reg nll01lO;
|
reg nll01Oi;
|
|
reg nll01OO;
|
reg nll01OO;
|
reg nll0iiO;
|
reg nll0i0l;
|
reg nll0ili;
|
reg nll0i0O;
|
|
reg nll0i1l;
|
|
reg nll0ill;
|
|
reg nll0ilO;
|
|
reg nll0iOi;
|
|
reg nll0iOl;
|
reg nll0iOO;
|
reg nll0iOO;
|
reg nll0l0i;
|
reg nll0l0i;
|
reg nll0l0l;
|
reg nll0l0l;
|
reg nll0l0O;
|
reg nll0l0O;
|
reg nll0l1i;
|
reg nll0l1i;
|
reg nll0l1l;
|
reg nll0l1l;
|
reg nll0l1O;
|
reg nll0l1O;
|
reg nll0lii;
|
reg nll0lii;
|
reg nll0lil;
|
reg nll0lil;
|
reg nll0liO;
|
reg nll0liO;
|
reg nll0ll;
|
|
reg nll0lli;
|
reg nll0lli;
|
reg nll0lll;
|
reg nll0lll;
|
reg nll0llO;
|
|
reg nll0lOi;
|
|
reg nll0lOl;
|
|
reg nll0lOO;
|
|
reg nll0Oi;
|
|
reg nll0OO;
|
|
reg nll100i;
|
|
reg nll100l;
|
|
reg nll100O;
|
|
reg nll101i;
|
|
reg nll101l;
|
|
reg nll101O;
|
|
reg nll10ii;
|
|
reg nll110i;
|
reg nll110i;
|
reg nll110l;
|
reg nll110l;
|
reg nll110O;
|
reg nll110O;
|
reg nll111i;
|
reg nll111i;
|
reg nll111l;
|
reg nll111l;
|
| Line 924... |
Line 928... |
reg nll11ll;
|
reg nll11ll;
|
reg nll11lO;
|
reg nll11lO;
|
reg nll11Oi;
|
reg nll11Oi;
|
reg nll11Ol;
|
reg nll11Ol;
|
reg nll11OO;
|
reg nll11OO;
|
reg nlli1i;
|
reg nlli0l;
|
reg nlli1O;
|
reg nlli1O;
|
|
reg nlliii;
|
|
reg nlliil;
|
reg nllil0l;
|
reg nllil0l;
|
|
reg nllil0O;
|
|
reg nllil1i;
|
|
reg nllili;
|
|
reg nllilii;
|
|
reg nllilil;
|
reg nlliliO;
|
reg nlliliO;
|
reg nllilli;
|
reg nllilli;
|
reg nllilll;
|
reg nllilll;
|
reg nllillO;
|
reg nllillO;
|
reg nllilOi;
|
reg nllilOi;
|
| Line 944... |
Line 955... |
reg nlliO1O;
|
reg nlliO1O;
|
reg nlliOii;
|
reg nlliOii;
|
reg nlliOil;
|
reg nlliOil;
|
reg nlliOiO;
|
reg nlliOiO;
|
reg nlliOli;
|
reg nlliOli;
|
reg nlliOll;
|
reg nllO1lO;
|
reg nlliOlO;
|
reg nllO1Oi;
|
reg nlliOOi;
|
reg nllO1Ol;
|
reg nlliOOl;
|
reg nllOi0i;
|
reg nllO01i;
|
reg nllOi0l;
|
reg nllO01l;
|
reg nllOi1l;
|
reg nllO01O;
|
reg nllOi1O;
|
reg nllOi0O;
|
reg nllOO0i;
|
reg nllOiii;
|
|
reg nllOiil;
|
|
reg nllOiiO;
|
|
reg nllOO0l;
|
reg nllOO0l;
|
reg nllOO0O;
|
reg nllOO0O;
|
|
reg nllOO1i;
|
|
reg nllOO1l;
|
|
reg nllOO1O;
|
reg nllOOii;
|
reg nllOOii;
|
reg nllOOil;
|
reg nllOOil;
|
reg nllOOiO;
|
reg nllOOiO;
|
reg nllOOli;
|
reg nllOOli;
|
reg nllOOll;
|
reg nllOOll;
|
reg nllOOlO;
|
reg nllOOlO;
|
reg nllOOOi;
|
reg nllOOOi;
|
reg nllOOOl;
|
reg nllOOOl;
|
reg nllOOOO;
|
reg nllOOOO;
|
reg nlO100i;
|
|
reg nlO100l;
|
|
reg nlO100O;
|
|
reg nlO101i;
|
reg nlO101i;
|
reg nlO101l;
|
reg nlO101l;
|
reg nlO101O;
|
|
reg nlO110i;
|
reg nlO110i;
|
reg nlO110l;
|
reg nlO110l;
|
reg nlO110O;
|
reg nlO110O;
|
reg nlO111i;
|
reg nlO111i;
|
reg nlO111l;
|
reg nlO111l;
|
| Line 987... |
Line 994... |
reg nlO11ll;
|
reg nlO11ll;
|
reg nlO11lO;
|
reg nlO11lO;
|
reg nlO11Oi;
|
reg nlO11Oi;
|
reg nlO11Ol;
|
reg nlO11Ol;
|
reg nlO11OO;
|
reg nlO11OO;
|
reg nlOi00i;
|
|
reg nlOi00l;
|
|
reg nlOi01i;
|
reg nlOi01i;
|
reg nlOi01l;
|
|
reg nlOi01O;
|
reg nlOi01O;
|
reg nlOi0ii;
|
reg nlOi1ll;
|
|
reg nlOi1lO;
|
|
reg nlOi1Oi;
|
|
reg nlOi1Ol;
|
reg nlOi1OO;
|
reg nlOi1OO;
|
reg nlOil1i;
|
reg nlOiilO;
|
reg nlOil1l;
|
reg nlOiiOi;
|
|
reg nlOil0l;
|
|
reg nlOil0O;
|
|
reg nlOilii;
|
|
reg nlOilil;
|
reg nlOiliO;
|
reg nlOiliO;
|
reg nlOilli;
|
reg nlOilli;
|
reg nlOilll;
|
reg nlOilll;
|
reg nlOillO;
|
reg nlOillO;
|
reg nlOilOi;
|
reg nlOilOi;
|
| Line 1019... |
Line 1030... |
reg nlOiOlO;
|
reg nlOiOlO;
|
reg nlOiOOi;
|
reg nlOiOOi;
|
reg nlOiOOl;
|
reg nlOiOOl;
|
reg nlOiOOO;
|
reg nlOiOOO;
|
reg nlOl10i;
|
reg nlOl10i;
|
reg nlOl10l;
|
|
reg nlOl10O;
|
|
reg nlOl11i;
|
reg nlOl11i;
|
reg nlOl11l;
|
reg nlOl11l;
|
reg nlOl11O;
|
reg nlOl11O;
|
reg nlOl1ii;
|
reg nlOlOlO;
|
reg nlOl1il;
|
|
reg nlOO00i;
|
reg nlOO00i;
|
reg nlOO00l;
|
|
reg nlOO00O;
|
|
reg nlOO01i;
|
reg nlOO01i;
|
reg nlOO01l;
|
reg nlOO01l;
|
reg nlOO01O;
|
reg nlOO01O;
|
reg nlOO0ii;
|
reg nlOO10i;
|
reg nlOO0il;
|
reg nlOO10l;
|
reg nlOO10O;
|
reg nlOO10O;
|
reg nlOO11i;
|
reg nlOO11l;
|
|
reg nlOO1ii;
|
reg nlOO1il;
|
reg nlOO1il;
|
reg nlOO1iO;
|
reg nlOO1iO;
|
reg nlOO1li;
|
reg nlOO1li;
|
reg nlOO1ll;
|
reg nlOO1ll;
|
reg nlOO1lO;
|
reg nlOO1lO;
|
reg nlOO1Oi;
|
reg nlOO1Oi;
|
reg nlOO1Ol;
|
reg nlOO1Ol;
|
reg nlOO1OO;
|
reg nlOO1OO;
|
reg nlOOO0i;
|
reg nlOOlOO;
|
wire wire_nlli1l_CLRN;
|
reg nlliiO_clk_prev;
|
reg nl010i;
|
wire wire_nlliiO_CLRN;
|
reg nlll0l;
|
wire wire_nlliiO_PRN;
|
reg nlOO0l;
|
|
reg nlOO0i_clk_prev;
|
|
wire wire_nlOO0i_CLRN;
|
|
wire wire_nlOO0i_PRN;
|
|
reg niOO0i;
|
reg niOO0i;
|
reg niOO0l;
|
reg niOO0l;
|
reg niOO0O;
|
reg niOO0O;
|
reg niOO1i;
|
reg niOO1i;
|
reg niOO1l;
|
reg niOO1l;
|
| Line 1084... |
Line 1087... |
reg nlilOl;
|
reg nlilOl;
|
reg nliO0l;
|
reg nliO0l;
|
reg nliO0O;
|
reg nliO0O;
|
reg nliOii;
|
reg nliOii;
|
reg nliOil;
|
reg nliOil;
|
reg nll0ii;
|
reg nll00i;
|
reg nll0iO;
|
reg nll00l;
|
reg nll0li;
|
reg nll01i;
|
|
reg nll01l;
|
|
reg nll01O;
|
|
reg nll0Ol;
|
reg nll11i;
|
reg nll11i;
|
reg nll11l;
|
|
reg nll1il;
|
reg nll1il;
|
reg nll1iO;
|
reg nll1iO;
|
reg nll1li;
|
reg nll1OO;
|
reg nll1ll;
|
reg nlli1i;
|
reg nll1lO;
|
reg nlli1l;
|
reg nll1Oi;
|
reg nllill;
|
reg nlli0i;
|
|
reg nlli0O;
|
|
reg nlliii;
|
|
reg nlliil;
|
|
reg nllilO;
|
|
reg nlliOi;
|
reg nlliOi;
|
reg nlliOl;
|
reg nlliOl;
|
reg nlliOO;
|
reg nlliOO;
|
reg nlll0i;
|
reg nlll0i;
|
reg nlll1i;
|
reg nlll0l;
|
reg nlll1l;
|
reg nlll0O;
|
reg nlll1O;
|
reg nlllii;
|
reg nllO0i;
|
reg nlllil;
|
reg nllO0l;
|
reg nllliO;
|
reg nllO0O;
|
reg nlllli;
|
reg nllO1i;
|
reg nlllll;
|
reg nllO1l;
|
|
reg nllO1O;
|
|
reg nllOii;
|
|
reg nllOil;
|
reg nllOil;
|
reg nllOiO;
|
reg nllOiO;
|
reg nllOli;
|
reg nllOli;
|
reg nllOll;
|
reg nllOll;
|
reg nllOlO;
|
reg nllOlO;
|
| Line 1132... |
Line 1129... |
reg nlO01O;
|
reg nlO01O;
|
reg nlO0ii;
|
reg nlO0ii;
|
reg nlO0il;
|
reg nlO0il;
|
reg nlO0iO;
|
reg nlO0iO;
|
reg nlO0li;
|
reg nlO0li;
|
|
reg nlO0ll;
|
|
reg nlO0lO;
|
|
reg nlO0Oi;
|
|
reg nlO0Ol;
|
|
reg nlO0OO;
|
reg nlO10i;
|
reg nlO10i;
|
reg nlO10l;
|
reg nlO10l;
|
reg nlO10O;
|
reg nlO10O;
|
reg nlO11i;
|
reg nlO11i;
|
reg nlO11l;
|
reg nlO11l;
|
| Line 1147... |
Line 1149... |
reg nlO1ll;
|
reg nlO1ll;
|
reg nlO1lO;
|
reg nlO1lO;
|
reg nlO1Oi;
|
reg nlO1Oi;
|
reg nlO1Ol;
|
reg nlO1Ol;
|
reg nlO1OO;
|
reg nlO1OO;
|
reg nlOlOO;
|
reg nlOi1i;
|
reg nlOO1i;
|
reg nlOi1l;
|
reg nlOO1l;
|
|
reg nlOO1O;
|
|
reg nlOOii;
|
reg nlOOii;
|
reg nlOO0O_clk_prev;
|
reg nlOOil;
|
wire wire_nlOO0O_PRN;
|
reg nlOOiO;
|
|
reg nlOOli;
|
|
reg nlOOOi;
|
|
wire wire_nlOOlO_CLRN;
|
wire wire_n0000i_dataout;
|
wire wire_n0000i_dataout;
|
wire wire_n0000l_dataout;
|
wire wire_n0000l_dataout;
|
wire wire_n0000O_dataout;
|
wire wire_n0000O_dataout;
|
wire wire_n0001i_dataout;
|
wire wire_n0001i_dataout;
|
wire wire_n0001l_dataout;
|
wire wire_n0001l_dataout;
|
wire wire_n0001O_dataout;
|
wire wire_n0001O_dataout;
|
|
wire wire_n000i_dataout;
|
wire wire_n000ii_dataout;
|
wire wire_n000ii_dataout;
|
wire wire_n000il_dataout;
|
wire wire_n000il_dataout;
|
wire wire_n000iO_dataout;
|
wire wire_n000iO_dataout;
|
|
wire wire_n000l_dataout;
|
wire wire_n000li_dataout;
|
wire wire_n000li_dataout;
|
wire wire_n000ll_dataout;
|
wire wire_n000ll_dataout;
|
wire wire_n000lO_dataout;
|
wire wire_n000lO_dataout;
|
|
wire wire_n000O_dataout;
|
wire wire_n000Oi_dataout;
|
wire wire_n000Oi_dataout;
|
wire wire_n000Ol_dataout;
|
wire wire_n000Ol_dataout;
|
wire wire_n000OO_dataout;
|
wire wire_n000OO_dataout;
|
wire wire_n0011i_dataout;
|
|
wire wire_n0011l_dataout;
|
wire wire_n0011l_dataout;
|
|
wire wire_n0011O_dataout;
|
|
wire wire_n001i_dataout;
|
|
wire wire_n001l_dataout;
|
wire wire_n001ll_dataout;
|
wire wire_n001ll_dataout;
|
wire wire_n001lO_dataout;
|
wire wire_n001lO_dataout;
|
|
wire wire_n001O_dataout;
|
wire wire_n001Oi_dataout;
|
wire wire_n001Oi_dataout;
|
wire wire_n001Ol_dataout;
|
wire wire_n001Ol_dataout;
|
wire wire_n001OO_dataout;
|
wire wire_n001OO_dataout;
|
wire wire_n00i0i_dataout;
|
wire wire_n00i0i_dataout;
|
wire wire_n00i0l_dataout;
|
wire wire_n00i0l_dataout;
|
| Line 1196... |
Line 1205... |
wire wire_n00O1l_dataout;
|
wire wire_n00O1l_dataout;
|
wire wire_n00O1O_dataout;
|
wire wire_n00O1O_dataout;
|
wire wire_n0100i_dataout;
|
wire wire_n0100i_dataout;
|
wire wire_n0100l_dataout;
|
wire wire_n0100l_dataout;
|
wire wire_n0100O_dataout;
|
wire wire_n0100O_dataout;
|
|
wire wire_n0101i_dataout;
|
|
wire wire_n0101l_dataout;
|
|
wire wire_n0101O_dataout;
|
wire wire_n010i_dataout;
|
wire wire_n010i_dataout;
|
wire wire_n010ii_dataout;
|
wire wire_n010ii_dataout;
|
wire wire_n010il_dataout;
|
wire wire_n010il_dataout;
|
wire wire_n010iO_dataout;
|
wire wire_n010iO_dataout;
|
wire wire_n010l_dataout;
|
wire wire_n010l_dataout;
|
wire wire_n010li_dataout;
|
|
wire wire_n010ll_dataout;
|
|
wire wire_n010lO_dataout;
|
wire wire_n010lO_dataout;
|
wire wire_n010O_dataout;
|
wire wire_n010O_dataout;
|
wire wire_n010Oi_dataout;
|
wire wire_n011iO_dataout;
|
wire wire_n010Ol_dataout;
|
wire wire_n011li_dataout;
|
wire wire_n010OO_dataout;
|
wire wire_n011ll_dataout;
|
wire wire_n011l_dataout;
|
wire wire_n011lO_dataout;
|
wire wire_n011O_dataout;
|
wire wire_n011Oi_dataout;
|
wire wire_n01i0i_dataout;
|
wire wire_n011Ol_dataout;
|
wire wire_n01i1i_dataout;
|
wire wire_n011OO_dataout;
|
wire wire_n01i1l_dataout;
|
wire wire_n01i1l_dataout;
|
wire wire_n01i1O_dataout;
|
|
wire wire_n01ii_dataout;
|
wire wire_n01ii_dataout;
|
wire wire_n01iii_dataout;
|
wire wire_n01il_dataout;
|
wire wire_n01ilO_dataout;
|
wire wire_n01iO_dataout;
|
wire wire_n01Oll_dataout;
|
wire wire_n01lii_dataout;
|
|
wire wire_n01lil_dataout;
|
|
wire wire_n01liO_dataout;
|
|
wire wire_n01lll_dataout;
|
|
wire wire_n01llO_dataout;
|
|
wire wire_n01Oli_dataout;
|
wire wire_n0i00i_dataout;
|
wire wire_n0i00i_dataout;
|
wire wire_n0i00l_dataout;
|
wire wire_n0i00l_dataout;
|
wire wire_n0i00O_dataout;
|
wire wire_n0i00O_dataout;
|
wire wire_n0i01O_dataout;
|
wire wire_n0i01O_dataout;
|
wire wire_n0iilO_dataout;
|
wire wire_n0iilO_dataout;
|
| Line 1272... |
Line 1286... |
wire wire_n1000l_dataout;
|
wire wire_n1000l_dataout;
|
wire wire_n1000O_dataout;
|
wire wire_n1000O_dataout;
|
wire wire_n1001i_dataout;
|
wire wire_n1001i_dataout;
|
wire wire_n1001l_dataout;
|
wire wire_n1001l_dataout;
|
wire wire_n1001O_dataout;
|
wire wire_n1001O_dataout;
|
|
wire wire_n100i_dataout;
|
wire wire_n100ii_dataout;
|
wire wire_n100ii_dataout;
|
wire wire_n100il_dataout;
|
wire wire_n100il_dataout;
|
wire wire_n100iO_dataout;
|
wire wire_n100iO_dataout;
|
|
wire wire_n100l_dataout;
|
wire wire_n100li_dataout;
|
wire wire_n100li_dataout;
|
wire wire_n100ll_dataout;
|
wire wire_n100ll_dataout;
|
wire wire_n100lO_dataout;
|
wire wire_n100lO_dataout;
|
wire wire_n100Oi_dataout;
|
wire wire_n100Oi_dataout;
|
wire wire_n100Ol_dataout;
|
wire wire_n100Ol_dataout;
|
wire wire_n100OO_dataout;
|
wire wire_n100OO_dataout;
|
|
wire wire_n101l_dataout;
|
|
wire wire_n101lO_dataout;
|
|
wire wire_n101O_dataout;
|
|
wire wire_n101Oi_dataout;
|
|
wire wire_n101Ol_dataout;
|
|
wire wire_n101OO_dataout;
|
wire wire_n10i0i_dataout;
|
wire wire_n10i0i_dataout;
|
wire wire_n10i0l_dataout;
|
wire wire_n10i0l_dataout;
|
wire wire_n10i0O_dataout;
|
wire wire_n10i0O_dataout;
|
wire wire_n10i1i_dataout;
|
wire wire_n10i1i_dataout;
|
wire wire_n10i1l_dataout;
|
wire wire_n10i1l_dataout;
|
| Line 1296... |
Line 1318... |
wire wire_n10ill_dataout;
|
wire wire_n10ill_dataout;
|
wire wire_n10ilO_dataout;
|
wire wire_n10ilO_dataout;
|
wire wire_n10iOi_dataout;
|
wire wire_n10iOi_dataout;
|
wire wire_n10iOl_dataout;
|
wire wire_n10iOl_dataout;
|
wire wire_n10iOO_dataout;
|
wire wire_n10iOO_dataout;
|
wire wire_n10l0i_dataout;
|
|
wire wire_n10l0l_dataout;
|
|
wire wire_n10l0O_dataout;
|
|
wire wire_n10l1i_dataout;
|
wire wire_n10l1i_dataout;
|
wire wire_n10l1l_dataout;
|
wire wire_n10l1l_dataout;
|
wire wire_n10l1O_dataout;
|
wire wire_n10l1O_dataout;
|
wire wire_n10lii_dataout;
|
wire wire_n10O0i_dataout;
|
wire wire_n10O0l_dataout;
|
wire wire_n10O0l_dataout;
|
wire wire_n10O0O_dataout;
|
wire wire_n10O0O_dataout;
|
|
wire wire_n10O1i_dataout;
|
|
wire wire_n10O1l_dataout;
|
|
wire wire_n10O1O_dataout;
|
wire wire_n10Oii_dataout;
|
wire wire_n10Oii_dataout;
|
wire wire_n10Oil_dataout;
|
wire wire_n10Oil_dataout;
|
wire wire_n10OiO_dataout;
|
wire wire_n10OiO_dataout;
|
wire wire_n10Oli_dataout;
|
wire wire_n10Oli_dataout;
|
wire wire_n10Oll_dataout;
|
wire wire_n10Oll_dataout;
|
wire wire_n10OlO_dataout;
|
|
wire wire_n10OOi_dataout;
|
|
wire wire_n10OOl_dataout;
|
wire wire_n10OOl_dataout;
|
wire wire_n10OOO_dataout;
|
wire wire_n10OOO_dataout;
|
|
wire wire_n1100i_dataout;
|
|
wire wire_n1100l_dataout;
|
|
wire wire_n1100O_dataout;
|
|
wire wire_n1101O_dataout;
|
wire wire_n110ii_dataout;
|
wire wire_n110ii_dataout;
|
wire wire_n110il_dataout;
|
|
wire wire_n110iO_dataout;
|
wire wire_n110iO_dataout;
|
wire wire_n110li_dataout;
|
wire wire_n110li_dataout;
|
wire wire_n110ll_dataout;
|
wire wire_n110ll_dataout;
|
|
wire wire_n110lO_dataout;
|
wire wire_n110Oi_dataout;
|
wire wire_n110Oi_dataout;
|
wire wire_n110Ol_dataout;
|
wire wire_n110Ol_dataout;
|
wire wire_n110OO_dataout;
|
wire wire_n110OO_dataout;
|
|
wire wire_n1110O_dataout;
|
wire wire_n1111O_dataout;
|
wire wire_n1111O_dataout;
|
wire wire_n111ii_dataout;
|
wire wire_n111ii_dataout;
|
wire wire_n111li_dataout;
|
|
wire wire_n111ll_dataout;
|
|
wire wire_n11i0i_dataout;
|
wire wire_n11i0i_dataout;
|
wire wire_n11i0l_dataout;
|
|
wire wire_n11i0O_dataout;
|
|
wire wire_n11i1i_dataout;
|
wire wire_n11i1i_dataout;
|
wire wire_n11i1l_dataout;
|
wire wire_n11i1l_dataout;
|
wire wire_n11i1O_dataout;
|
wire wire_n11i1O_dataout;
|
wire wire_n11ii_dataout;
|
wire wire_n11ill_dataout;
|
wire wire_n11iii_dataout;
|
wire wire_n11ilO_dataout;
|
wire wire_n11iil_dataout;
|
wire wire_n11iOl_dataout;
|
wire wire_n11il_dataout;
|
|
wire wire_n11iO_dataout;
|
|
wire wire_n11iOO_dataout;
|
wire wire_n11iOO_dataout;
|
wire wire_n11l0i_dataout;
|
wire wire_n11l0i_dataout;
|
|
wire wire_n11l0l_dataout;
|
wire wire_n11l0O_dataout;
|
wire wire_n11l0O_dataout;
|
wire wire_n11l1i_dataout;
|
wire wire_n11l1l_dataout;
|
wire wire_n11l1O_dataout;
|
wire wire_n11l1O_dataout;
|
wire wire_n11li_dataout;
|
|
wire wire_n11lii_dataout;
|
wire wire_n11lii_dataout;
|
wire wire_n11lil_dataout;
|
wire wire_n11lil_dataout;
|
wire wire_n11liO_dataout;
|
wire wire_n11liO_dataout;
|
wire wire_n11lli_dataout;
|
wire wire_n11O0i_dataout;
|
wire wire_n11lll_dataout;
|
wire wire_n11O0l_dataout;
|
wire wire_n11llO_dataout;
|
wire wire_n1i0ll_dataout;
|
wire wire_n11lOi_dataout;
|
wire wire_n1i0lO_dataout;
|
wire wire_n11Oil_dataout;
|
wire wire_n1i0Oi_dataout;
|
wire wire_n11OiO_dataout;
|
wire wire_n1i0Ol_dataout;
|
wire wire_n1i00i_dataout;
|
|
wire wire_n1i01l_dataout;
|
|
wire wire_n1i01O_dataout;
|
|
wire wire_n1i0OO_dataout;
|
wire wire_n1i0OO_dataout;
|
wire wire_n1i10i_dataout;
|
wire wire_n1i1iO_dataout;
|
wire wire_n1i11O_dataout;
|
wire wire_n1i1li_dataout;
|
|
wire wire_n1i1ll_dataout;
|
wire wire_n1i1Oi_dataout;
|
wire wire_n1i1Oi_dataout;
|
wire wire_n1i1Ol_dataout;
|
wire wire_n1i1Ol_dataout;
|
wire wire_n1i1OO_dataout;
|
wire wire_n1i1OO_dataout;
|
wire wire_n1ii0i_dataout;
|
wire wire_n1ii0i_dataout;
|
wire wire_n1ii0l_dataout;
|
wire wire_n1ii0l_dataout;
|
wire wire_n1ii0O_dataout;
|
wire wire_n1ii0O_dataout;
|
wire wire_n1ii1i_dataout;
|
wire wire_n1ii1i_dataout;
|
wire wire_n1ii1l_dataout;
|
wire wire_n1ii1l_dataout;
|
wire wire_n1ii1O_dataout;
|
wire wire_n1ii1O_dataout;
|
wire wire_n1iii_dataout;
|
|
wire wire_n1iiii_dataout;
|
wire wire_n1iiii_dataout;
|
wire wire_n1iiil_dataout;
|
wire wire_n1iiil_dataout;
|
wire wire_n1iiiO_dataout;
|
wire wire_n1iiiO_dataout;
|
wire wire_n1iil_dataout;
|
|
wire wire_n1iili_dataout;
|
wire wire_n1iili_dataout;
|
wire wire_n1iill_dataout;
|
wire wire_n1iill_dataout;
|
wire wire_n1iilO_dataout;
|
wire wire_n1iilO_dataout;
|
wire wire_n1iiOi_dataout;
|
wire wire_n1iiOi_dataout;
|
wire wire_n1iiOl_dataout;
|
wire wire_n1iiOl_dataout;
|
| Line 1432... |
Line 1447... |
wire wire_n1l11l_dataout;
|
wire wire_n1l11l_dataout;
|
wire wire_n1l11O_dataout;
|
wire wire_n1l11O_dataout;
|
wire wire_n1l1ii_dataout;
|
wire wire_n1l1ii_dataout;
|
wire wire_n1l1il_dataout;
|
wire wire_n1l1il_dataout;
|
wire wire_n1l1iO_dataout;
|
wire wire_n1l1iO_dataout;
|
|
wire wire_n1l1l_dataout;
|
wire wire_n1l1li_dataout;
|
wire wire_n1l1li_dataout;
|
wire wire_n1l1ll_dataout;
|
wire wire_n1l1ll_dataout;
|
wire wire_n1l1lO_dataout;
|
wire wire_n1l1lO_dataout;
|
|
wire wire_n1l1O_dataout;
|
wire wire_n1l1Oi_dataout;
|
wire wire_n1l1Oi_dataout;
|
wire wire_n1l1Ol_dataout;
|
wire wire_n1l1Ol_dataout;
|
wire wire_n1l1OO_dataout;
|
wire wire_n1l1OO_dataout;
|
wire wire_n1li0i_dataout;
|
wire wire_n1li0i_dataout;
|
wire wire_n1li0l_dataout;
|
wire wire_n1li0l_dataout;
|
wire wire_n1li0O_dataout;
|
wire wire_n1li0O_dataout;
|
wire wire_n1li1i_dataout;
|
wire wire_n1li1i_dataout;
|
wire wire_n1li1l_dataout;
|
wire wire_n1li1l_dataout;
|
wire wire_n1li1O_dataout;
|
wire wire_n1li1O_dataout;
|
wire wire_n1lii_dataout;
|
|
wire wire_n1liii_dataout;
|
wire wire_n1liii_dataout;
|
wire wire_n1liil_dataout;
|
wire wire_n1liil_dataout;
|
wire wire_n1liiO_dataout;
|
wire wire_n1liiO_dataout;
|
wire wire_n1lil_dataout;
|
|
wire wire_n1lili_dataout;
|
wire wire_n1lili_dataout;
|
wire wire_n1lill_dataout;
|
wire wire_n1lill_dataout;
|
wire wire_n1lilO_dataout;
|
wire wire_n1lilO_dataout;
|
wire wire_n1liO_dataout;
|
|
wire wire_n1liOi_dataout;
|
wire wire_n1liOi_dataout;
|
wire wire_n1liOl_dataout;
|
wire wire_n1liOl_dataout;
|
wire wire_n1liOO_dataout;
|
wire wire_n1liOO_dataout;
|
wire wire_n1ll0i_dataout;
|
wire wire_n1ll0i_dataout;
|
wire wire_n1ll0l_dataout;
|
wire wire_n1ll0l_dataout;
|
wire wire_n1ll0O_dataout;
|
wire wire_n1ll0O_dataout;
|
wire wire_n1ll1i_dataout;
|
wire wire_n1ll1i_dataout;
|
wire wire_n1ll1l_dataout;
|
wire wire_n1ll1l_dataout;
|
wire wire_n1ll1O_dataout;
|
wire wire_n1ll1O_dataout;
|
wire wire_n1lli_dataout;
|
|
wire wire_n1llii_dataout;
|
wire wire_n1llii_dataout;
|
wire wire_n1llil_dataout;
|
wire wire_n1llil_dataout;
|
wire wire_n1lliO_dataout;
|
wire wire_n1lliO_dataout;
|
wire wire_n1llli_dataout;
|
wire wire_n1llli_dataout;
|
wire wire_n1llll_dataout;
|
wire wire_n1llll_dataout;
|
| Line 1519... |
Line 1532... |
wire wire_n1O1ll_dataout;
|
wire wire_n1O1ll_dataout;
|
wire wire_n1O1lO_dataout;
|
wire wire_n1O1lO_dataout;
|
wire wire_n1O1Oi_dataout;
|
wire wire_n1O1Oi_dataout;
|
wire wire_n1O1Ol_dataout;
|
wire wire_n1O1Ol_dataout;
|
wire wire_n1O1OO_dataout;
|
wire wire_n1O1OO_dataout;
|
wire wire_n1Oi0i_dataout;
|
|
wire wire_n1Oi0l_dataout;
|
wire wire_n1Oi0l_dataout;
|
wire wire_n1Oi1i_dataout;
|
wire wire_n1Oi1i_dataout;
|
wire wire_n1Oi1l_dataout;
|
|
wire wire_n1Oi1O_dataout;
|
|
wire wire_n1Oii_dataout;
|
wire wire_n1Oii_dataout;
|
wire wire_n1OiiO_dataout;
|
wire wire_n1Oiil_dataout;
|
wire wire_n1Oil_dataout;
|
wire wire_n1Oil_dataout;
|
wire wire_n1OilO_dataout;
|
wire wire_n1Oili_dataout;
|
wire wire_n1OiO_dataout;
|
wire wire_n1Ol0i_dataout;
|
wire wire_n1OiOl_dataout;
|
wire wire_n1Ol0l_dataout;
|
wire wire_n1Oli_dataout;
|
wire wire_n1Ol0O_dataout;
|
|
wire wire_n1Ol1O_dataout;
|
wire wire_n1Olii_dataout;
|
wire wire_n1Olii_dataout;
|
wire wire_n1Olil_dataout;
|
|
wire wire_n1OliO_dataout;
|
|
wire wire_n1Olli_dataout;
|
|
wire wire_n1Olll_dataout;
|
wire wire_n1Olll_dataout;
|
|
wire wire_n1OllO_dataout;
|
wire wire_n1OlOi_dataout;
|
wire wire_n1OlOi_dataout;
|
wire wire_n1OlOl_dataout;
|
wire wire_n1OlOl_dataout;
|
wire wire_n1OlOO_dataout;
|
wire wire_n1OlOO_dataout;
|
wire wire_n1OO0O_dataout;
|
|
wire wire_n1OO1i_dataout;
|
|
wire wire_n1OO1l_dataout;
|
|
wire wire_n1OOii_dataout;
|
|
wire wire_n1OOil_dataout;
|
|
wire wire_n1OOiO_dataout;
|
|
wire wire_n1OOli_dataout;
|
|
wire wire_ni01il_dataout;
|
wire wire_ni01il_dataout;
|
wire wire_ni01iO_dataout;
|
wire wire_ni01iO_dataout;
|
wire wire_ni01li_dataout;
|
wire wire_ni01li_dataout;
|
wire wire_ni01ll_dataout;
|
wire wire_ni01ll_dataout;
|
wire wire_ni0i0i_dataout;
|
wire wire_ni0i0i_dataout;
|
| Line 1611... |
Line 1613... |
wire wire_niiOll_dataout;
|
wire wire_niiOll_dataout;
|
wire wire_niiOlO_dataout;
|
wire wire_niiOlO_dataout;
|
wire wire_nil10l_dataout;
|
wire wire_nil10l_dataout;
|
wire wire_nil10O_dataout;
|
wire wire_nil10O_dataout;
|
wire wire_nil1iO_dataout;
|
wire wire_nil1iO_dataout;
|
wire wire_nil1l_dataout;
|
|
wire wire_nil1li_dataout;
|
wire wire_nil1li_dataout;
|
wire wire_nil1O_dataout;
|
|
wire wire_nill0O_dataout;
|
wire wire_nill0O_dataout;
|
wire wire_nillii_dataout;
|
wire wire_nillii_dataout;
|
wire wire_nillil_dataout;
|
wire wire_nillil_dataout;
|
wire wire_nilliO_dataout;
|
wire wire_nilliO_dataout;
|
wire wire_nillli_dataout;
|
wire wire_nillli_dataout;
|
| Line 1636... |
Line 1636... |
wire wire_nilOil_dataout;
|
wire wire_nilOil_dataout;
|
wire wire_nilOiO_dataout;
|
wire wire_nilOiO_dataout;
|
wire wire_nilOli_dataout;
|
wire wire_nilOli_dataout;
|
wire wire_niO0ll_dataout;
|
wire wire_niO0ll_dataout;
|
wire wire_niO1iO_dataout;
|
wire wire_niO1iO_dataout;
|
|
wire wire_niO1l_dataout;
|
wire wire_niO1li_dataout;
|
wire wire_niO1li_dataout;
|
|
wire wire_niO1O_dataout;
|
wire wire_niOi0l_dataout;
|
wire wire_niOi0l_dataout;
|
wire wire_niOi1i_dataout;
|
wire wire_niOi1i_dataout;
|
wire wire_niOilO_dataout;
|
wire wire_niOilO_dataout;
|
wire wire_nl000i_dataout;
|
wire wire_nl000i_dataout;
|
wire wire_nl00il_dataout;
|
wire wire_nl00il_dataout;
|
| Line 1650... |
Line 1652... |
wire wire_nl01il_dataout;
|
wire wire_nl01il_dataout;
|
wire wire_nl01iO_dataout;
|
wire wire_nl01iO_dataout;
|
wire wire_nl01li_dataout;
|
wire wire_nl01li_dataout;
|
wire wire_nl01ll_dataout;
|
wire wire_nl01ll_dataout;
|
wire wire_nl01lO_dataout;
|
wire wire_nl01lO_dataout;
|
wire wire_nl01O_dataout;
|
|
wire wire_nl01Oi_dataout;
|
wire wire_nl01Oi_dataout;
|
wire wire_nl01Ol_dataout;
|
wire wire_nl01Ol_dataout;
|
wire wire_nl01OO_dataout;
|
wire wire_nl01OO_dataout;
|
wire wire_nl101i_dataout;
|
wire wire_nl101i_dataout;
|
wire wire_nl101l_dataout;
|
wire wire_nl101l_dataout;
|
| Line 1690... |
Line 1691... |
wire wire_nl1Oii_dataout;
|
wire wire_nl1Oii_dataout;
|
wire wire_nli01i_dataout;
|
wire wire_nli01i_dataout;
|
wire wire_nli01l_dataout;
|
wire wire_nli01l_dataout;
|
wire wire_nli1ii_dataout;
|
wire wire_nli1ii_dataout;
|
wire wire_nli1il_dataout;
|
wire wire_nli1il_dataout;
|
|
wire wire_nli1l_dataout;
|
wire wire_nlii0l_dataout;
|
wire wire_nlii0l_dataout;
|
wire wire_nlii0O_dataout;
|
wire wire_nlii0O_dataout;
|
wire wire_nliiii_dataout;
|
wire wire_nliiii_dataout;
|
wire wire_nliiil_dataout;
|
wire wire_nliiil_dataout;
|
wire wire_nliiiO_dataout;
|
wire wire_nliiiO_dataout;
|
|
wire wire_nliil1l_dataout;
|
|
wire wire_nliil1O_dataout;
|
wire wire_nliili_dataout;
|
wire wire_nliili_dataout;
|
wire wire_nliilli_dataout;
|
wire wire_nliiO0i_dataout;
|
wire wire_nliilll_dataout;
|
wire wire_nliiO0l_dataout;
|
|
wire wire_nliiO0O_dataout;
|
|
wire wire_nliiO1i_dataout;
|
|
wire wire_nliiO1l_dataout;
|
|
wire wire_nliiO1O_dataout;
|
|
wire wire_nliiOil_dataout;
|
wire wire_nliiOiO_dataout;
|
wire wire_nliiOiO_dataout;
|
wire wire_nliiOli_dataout;
|
wire wire_nliiOli_dataout;
|
wire wire_nliiOll_dataout;
|
wire wire_nlil00i_dataout;
|
wire wire_nliiOlO_dataout;
|
wire wire_nlil00l_dataout;
|
wire wire_nliiOOi_dataout;
|
wire wire_nlil00O_dataout;
|
wire wire_nliiOOl_dataout;
|
wire wire_nlil0ii_dataout;
|
|
wire wire_nlil0il_dataout;
|
|
wire wire_nlil0iO_dataout;
|
|
wire wire_nlil0ll_dataout;
|
wire wire_nlil0lO_dataout;
|
wire wire_nlil0lO_dataout;
|
wire wire_nlil0Oi_dataout;
|
wire wire_nlil0Oi_dataout;
|
wire wire_nlil0Ol_dataout;
|
wire wire_nlil10l_dataout;
|
wire wire_nlil0OO_dataout;
|
wire wire_nlil10O_dataout;
|
wire wire_nlil11i_dataout;
|
|
wire wire_nlil11l_dataout;
|
|
wire wire_nlil11O_dataout;
|
|
wire wire_nlil1Oi_dataout;
|
|
wire wire_nlil1Ol_dataout;
|
|
wire wire_nlili0i_dataout;
|
|
wire wire_nlili0l_dataout;
|
|
wire wire_nlili0O_dataout;
|
|
wire wire_nlili1i_dataout;
|
|
wire wire_nlili1l_dataout;
|
|
wire wire_nlilli_dataout;
|
wire wire_nlilli_dataout;
|
wire wire_nlilll_dataout;
|
wire wire_nlilll_dataout;
|
wire wire_nlilOO_dataout;
|
wire wire_nlilOO_dataout;
|
wire wire_nliO1i_dataout;
|
wire wire_nliO1i_dataout;
|
|
wire wire_nliOll_dataout;
|
|
wire wire_nliOlO_dataout;
|
|
wire wire_nliOlOl_dataout;
|
|
wire wire_nliOlOO_dataout;
|
|
wire wire_nliOO0i_dataout;
|
wire wire_nliOO0O_dataout;
|
wire wire_nliOO0O_dataout;
|
|
wire wire_nliOO1i_dataout;
|
wire wire_nliOOii_dataout;
|
wire wire_nliOOii_dataout;
|
wire wire_nliOOil_dataout;
|
wire wire_nliOOil_dataout;
|
wire wire_nliOOll_dataout;
|
wire wire_nliOOO_dataout;
|
wire wire_nliOOOi_dataout;
|
wire wire_nll000i_dataout;
|
wire wire_nliOOOl_dataout;
|
|
wire wire_nliOOOO_dataout;
|
|
wire wire_nll000l_dataout;
|
wire wire_nll000l_dataout;
|
wire wire_nll001i_dataout;
|
wire wire_nll000O_dataout;
|
wire wire_nll001l_dataout;
|
|
wire wire_nll001O_dataout;
|
wire wire_nll001O_dataout;
|
|
wire wire_nll00ii_dataout;
|
|
wire wire_nll00il_dataout;
|
|
wire wire_nll00iO_dataout;
|
wire wire_nll00li_dataout;
|
wire wire_nll00li_dataout;
|
wire wire_nll00ll_dataout;
|
wire wire_nll00ll_dataout;
|
wire wire_nll00lO_dataout;
|
wire wire_nll00lO_dataout;
|
wire wire_nll00Oi_dataout;
|
wire wire_nll00Oi_dataout;
|
wire wire_nll00Ol_dataout;
|
wire wire_nll00Ol_dataout;
|
wire wire_nll00OO_dataout;
|
|
wire wire_nll010i_dataout;
|
|
wire wire_nll010l_dataout;
|
|
wire wire_nll010O_dataout;
|
|
wire wire_nll011i_dataout;
|
wire wire_nll011i_dataout;
|
wire wire_nll011l_dataout;
|
wire wire_nll011l_dataout;
|
wire wire_nll011O_dataout;
|
wire wire_nll011O_dataout;
|
wire wire_nll01ii_dataout;
|
wire wire_nll01ii_dataout;
|
wire wire_nll01il_dataout;
|
|
wire wire_nll01iO_dataout;
|
wire wire_nll01iO_dataout;
|
wire wire_nll01li_dataout;
|
wire wire_nll01li_dataout;
|
wire wire_nll01Ol_dataout;
|
wire wire_nll01ll_dataout;
|
wire wire_nll0i0i_dataout;
|
wire wire_nll01Oi_dataout;
|
wire wire_nll0i0l_dataout;
|
|
wire wire_nll0i0O_dataout;
|
|
wire wire_nll0i1i_dataout;
|
|
wire wire_nll0i1l_dataout;
|
|
wire wire_nll0i1O_dataout;
|
wire wire_nll0i1O_dataout;
|
wire wire_nll0ill_dataout;
|
wire wire_nll0iii_dataout;
|
wire wire_nll0ilO_dataout;
|
wire wire_nll0iil_dataout;
|
wire wire_nll0lO_dataout;
|
wire wire_nll0llO_dataout;
|
|
wire wire_nll0lOi_dataout;
|
|
wire wire_nll0lOl_dataout;
|
|
wire wire_nll0lOO_dataout;
|
wire wire_nll0O0i_dataout;
|
wire wire_nll0O0i_dataout;
|
wire wire_nll0O0l_dataout;
|
wire wire_nll0O0l_dataout;
|
wire wire_nll0O0O_dataout;
|
wire wire_nll0O0O_dataout;
|
wire wire_nll0O1i_dataout;
|
wire wire_nll0O1i_dataout;
|
wire wire_nll0O1l_dataout;
|
wire wire_nll0O1l_dataout;
|
| Line 1774... |
Line 1776... |
wire wire_nll0Oll_dataout;
|
wire wire_nll0Oll_dataout;
|
wire wire_nll0OlO_dataout;
|
wire wire_nll0OlO_dataout;
|
wire wire_nll0OOi_dataout;
|
wire wire_nll0OOi_dataout;
|
wire wire_nll0OOl_dataout;
|
wire wire_nll0OOl_dataout;
|
wire wire_nll0OOO_dataout;
|
wire wire_nll0OOO_dataout;
|
wire wire_nll10i_dataout;
|
wire wire_nll100i_dataout;
|
|
wire wire_nll100l_dataout;
|
|
wire wire_nll100O_dataout;
|
|
wire wire_nll101i_dataout;
|
|
wire wire_nll101l_dataout;
|
|
wire wire_nll101O_dataout;
|
|
wire wire_nll10ii_dataout;
|
wire wire_nll10il_dataout;
|
wire wire_nll10il_dataout;
|
wire wire_nll10iO_dataout;
|
wire wire_nll10iO_dataout;
|
wire wire_nll10l_dataout;
|
|
wire wire_nll10li_dataout;
|
wire wire_nll10li_dataout;
|
wire wire_nll10ll_dataout;
|
wire wire_nll10ll_dataout;
|
wire wire_nll10lO_dataout;
|
wire wire_nll10lO_dataout;
|
wire wire_nll10O_dataout;
|
|
wire wire_nll10Oi_dataout;
|
wire wire_nll10Oi_dataout;
|
wire wire_nll10Ol_dataout;
|
wire wire_nll10Ol_dataout;
|
wire wire_nll10OO_dataout;
|
wire wire_nll10OO_dataout;
|
wire wire_nll11O_dataout;
|
|
wire wire_nll1i0i_dataout;
|
wire wire_nll1i0i_dataout;
|
wire wire_nll1i0l_dataout;
|
wire wire_nll1i0l_dataout;
|
wire wire_nll1i0O_dataout;
|
wire wire_nll1i0O_dataout;
|
wire wire_nll1i1i_dataout;
|
wire wire_nll1i1i_dataout;
|
wire wire_nll1i1l_dataout;
|
wire wire_nll1i1l_dataout;
|
| Line 1807... |
Line 1812... |
wire wire_nll1l0l_dataout;
|
wire wire_nll1l0l_dataout;
|
wire wire_nll1l0O_dataout;
|
wire wire_nll1l0O_dataout;
|
wire wire_nll1l1i_dataout;
|
wire wire_nll1l1i_dataout;
|
wire wire_nll1l1l_dataout;
|
wire wire_nll1l1l_dataout;
|
wire wire_nll1l1O_dataout;
|
wire wire_nll1l1O_dataout;
|
|
wire wire_nll1li_dataout;
|
wire wire_nll1lii_dataout;
|
wire wire_nll1lii_dataout;
|
wire wire_nll1lil_dataout;
|
wire wire_nll1lil_dataout;
|
wire wire_nll1liO_dataout;
|
wire wire_nll1liO_dataout;
|
|
wire wire_nll1ll_dataout;
|
wire wire_nll1lli_dataout;
|
wire wire_nll1lli_dataout;
|
wire wire_nll1lll_dataout;
|
wire wire_nll1lll_dataout;
|
wire wire_nll1llO_dataout;
|
wire wire_nll1llO_dataout;
|
|
wire wire_nll1lO_dataout;
|
wire wire_nll1lOi_dataout;
|
wire wire_nll1lOi_dataout;
|
wire wire_nll1lOl_dataout;
|
wire wire_nll1lOl_dataout;
|
wire wire_nll1lOO_dataout;
|
wire wire_nll1lOO_dataout;
|
wire wire_nll1O0i_dataout;
|
wire wire_nll1O0i_dataout;
|
wire wire_nll1O0l_dataout;
|
wire wire_nll1O0l_dataout;
|
wire wire_nll1O0O_dataout;
|
wire wire_nll1O0O_dataout;
|
wire wire_nll1O1i_dataout;
|
wire wire_nll1O1i_dataout;
|
wire wire_nll1O1l_dataout;
|
wire wire_nll1O1l_dataout;
|
wire wire_nll1O1O_dataout;
|
wire wire_nll1O1O_dataout;
|
|
wire wire_nll1Oi_dataout;
|
wire wire_nll1Oii_dataout;
|
wire wire_nll1Oii_dataout;
|
wire wire_nll1Oil_dataout;
|
wire wire_nll1Oil_dataout;
|
wire wire_nll1OiO_dataout;
|
wire wire_nll1OiO_dataout;
|
wire wire_nll1Oli_dataout;
|
wire wire_nll1Oli_dataout;
|
wire wire_nll1Oll_dataout;
|
wire wire_nll1Oll_dataout;
|
| Line 1837... |
Line 1846... |
wire wire_nlli00l_dataout;
|
wire wire_nlli00l_dataout;
|
wire wire_nlli00O_dataout;
|
wire wire_nlli00O_dataout;
|
wire wire_nlli01i_dataout;
|
wire wire_nlli01i_dataout;
|
wire wire_nlli01l_dataout;
|
wire wire_nlli01l_dataout;
|
wire wire_nlli01O_dataout;
|
wire wire_nlli01O_dataout;
|
|
wire wire_nlli0i_dataout;
|
wire wire_nlli0ii_dataout;
|
wire wire_nlli0ii_dataout;
|
wire wire_nlli0il_dataout;
|
wire wire_nlli0il_dataout;
|
wire wire_nlli0iO_dataout;
|
wire wire_nlli0iO_dataout;
|
wire wire_nlli0li_dataout;
|
wire wire_nlli0li_dataout;
|
wire wire_nlli0ll_dataout;
|
wire wire_nlli0ll_dataout;
|
| Line 1873... |
Line 1883... |
wire wire_nlliiil_dataout;
|
wire wire_nlliiil_dataout;
|
wire wire_nlliiiO_dataout;
|
wire wire_nlliiiO_dataout;
|
wire wire_nlliili_dataout;
|
wire wire_nlliili_dataout;
|
wire wire_nlliill_dataout;
|
wire wire_nlliill_dataout;
|
wire wire_nlliilO_dataout;
|
wire wire_nlliilO_dataout;
|
wire wire_nlliiO_dataout;
|
|
wire wire_nlliiOi_dataout;
|
wire wire_nlliiOi_dataout;
|
wire wire_nlliiOl_dataout;
|
wire wire_nlliiOl_dataout;
|
wire wire_nlliiOO_dataout;
|
wire wire_nlliiOO_dataout;
|
wire wire_nllil0i_dataout;
|
|
wire wire_nllil0O_dataout;
|
|
wire wire_nllil1i_dataout;
|
|
wire wire_nllil1l_dataout;
|
wire wire_nllil1l_dataout;
|
wire wire_nllil1O_dataout;
|
wire wire_nllil1O_dataout;
|
wire wire_nllilii_dataout;
|
wire wire_nlliOll_dataout;
|
|
wire wire_nlliOlO_dataout;
|
|
wire wire_nlliOOi_dataout;
|
|
wire wire_nlliOOl_dataout;
|
wire wire_nlliOOO_dataout;
|
wire wire_nlliOOO_dataout;
|
wire wire_nlll00i_dataout;
|
wire wire_nlll00i_dataout;
|
wire wire_nlll00l_dataout;
|
wire wire_nlll00l_dataout;
|
wire wire_nlll00O_dataout;
|
wire wire_nlll00O_dataout;
|
wire wire_nlll01i_dataout;
|
wire wire_nlll01i_dataout;
|
| Line 1896... |
Line 1905... |
wire wire_nlll0il_dataout;
|
wire wire_nlll0il_dataout;
|
wire wire_nlll0iO_dataout;
|
wire wire_nlll0iO_dataout;
|
wire wire_nlll0li_dataout;
|
wire wire_nlll0li_dataout;
|
wire wire_nlll0ll_dataout;
|
wire wire_nlll0ll_dataout;
|
wire wire_nlll0lO_dataout;
|
wire wire_nlll0lO_dataout;
|
wire wire_nlll0O_dataout;
|
|
wire wire_nlll0Oi_dataout;
|
wire wire_nlll0Oi_dataout;
|
wire wire_nlll0Ol_dataout;
|
wire wire_nlll0Ol_dataout;
|
wire wire_nlll0OO_dataout;
|
wire wire_nlll0OO_dataout;
|
wire wire_nlll10i_dataout;
|
wire wire_nlll10i_dataout;
|
wire wire_nlll10l_dataout;
|
wire wire_nlll10l_dataout;
|
wire wire_nlll10O_dataout;
|
wire wire_nlll10O_dataout;
|
wire wire_nlll11i_dataout;
|
wire wire_nlll11i_dataout;
|
wire wire_nlll11l_dataout;
|
wire wire_nlll11l_dataout;
|
wire wire_nlll11O_dataout;
|
wire wire_nlll11O_dataout;
|
|
wire wire_nlll1i_dataout;
|
wire wire_nlll1ii_dataout;
|
wire wire_nlll1ii_dataout;
|
wire wire_nlll1il_dataout;
|
wire wire_nlll1il_dataout;
|
wire wire_nlll1iO_dataout;
|
wire wire_nlll1iO_dataout;
|
wire wire_nlll1li_dataout;
|
wire wire_nlll1li_dataout;
|
wire wire_nlll1ll_dataout;
|
wire wire_nlll1ll_dataout;
|
| Line 1921... |
Line 1930... |
wire wire_nllli0l_dataout;
|
wire wire_nllli0l_dataout;
|
wire wire_nllli0O_dataout;
|
wire wire_nllli0O_dataout;
|
wire wire_nllli1i_dataout;
|
wire wire_nllli1i_dataout;
|
wire wire_nllli1l_dataout;
|
wire wire_nllli1l_dataout;
|
wire wire_nllli1O_dataout;
|
wire wire_nllli1O_dataout;
|
wire wire_nlllii_dataout;
|
|
wire wire_nllliii_dataout;
|
wire wire_nllliii_dataout;
|
wire wire_nllliil_dataout;
|
wire wire_nllliil_dataout;
|
wire wire_nllliiO_dataout;
|
wire wire_nllliiO_dataout;
|
wire wire_nlllil_dataout;
|
|
wire wire_nlllili_dataout;
|
wire wire_nlllili_dataout;
|
wire wire_nlllill_dataout;
|
wire wire_nlllill_dataout;
|
wire wire_nlllilO_dataout;
|
wire wire_nlllilO_dataout;
|
wire wire_nllliO_dataout;
|
|
wire wire_nllliOi_dataout;
|
wire wire_nllliOi_dataout;
|
wire wire_nllliOl_dataout;
|
wire wire_nllliOl_dataout;
|
wire wire_nllliOO_dataout;
|
wire wire_nllliOO_dataout;
|
wire wire_nllll0i_dataout;
|
wire wire_nllll0i_dataout;
|
wire wire_nllll0l_dataout;
|
wire wire_nllll0l_dataout;
|
wire wire_nllll0O_dataout;
|
wire wire_nllll0O_dataout;
|
wire wire_nllll1i_dataout;
|
wire wire_nllll1i_dataout;
|
wire wire_nllll1l_dataout;
|
wire wire_nllll1l_dataout;
|
wire wire_nllll1O_dataout;
|
wire wire_nllll1O_dataout;
|
wire wire_nlllli_dataout;
|
|
wire wire_nllllii_dataout;
|
wire wire_nllllii_dataout;
|
wire wire_nllllil_dataout;
|
wire wire_nllllil_dataout;
|
wire wire_nlllliO_dataout;
|
wire wire_nlllliO_dataout;
|
wire wire_nlllll_dataout;
|
|
wire wire_nllllli_dataout;
|
wire wire_nllllli_dataout;
|
wire wire_nllllll_dataout;
|
wire wire_nllllll_dataout;
|
wire wire_nlllllO_dataout;
|
wire wire_nlllllO_dataout;
|
wire wire_nllllO_dataout;
|
|
wire wire_nllllOi_dataout;
|
wire wire_nllllOi_dataout;
|
wire wire_nllllOl_dataout;
|
wire wire_nllllOl_dataout;
|
wire wire_nllllOO_dataout;
|
wire wire_nllllOO_dataout;
|
wire wire_nlllO0i_dataout;
|
wire wire_nlllO0i_dataout;
|
wire wire_nlllO0l_dataout;
|
wire wire_nlllO0l_dataout;
|
| Line 1961... |
Line 1964... |
wire wire_nlllO1O_dataout;
|
wire wire_nlllO1O_dataout;
|
wire wire_nlllOi_dataout;
|
wire wire_nlllOi_dataout;
|
wire wire_nlllOii_dataout;
|
wire wire_nlllOii_dataout;
|
wire wire_nlllOil_dataout;
|
wire wire_nlllOil_dataout;
|
wire wire_nlllOiO_dataout;
|
wire wire_nlllOiO_dataout;
|
|
wire wire_nlllOl_dataout;
|
wire wire_nlllOli_dataout;
|
wire wire_nlllOli_dataout;
|
wire wire_nlllOll_dataout;
|
wire wire_nlllOll_dataout;
|
wire wire_nlllOlO_dataout;
|
wire wire_nlllOlO_dataout;
|
|
wire wire_nlllOO_dataout;
|
wire wire_nlllOOi_dataout;
|
wire wire_nlllOOi_dataout;
|
wire wire_nlllOOl_dataout;
|
wire wire_nlllOOl_dataout;
|
wire wire_nlllOOO_dataout;
|
wire wire_nlllOOO_dataout;
|
wire wire_nllO00i_dataout;
|
wire wire_nllO01i_dataout;
|
wire wire_nllO00l_dataout;
|
wire wire_nllO01l_dataout;
|
wire wire_nllO00O_dataout;
|
wire wire_nllO0i_dataout;
|
|
wire wire_nllO0l_dataout;
|
wire wire_nllO10i_dataout;
|
wire wire_nllO10i_dataout;
|
wire wire_nllO10l_dataout;
|
|
wire wire_nllO10O_dataout;
|
|
wire wire_nllO11i_dataout;
|
wire wire_nllO11i_dataout;
|
wire wire_nllO11l_dataout;
|
wire wire_nllO11l_dataout;
|
wire wire_nllO11O_dataout;
|
wire wire_nllO11O_dataout;
|
wire wire_nllO1ii_dataout;
|
wire wire_nllO1i_dataout;
|
wire wire_nllO1il_dataout;
|
wire wire_nllO1l_dataout;
|
|
wire wire_nllO1O_dataout;
|
|
wire wire_nllO1OO_dataout;
|
|
wire wire_nllOi0O_dataout;
|
|
wire wire_nllOiii_dataout;
|
|
wire wire_nllOiil_dataout;
|
|
wire wire_nllOiiO_dataout;
|
wire wire_nllOili_dataout;
|
wire wire_nllOili_dataout;
|
wire wire_nllOill_dataout;
|
wire wire_nllOill_dataout;
|
wire wire_nllOilO_dataout;
|
wire wire_nllOilO_dataout;
|
wire wire_nllOiOi_dataout;
|
wire wire_nllOiOi_dataout;
|
wire wire_nllOiOl_dataout;
|
wire wire_nllOiOl_dataout;
|
wire wire_nllOiOO_dataout;
|
wire wire_nllOiOO_dataout;
|
wire wire_nllOl0i_dataout;
|
|
wire wire_nllOl0l_dataout;
|
wire wire_nllOl0l_dataout;
|
wire wire_nllOl0O_dataout;
|
wire wire_nllOl0O_dataout;
|
wire wire_nllOl1i_dataout;
|
wire wire_nllOl1i_dataout;
|
wire wire_nllOl1l_dataout;
|
wire wire_nllOl1l_dataout;
|
wire wire_nllOl1O_dataout;
|
wire wire_nllOlii_dataout;
|
|
wire wire_nllOlil_dataout;
|
wire wire_nllOliO_dataout;
|
wire wire_nllOliO_dataout;
|
wire wire_nllOlli_dataout;
|
wire wire_nllOlli_dataout;
|
wire wire_nllOlll_dataout;
|
wire wire_nllOlll_dataout;
|
wire wire_nllOllO_dataout;
|
wire wire_nllOllO_dataout;
|
wire wire_nllOlOi_dataout;
|
|
wire wire_nllOlOl_dataout;
|
|
wire wire_nllOlOO_dataout;
|
|
wire wire_nllOO1i_dataout;
|
|
wire wire_nlO000i_dataout;
|
wire wire_nlO000i_dataout;
|
wire wire_nlO000l_dataout;
|
wire wire_nlO000l_dataout;
|
wire wire_nlO000O_dataout;
|
wire wire_nlO000O_dataout;
|
wire wire_nlO001i_dataout;
|
wire wire_nlO001i_dataout;
|
wire wire_nlO001l_dataout;
|
wire wire_nlO001l_dataout;
|
wire wire_nlO001O_dataout;
|
wire wire_nlO001O_dataout;
|
wire wire_nlO00ii_dataout;
|
|
wire wire_nlO00il_dataout;
|
wire wire_nlO00il_dataout;
|
wire wire_nlO00iO_dataout;
|
wire wire_nlO00iO_dataout;
|
wire wire_nlO00li_dataout;
|
wire wire_nlO00li_dataout;
|
|
wire wire_nlO00ll_dataout;
|
wire wire_nlO00lO_dataout;
|
wire wire_nlO00lO_dataout;
|
wire wire_nlO00Oi_dataout;
|
wire wire_nlO00Oi_dataout;
|
wire wire_nlO00Ol_dataout;
|
wire wire_nlO00Ol_dataout;
|
wire wire_nlO00OO_dataout;
|
wire wire_nlO00OO_dataout;
|
wire wire_nlO010i_dataout;
|
wire wire_nlO010i_dataout;
|
| Line 2051... |
Line 2057... |
wire wire_nlO0l1l_dataout;
|
wire wire_nlO0l1l_dataout;
|
wire wire_nlO0l1O_dataout;
|
wire wire_nlO0l1O_dataout;
|
wire wire_nlO0lii_dataout;
|
wire wire_nlO0lii_dataout;
|
wire wire_nlO0lil_dataout;
|
wire wire_nlO0lil_dataout;
|
wire wire_nlO0liO_dataout;
|
wire wire_nlO0liO_dataout;
|
wire wire_nlO0ll_dataout;
|
wire wire_nlO0Oll_dataout;
|
wire wire_nlO0lli_dataout;
|
wire wire_nlO0OlO_dataout;
|
wire wire_nlO0lll_dataout;
|
wire wire_nlO0OOl_dataout;
|
wire wire_nlO0llO_dataout;
|
|
wire wire_nlO0lOi_dataout;
|
|
wire wire_nlO0OOO_dataout;
|
wire wire_nlO0OOO_dataout;
|
|
wire wire_nlO100i_dataout;
|
|
wire wire_nlO100l_dataout;
|
|
wire wire_nlO100O_dataout;
|
|
wire wire_nlO101O_dataout;
|
wire wire_nlO10ii_dataout;
|
wire wire_nlO10ii_dataout;
|
wire wire_nlO10il_dataout;
|
wire wire_nlO10il_dataout;
|
wire wire_nlO10iO_dataout;
|
wire wire_nlO10iO_dataout;
|
wire wire_nlO10li_dataout;
|
wire wire_nlO10li_dataout;
|
wire wire_nlO10ll_dataout;
|
wire wire_nlO10ll_dataout;
|
| Line 2111... |
Line 2119... |
wire wire_nlO1Oll_dataout;
|
wire wire_nlO1Oll_dataout;
|
wire wire_nlO1OlO_dataout;
|
wire wire_nlO1OlO_dataout;
|
wire wire_nlO1OOi_dataout;
|
wire wire_nlO1OOi_dataout;
|
wire wire_nlO1OOl_dataout;
|
wire wire_nlO1OOl_dataout;
|
wire wire_nlO1OOO_dataout;
|
wire wire_nlO1OOO_dataout;
|
|
wire wire_nlOi00i_dataout;
|
|
wire wire_nlOi00l_dataout;
|
|
wire wire_nlOi00O_dataout;
|
|
wire wire_nlOi0ii_dataout;
|
wire wire_nlOi0il_dataout;
|
wire wire_nlOi0il_dataout;
|
wire wire_nlOi0iO_dataout;
|
wire wire_nlOi0iO_dataout;
|
wire wire_nlOi0li_dataout;
|
wire wire_nlOi0li_dataout;
|
wire wire_nlOi0ll_dataout;
|
wire wire_nlOi0ll_dataout;
|
wire wire_nlOi0lO_dataout;
|
|
wire wire_nlOi0Oi_dataout;
|
|
wire wire_nlOi0Ol_dataout;
|
|
wire wire_nlOi0OO_dataout;
|
|
wire wire_nlOi10i_dataout;
|
wire wire_nlOi10i_dataout;
|
wire wire_nlOi11i_dataout;
|
wire wire_nlOi10l_dataout;
|
|
wire wire_nlOi10O_dataout;
|
wire wire_nlOi11O_dataout;
|
wire wire_nlOi11O_dataout;
|
wire wire_nlOi1ii_dataout;
|
wire wire_nlOi1O_dataout;
|
wire wire_nlOi1il_dataout;
|
wire wire_nlOiiOl_dataout;
|
wire wire_nlOi1iO_dataout;
|
wire wire_nlOiiOO_dataout;
|
wire wire_nlOi1li_dataout;
|
wire wire_nlOil1i_dataout;
|
wire wire_nlOiiO_dataout;
|
|
wire wire_nlOil0i_dataout;
|
|
wire wire_nlOil0l_dataout;
|
|
wire wire_nlOil1O_dataout;
|
|
wire wire_nlOili_dataout;
|
|
wire wire_nlOill_dataout;
|
|
wire wire_nlOilO_dataout;
|
|
wire wire_nlOiOi_dataout;
|
|
wire wire_nlOiOl_dataout;
|
|
wire wire_nlOiOO_dataout;
|
|
wire wire_nlOl00i_dataout;
|
wire wire_nlOl00i_dataout;
|
wire wire_nlOl00l_dataout;
|
wire wire_nlOl00l_dataout;
|
wire wire_nlOl00O_dataout;
|
wire wire_nlOl00O_dataout;
|
wire wire_nlOl01i_dataout;
|
wire wire_nlOl01i_dataout;
|
wire wire_nlOl01l_dataout;
|
wire wire_nlOl01l_dataout;
|
| Line 2154... |
Line 2153... |
wire wire_nlOl0lO_dataout;
|
wire wire_nlOl0lO_dataout;
|
wire wire_nlOl0O_dataout;
|
wire wire_nlOl0O_dataout;
|
wire wire_nlOl0Oi_dataout;
|
wire wire_nlOl0Oi_dataout;
|
wire wire_nlOl0Ol_dataout;
|
wire wire_nlOl0Ol_dataout;
|
wire wire_nlOl0OO_dataout;
|
wire wire_nlOl0OO_dataout;
|
|
wire wire_nlOl10l_dataout;
|
|
wire wire_nlOl10O_dataout;
|
wire wire_nlOl1i_dataout;
|
wire wire_nlOl1i_dataout;
|
|
wire wire_nlOl1ii_dataout;
|
|
wire wire_nlOl1il_dataout;
|
wire wire_nlOl1iO_dataout;
|
wire wire_nlOl1iO_dataout;
|
wire wire_nlOl1l_dataout;
|
wire wire_nlOl1l_dataout;
|
wire wire_nlOl1li_dataout;
|
wire wire_nlOl1li_dataout;
|
wire wire_nlOl1ll_dataout;
|
wire wire_nlOl1ll_dataout;
|
wire wire_nlOl1lO_dataout;
|
wire wire_nlOl1lO_dataout;
|
| Line 2173... |
Line 2176... |
wire wire_nlOli1l_dataout;
|
wire wire_nlOli1l_dataout;
|
wire wire_nlOli1O_dataout;
|
wire wire_nlOli1O_dataout;
|
wire wire_nlOlii_dataout;
|
wire wire_nlOlii_dataout;
|
wire wire_nlOliii_dataout;
|
wire wire_nlOliii_dataout;
|
wire wire_nlOliil_dataout;
|
wire wire_nlOliil_dataout;
|
wire wire_nlOliiO_dataout;
|
wire wire_nlOlil_dataout;
|
wire wire_nlOlili_dataout;
|
|
wire wire_nlOlill_dataout;
|
|
wire wire_nlOlilO_dataout;
|
wire wire_nlOlilO_dataout;
|
wire wire_nlOll1i_dataout;
|
wire wire_nlOliO_dataout;
|
wire wire_nlOll1l_dataout;
|
wire wire_nlOliOi_dataout;
|
|
wire wire_nlOlli_dataout;
|
|
wire wire_nlOllii_dataout;
|
|
wire wire_nlOllil_dataout;
|
|
wire wire_nlOlliO_dataout;
|
|
wire wire_nlOlll_dataout;
|
|
wire wire_nlOllli_dataout;
|
wire wire_nlOllll_dataout;
|
wire wire_nlOllll_dataout;
|
wire wire_nlOlllO_dataout;
|
wire wire_nlOlllO_dataout;
|
|
wire wire_nlOllO_dataout;
|
wire wire_nlOllOi_dataout;
|
wire wire_nlOllOi_dataout;
|
wire wire_nlOllOl_dataout;
|
wire wire_nlOllOl_dataout;
|
wire wire_nlOllOO_dataout;
|
wire wire_nlOllOO_dataout;
|
wire wire_nlOlO0i_dataout;
|
wire wire_nlOlO0i_dataout;
|
wire wire_nlOlO0l_dataout;
|
wire wire_nlOlO0l_dataout;
|
wire wire_nlOlO0O_dataout;
|
wire wire_nlOlO0O_dataout;
|
wire wire_nlOlO1i_dataout;
|
wire wire_nlOlO1i_dataout;
|
wire wire_nlOlO1l_dataout;
|
wire wire_nlOlO1l_dataout;
|
wire wire_nlOlO1O_dataout;
|
wire wire_nlOlO1O_dataout;
|
|
wire wire_nlOlOi_dataout;
|
wire wire_nlOlOii_dataout;
|
wire wire_nlOlOii_dataout;
|
wire wire_nlOlOil_dataout;
|
wire wire_nlOlOil_dataout;
|
wire wire_nlOlOiO_dataout;
|
wire wire_nlOlOiO_dataout;
|
|
wire wire_nlOlOl_dataout;
|
wire wire_nlOlOli_dataout;
|
wire wire_nlOlOli_dataout;
|
wire wire_nlOlOll_dataout;
|
|
wire wire_nlOlOlO_dataout;
|
|
wire wire_nlOlOOi_dataout;
|
wire wire_nlOlOOi_dataout;
|
wire wire_nlOlOOl_dataout;
|
wire wire_nlOO00l_dataout;
|
|
wire wire_nlOO00O_dataout;
|
|
wire wire_nlOO0ii_dataout;
|
|
wire wire_nlOO0il_dataout;
|
wire wire_nlOO0iO_dataout;
|
wire wire_nlOO0iO_dataout;
|
wire wire_nlOO0li_dataout;
|
wire wire_nlOO0li_dataout;
|
wire wire_nlOO0ll_dataout;
|
wire wire_nlOO0ll_dataout;
|
wire wire_nlOO0lO_dataout;
|
wire wire_nlOO0lO_dataout;
|
wire wire_nlOO0Oi_dataout;
|
wire wire_nlOO0Oi_dataout;
|
wire wire_nlOO0Ol_dataout;
|
wire wire_nlOO0Ol_dataout;
|
wire wire_nlOO0OO_dataout;
|
wire wire_nlOO0OO_dataout;
|
wire wire_nlOO11l_dataout;
|
wire wire_nlOO11O_dataout;
|
wire wire_nlOO1ii_dataout;
|
|
wire wire_nlOOi0i_dataout;
|
wire wire_nlOOi0i_dataout;
|
wire wire_nlOOi0l_dataout;
|
wire wire_nlOOi0l_dataout;
|
wire wire_nlOOi0O_dataout;
|
wire wire_nlOOi0O_dataout;
|
wire wire_nlOOi1i_dataout;
|
wire wire_nlOOi1i_dataout;
|
wire wire_nlOOi1l_dataout;
|
wire wire_nlOOi1l_dataout;
|
wire wire_nlOOi1O_dataout;
|
wire wire_nlOOi1O_dataout;
|
wire wire_nlOOiii_dataout;
|
wire wire_nlOOiii_dataout;
|
wire wire_nlOOiil_dataout;
|
wire wire_nlOOiil_dataout;
|
wire wire_nlOOiiO_dataout;
|
wire wire_nlOOiiO_dataout;
|
wire wire_nlOOil_dataout;
|
|
wire wire_nlOOili_dataout;
|
wire wire_nlOOili_dataout;
|
wire wire_nlOOill_dataout;
|
wire wire_nlOOill_dataout;
|
wire wire_nlOOilO_dataout;
|
wire wire_nlOOilO_dataout;
|
wire wire_nlOOiO_dataout;
|
|
wire wire_nlOOiOi_dataout;
|
wire wire_nlOOiOi_dataout;
|
wire wire_nlOOiOl_dataout;
|
wire wire_nlOOiOl_dataout;
|
wire wire_nlOOiOO_dataout;
|
wire wire_nlOOiOO_dataout;
|
wire wire_nlOOl0i_dataout;
|
wire wire_nlOOl0i_dataout;
|
wire wire_nlOOl0l_dataout;
|
wire wire_nlOOl0l_dataout;
|
| Line 2238... |
Line 2246... |
wire wire_nlOOlli_dataout;
|
wire wire_nlOOlli_dataout;
|
wire wire_nlOOlll_dataout;
|
wire wire_nlOOlll_dataout;
|
wire wire_nlOOllO_dataout;
|
wire wire_nlOOllO_dataout;
|
wire wire_nlOOlOi_dataout;
|
wire wire_nlOOlOi_dataout;
|
wire wire_nlOOlOl_dataout;
|
wire wire_nlOOlOl_dataout;
|
wire wire_nlOOlOO_dataout;
|
|
wire wire_nlOOO0l_dataout;
|
|
wire wire_nlOOO0O_dataout;
|
wire wire_nlOOO0O_dataout;
|
wire wire_nlOOO1i_dataout;
|
wire wire_nlOOO1i_dataout;
|
wire wire_nlOOO1l_dataout;
|
wire wire_nlOOO1l_dataout;
|
wire wire_nlOOO1O_dataout;
|
wire wire_nlOOOii_dataout;
|
wire wire_nlOOOli_dataout;
|
wire wire_nlOOOl_dataout;
|
wire wire_nlOOOll_dataout;
|
wire wire_nlOOOO_dataout;
|
|
wire wire_nlOOOOl_dataout;
|
wire [6:0] wire_n00i1l_o;
|
wire [6:0] wire_n00i1l_o;
|
|
wire [3:0] wire_n00ii_o;
|
wire [1:0] wire_n00O0i_o;
|
wire [1:0] wire_n00O0i_o;
|
wire [3:0] wire_n01il_o;
|
wire [3:0] wire_n01li_o;
|
wire [3:0] wire_n0i0ii_o;
|
wire [3:0] wire_n0i0ii_o;
|
wire [3:0] wire_n0il1i_o;
|
wire [3:0] wire_n0il1i_o;
|
wire [4:0] wire_n0ilOl_o;
|
wire [4:0] wire_n0ilOl_o;
|
wire [4:0] wire_n0iO0l_o;
|
wire [4:0] wire_n0iO0l_o;
|
wire [2:0] wire_n11ll_o;
|
wire [2:0] wire_n100O_o;
|
wire [2:0] wire_n1iiO_o;
|
wire [0:0] wire_n111i_o;
|
wire [4:0] wire_n1lll_o;
|
wire [2:0] wire_n1l0i_o;
|
wire [3:0] wire_n1Oll_o;
|
wire [4:0] wire_n1OiO_o;
|
wire [3:0] wire_ni01lO_o;
|
wire [3:0] wire_ni01lO_o;
|
wire [3:0] wire_ni0i0l_o;
|
wire [3:0] wire_ni0i0l_o;
|
wire [4:0] wire_ni0l1O_o;
|
wire [4:0] wire_ni0l1O_o;
|
wire [4:0] wire_ni0lil_o;
|
wire [4:0] wire_ni0lil_o;
|
wire [6:0] wire_niiO0i_o;
|
wire [6:0] wire_niiO0i_o;
|
wire [5:0] wire_nliiOOO_o;
|
wire [5:0] wire_nliiOii_o;
|
wire [2:0] wire_nlil10i_o;
|
wire [2:0] wire_nliiOll_o;
|
wire [5:0] wire_nlili1O_o;
|
wire [5:0] wire_nlil0li_o;
|
wire [2:0] wire_nliliii_o;
|
wire [2:0] wire_nlil0Ol_o;
|
wire [20:0] wire_nll01ll_o;
|
wire [2:0] wire_nll00OO_o;
|
wire [2:0] wire_nll0iii_o;
|
wire [20:0] wire_nll010i_o;
|
wire [7:0] wire_nlllOl_o;
|
wire [7:0] wire_nllO0O_o;
|
wire [20:0] wire_nllO1iO_o;
|
wire [20:0] wire_nllO10l_o;
|
wire [1:0] wire_nllOlii_o;
|
wire [1:0] wire_nllOl1O_o;
|
wire [1:0] wire_nllOO1l_o;
|
wire [1:0] wire_nllOlOi_o;
|
wire [0:0] wire_nlOOli_o;
|
wire [1:0] wire_n010Oi_o;
|
wire [1:0] wire_n01iil_o;
|
|
wire [1:0] wire_n0lilO_o;
|
wire [1:0] wire_n0lilO_o;
|
wire [1:0] wire_niO0lO_o;
|
wire [1:0] wire_niO0lO_o;
|
wire [1:0] wire_niOi0O_o;
|
wire [1:0] wire_niOi0O_o;
|
wire wire_n00i1O_o;
|
wire wire_n00i1O_o;
|
wire wire_n0i0il_o;
|
wire wire_n0i0il_o;
|
| Line 2287... |
Line 2294... |
wire wire_ni01Oi_o;
|
wire wire_ni01Oi_o;
|
wire wire_ni0i0O_o;
|
wire wire_ni0i0O_o;
|
wire wire_ni0llO_o;
|
wire wire_ni0llO_o;
|
wire wire_ni0OOl_o;
|
wire wire_ni0OOl_o;
|
wire wire_niiO0l_o;
|
wire wire_niiO0l_o;
|
wire wire_nllill_o;
|
wire wire_nlll1O_o;
|
wire wire_nl100i_o;
|
wire wire_nl100i_o;
|
wire wire_nl100l_o;
|
wire wire_nl100l_o;
|
wire wire_nl100O_o;
|
wire wire_nl100O_o;
|
wire wire_nl101O_o;
|
wire wire_nl101O_o;
|
wire wire_nl10ii_o;
|
wire wire_nl10ii_o;
|
| Line 2308... |
Line 2315... |
wire wire_nl1i1O_o;
|
wire wire_nl1i1O_o;
|
wire wire_n00ill_o;
|
wire wire_n00ill_o;
|
wire wire_n00iOi_o;
|
wire wire_n00iOi_o;
|
wire wire_n00iOO_o;
|
wire wire_n00iOO_o;
|
wire wire_n00l1l_o;
|
wire wire_n00l1l_o;
|
wire wire_n1100l_o;
|
|
wire wire_n1101i_o;
|
wire wire_n1101i_o;
|
wire wire_n1101O_o;
|
|
wire wire_n1110i_o;
|
wire wire_n1110i_o;
|
wire wire_n1110l_o;
|
|
wire wire_n1111i_o;
|
wire wire_n1111i_o;
|
wire wire_n111il_o;
|
wire wire_n111il_o;
|
|
wire wire_n111li_o;
|
wire wire_n111lO_o;
|
wire wire_n111lO_o;
|
wire wire_n111Ol_o;
|
wire wire_n111Ol_o;
|
wire wire_n1Oili_o;
|
wire wire_n1Oi0O_o;
|
wire wire_n1OiOi_o;
|
wire wire_n1OiiO_o;
|
wire wire_n1OiOO_o;
|
wire wire_n1Oill_o;
|
wire wire_n1Ol0l_o;
|
wire wire_n1OiOl_o;
|
wire wire_n1Ol1O_o;
|
wire wire_n1Ol1i_o;
|
wire wire_ni101l_o;
|
wire wire_ni101l_o;
|
wire wire_ni11lO_o;
|
wire wire_ni11lO_o;
|
wire wire_ni11Oi_o;
|
wire wire_ni11Oi_o;
|
wire wire_ni11OO_o;
|
wire wire_ni11OO_o;
|
wire wire_niiOOi_o;
|
wire wire_niiOOi_o;
|
wire wire_niiOOO_o;
|
wire wire_niiOOO_o;
|
wire wire_nil10i_o;
|
wire wire_nil10i_o;
|
wire wire_nil11l_o;
|
wire wire_nil11l_o;
|
wire wire_nlO0lO_o;
|
wire wire_nlO0lli_o;
|
|
wire wire_nlO0llO_o;
|
wire wire_nlO0lOl_o;
|
wire wire_nlO0lOl_o;
|
wire wire_nlO0O0l_o;
|
wire wire_nlO0O0l_o;
|
wire wire_nlO0O1i_o;
|
wire wire_nlO0O1i_o;
|
wire wire_nlO0O1O_o;
|
wire wire_nlO0O1O_o;
|
wire wire_nlO0Oii_o;
|
wire wire_nlO0Oii_o;
|
wire wire_nlO0OiO_o;
|
wire wire_nlO0OiO_o;
|
wire wire_nlO0Ol_o;
|
wire wire_nlOi0i_o;
|
wire wire_nlO0Oll_o;
|
wire wire_nlOi0O_o;
|
wire wire_nlO0OOi_o;
|
wire wire_nlOiil_o;
|
wire wire_nlOi0l_o;
|
wire wire_nlOili_o;
|
wire wire_nlOi1i_o;
|
wire wire_nlOilO_o;
|
wire wire_nlOi1O_o;
|
wire wire_nlOOO0i_o;
|
wire wire_nlOOOil_o;
|
wire wire_nlOOOil_o;
|
|
wire wire_nlOOOli_o;
|
wire wire_nlOOOlO_o;
|
wire wire_nlOOOlO_o;
|
wire wire_nlOOOOl_o;
|
wire wire_nlOOOOO_o;
|
wire nl0O00i;
|
wire nl0O00i;
|
wire nl0O00l;
|
wire nl0O00l;
|
wire nl0O00O;
|
wire nl0O00O;
|
wire nl0O01i;
|
wire nl0O01i;
|
wire nl0O01l;
|
wire nl0O01l;
|
| Line 2361... |
Line 2368... |
wire nl0O0ll;
|
wire nl0O0ll;
|
wire nl0O0lO;
|
wire nl0O0lO;
|
wire nl0O0Oi;
|
wire nl0O0Oi;
|
wire nl0O0Ol;
|
wire nl0O0Ol;
|
wire nl0O0OO;
|
wire nl0O0OO;
|
|
wire nl0O10i;
|
|
wire nl0O10l;
|
|
wire nl0O10O;
|
|
wire nl0O11O;
|
|
wire nl0O1ii;
|
|
wire nl0O1il;
|
|
wire nl0O1iO;
|
|
wire nl0O1li;
|
|
wire nl0O1ll;
|
|
wire nl0O1lO;
|
|
wire nl0O1Oi;
|
|
wire nl0O1Ol;
|
wire nl0O1OO;
|
wire nl0O1OO;
|
wire nl0Oi0i;
|
wire nl0Oi0i;
|
wire nl0Oi0l;
|
wire nl0Oi0l;
|
wire nl0Oi0O;
|
wire nl0Oi0O;
|
wire nl0Oi1i;
|
wire nl0Oi1i;
|
| Line 2407... |
Line 2426... |
wire nl0OOll;
|
wire nl0OOll;
|
wire nl0OOlO;
|
wire nl0OOlO;
|
wire nl0OOOi;
|
wire nl0OOOi;
|
wire nl0OOOl;
|
wire nl0OOOl;
|
wire nl0OOOO;
|
wire nl0OOOO;
|
wire nli000i;
|
|
wire nli000l;
|
wire nli000l;
|
wire nli000O;
|
wire nli000O;
|
wire nli001i;
|
wire nli001i;
|
wire nli001l;
|
wire nli001l;
|
wire nli001O;
|
|
wire nli00ii;
|
wire nli00ii;
|
wire nli00il;
|
wire nli00il;
|
wire nli00iO;
|
wire nli00iO;
|
wire nli00li;
|
wire nli00li;
|
wire nli00ll;
|
wire nli00ll;
|
wire nli00lO;
|
wire nli00lO;
|
wire nli010i;
|
wire nli00Oi;
|
wire nli011l;
|
wire nli00Ol;
|
wire nli011O;
|
wire nli00OO;
|
|
wire nli010l;
|
|
wire nli010O;
|
|
wire nli011i;
|
wire nli01ii;
|
wire nli01ii;
|
wire nli01il;
|
wire nli01il;
|
wire nli01iO;
|
wire nli01iO;
|
|
wire nli01li;
|
|
wire nli01ll;
|
wire nli01lO;
|
wire nli01lO;
|
wire nli01Oi;
|
wire nli01Oi;
|
|
wire nli01Ol;
|
wire nli01OO;
|
wire nli01OO;
|
wire nli0i0i;
|
wire nli0i0i;
|
wire nli0i0l;
|
wire nli0i0l;
|
wire nli0i0O;
|
wire nli0i0O;
|
wire nli0i1i;
|
wire nli0i1i;
|
| Line 2442... |
Line 2465... |
wire nli0ili;
|
wire nli0ili;
|
wire nli0ill;
|
wire nli0ill;
|
wire nli0ilO;
|
wire nli0ilO;
|
wire nli0iOi;
|
wire nli0iOi;
|
wire nli0iOl;
|
wire nli0iOl;
|
wire nli0l0i;
|
wire nli0iOO;
|
wire nli0l0l;
|
|
wire nli0l0O;
|
wire nli0l0O;
|
wire nli0l1i;
|
wire nli0l1i;
|
wire nli0l1l;
|
wire nli0l1l;
|
wire nli0l1O;
|
wire nli0l1O;
|
wire nli0lii;
|
wire nli0lOO;
|
wire nli0lil;
|
|
wire nli0liO;
|
|
wire nli0lli;
|
|
wire nli0lll;
|
|
wire nli0lOl;
|
|
wire nli0O0O;
|
wire nli0O0O;
|
wire nli0OiO;
|
wire nli0O1i;
|
wire nli0OOl;
|
wire nli0Oll;
|
wire nli100i;
|
wire nli100i;
|
wire nli100l;
|
wire nli100l;
|
wire nli100O;
|
wire nli100O;
|
wire nli101i;
|
wire nli101i;
|
wire nli101l;
|
wire nli101l;
|
| Line 2513... |
Line 2530... |
wire nli1lii;
|
wire nli1lii;
|
wire nli1lil;
|
wire nli1lil;
|
wire nli1liO;
|
wire nli1liO;
|
wire nli1lli;
|
wire nli1lli;
|
wire nli1lll;
|
wire nli1lll;
|
wire nli1llO;
|
|
wire nli1lOi;
|
|
wire nli1lOl;
|
wire nli1lOl;
|
wire nli1lOO;
|
wire nli1lOO;
|
wire nli1O0i;
|
wire nli1O0i;
|
wire nli1O0l;
|
wire nli1O0l;
|
wire nli1O0O;
|
|
wire nli1O1i;
|
wire nli1O1i;
|
wire nli1O1l;
|
wire nli1O1l;
|
wire nli1O1O;
|
wire nli1O1O;
|
wire nli1Oii;
|
wire nli1OiO;
|
wire nli1Oil;
|
wire nli1Oli;
|
wire nli1Oll;
|
wire nli1Oll;
|
wire nli1OlO;
|
wire nli1OOO;
|
wire nli1OOi;
|
wire nlii00i;
|
wire nli1OOl;
|
wire nlii0iO;
|
wire nlii00O;
|
wire nlii0li;
|
|
wire nlii0ll;
|
wire nlii0lO;
|
wire nlii0lO;
|
wire nlii0Oi;
|
wire nlii11i;
|
wire nlii11l;
|
wire nlii1il;
|
wire nlii1ii;
|
wire nlii1Oi;
|
wire nlii1Ol;
|
|
wire nliii0i;
|
|
wire nliii0l;
|
|
wire nliii1O;
|
|
|
|
altera_std_synchronizer n1i1ii
|
altera_std_synchronizer n1i10i
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din(nll0iiO),
|
.din(nll0i1l),
|
.dout(wire_n1i1ii_dout),
|
.dout(wire_n1i10i_dout),
|
.reset_n((~ nliii1O)));
|
.reset_n((~ nlii0li)));
|
defparam
|
defparam
|
n1i1ii.depth = 3;
|
n1i10i.depth = 3;
|
altera_std_synchronizer n1i1il
|
altera_std_synchronizer n1i10O
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din(nll00iO),
|
.din(nlilOl),
|
.dout(wire_n1i1il_dout),
|
.dout(wire_n1i10O_dout),
|
.reset_n((~ nliii1O)));
|
.reset_n((~ nlii0li)));
|
defparam
|
defparam
|
n1i1il.depth = 3;
|
n1i10O.depth = 3;
|
altera_std_synchronizer n1i1li
|
altera_std_synchronizer n1i11O
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din(nlilOl),
|
.din(nll001l),
|
.dout(wire_n1i1li_dout),
|
.dout(wire_n1i11O_dout),
|
.reset_n((~ nliii1O)));
|
.reset_n((~ nlii0li)));
|
defparam
|
defparam
|
n1i1li.depth = 3;
|
n1i11O.depth = 3;
|
altera_std_synchronizer n1i1ll
|
altera_std_synchronizer n1i1ii
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din(nliO0l),
|
.din(nliO0l),
|
.dout(wire_n1i1ll_dout),
|
.dout(wire_n1i1ii_dout),
|
.reset_n((~ nliii1O)));
|
.reset_n((~ nlii0li)));
|
defparam
|
defparam
|
n1i1ll.depth = 3;
|
n1i1ii.depth = 3;
|
altera_std_synchronizer nliliOl
|
altera_std_synchronizer nlili0O
|
(
|
(
|
.clk(wire_nl1ii_clkout),
|
.clk(wire_nl0ii_clkout),
|
.din(nliO0l),
|
.din(nliO0l),
|
.dout(wire_nliliOl_dout),
|
.dout(wire_nlili0O_dout),
|
.reset_n((~ nlilill)));
|
.reset_n((~ nlili1O)));
|
defparam
|
defparam
|
nliliOl.depth = 3;
|
nlili0O.depth = 3;
|
altera_std_synchronizer nliliOO
|
altera_std_synchronizer nliliii
|
(
|
(
|
.clk(wire_nl1ii_clkout),
|
.clk(wire_nl0ii_clkout),
|
.din(nliOii),
|
.din(nliOii),
|
.dout(wire_nliliOO_dout),
|
.dout(wire_nliliii_dout),
|
.reset_n((~ nlilill)));
|
.reset_n((~ nlili1O)));
|
defparam
|
defparam
|
nliliOO.depth = 3;
|
nliliii.depth = 3;
|
altera_std_synchronizer nlill1i
|
altera_std_synchronizer nliliil
|
(
|
(
|
.clk(wire_nl1ii_clkout),
|
.clk(wire_nl0ii_clkout),
|
.din(nlilOl),
|
.din(nlilOl),
|
.dout(wire_nlill1i_dout),
|
.dout(wire_nliliil_dout),
|
.reset_n((~ nlilill)));
|
.reset_n((~ nlili1O)));
|
|
defparam
|
|
nliliil.depth = 3;
|
|
altera_std_synchronizer nliliiO
|
|
(
|
|
.clk(wire_nl0ii_clkout),
|
|
.din(nliOil),
|
|
.dout(wire_nliliiO_dout),
|
|
.reset_n((~ nlili1O)));
|
defparam
|
defparam
|
nlill1i.depth = 3;
|
nliliiO.depth = 3;
|
altera_std_synchronizer_bundle n01l0O
|
altera_std_synchronizer_bundle n01ill
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din({nl010i, nl011O}),
|
.din({nl010i, nl011O}),
|
.dout(wire_n01l0O_dout),
|
.dout(wire_n01ill_dout),
|
.reset_n((~ nliii0i)));
|
.reset_n((~ nlii0ll)));
|
defparam
|
defparam
|
n01l0O.depth = 3,
|
n01ill.depth = 3,
|
n01l0O.width = 2;
|
n01ill.width = 2;
|
altera_std_synchronizer_bundle n01lii
|
altera_std_synchronizer_bundle n01ilO
|
(
|
(
|
.clk(wire_nl1ii_clkout),
|
.clk(wire_nl0ii_clkout),
|
.din({nl010i, nl011O}),
|
.din({nl010i, nl011O}),
|
.dout(wire_n01lii_dout),
|
.dout(wire_n01ilO_dout),
|
.reset_n((~ nlilill)));
|
.reset_n((~ nlili1O)));
|
defparam
|
defparam
|
n01lii.depth = 3,
|
n01ilO.depth = 3,
|
n01lii.width = 2;
|
n01ilO.width = 2;
|
altera_std_synchronizer_bundle n1i1iO
|
altera_std_synchronizer_bundle n1i10l
|
(
|
(
|
.clk(wire_nl10l_clkout),
|
.clk(wire_nl00l_clkout),
|
.din({nll0lOl, nll0lOi, nll0llO, nll0lll, nll0lli, nll0liO, nll0lil, nll0lii, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0ili}),
|
.din({nll0lli, nll0liO, nll0lil, nll0lii, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0i0O}),
|
.dout(wire_n1i1iO_dout),
|
.dout(wire_n1i10l_dout),
|
.reset_n((~ nliii1O)));
|
.reset_n((~ nlii0li)));
|
defparam
|
defparam
|
n1i1iO.depth = 3,
|
n1i10l.depth = 3,
|
n1i1iO.width = 16;
|
n1i10l.width = 16;
|
altpll nl11O
|
altpll nl01O
|
(
|
(
|
.activeclock(),
|
.activeclock(),
|
.areset(gxb_pwrdn_in),
|
.areset(gxb_pwrdn_in),
|
.clk(wire_nl11O_clk),
|
.clk(wire_nl01O_clk),
|
.clkbad(),
|
.clkbad(),
|
.clkloss(),
|
.clkloss(),
|
.enable0(),
|
.enable0(),
|
.enable1(),
|
.enable1(),
|
.extclk(),
|
.extclk(),
|
.fbout(),
|
.fbout(),
|
.fref(wire_nl11O_fref),
|
.fref(wire_nl01O_fref),
|
.icdrclk(wire_nl11O_icdrclk),
|
.icdrclk(wire_nl01O_icdrclk),
|
.inclk({1'b0, ref_clk}),
|
.inclk({1'b0, ref_clk}),
|
.locked(wire_nl11O_locked),
|
.locked(wire_nl01O_locked),
|
.phasedone(),
|
.phasedone(),
|
.scandataout(),
|
.scandataout(),
|
.scandone(),
|
.scandone(),
|
.sclkout0(),
|
.sclkout0(),
|
.sclkout1(),
|
.sclkout1(),
|
| Line 2662... |
Line 2681... |
.scandata(),
|
.scandata(),
|
.scanread(),
|
.scanread(),
|
.scanwrite()
|
.scanwrite()
|
);
|
);
|
defparam
|
defparam
|
nl11O.bandwidth = 0,
|
nl01O.bandwidth = 0,
|
nl11O.bandwidth_type = "HIGH",
|
nl01O.bandwidth_type = "HIGH",
|
nl11O.c0_high = 0,
|
nl01O.c0_high = 0,
|
nl11O.c0_initial = 0,
|
nl01O.c0_initial = 0,
|
nl11O.c0_low = 0,
|
nl01O.c0_low = 0,
|
nl11O.c0_mode = "BYPASS",
|
nl01O.c0_mode = "BYPASS",
|
nl11O.c0_ph = 0,
|
nl01O.c0_ph = 0,
|
nl11O.c0_test_source = 5,
|
nl01O.c0_test_source = 5,
|
nl11O.c1_high = 0,
|
nl01O.c1_high = 0,
|
nl11O.c1_initial = 0,
|
nl01O.c1_initial = 0,
|
nl11O.c1_low = 0,
|
nl01O.c1_low = 0,
|
nl11O.c1_mode = "BYPASS",
|
nl01O.c1_mode = "BYPASS",
|
nl11O.c1_ph = 0,
|
nl01O.c1_ph = 0,
|
nl11O.c1_test_source = 5,
|
nl01O.c1_test_source = 5,
|
nl11O.c1_use_casc_in = "OFF",
|
nl01O.c1_use_casc_in = "OFF",
|
nl11O.c2_high = 0,
|
nl01O.c2_high = 0,
|
nl11O.c2_initial = 0,
|
nl01O.c2_initial = 0,
|
nl11O.c2_low = 0,
|
nl01O.c2_low = 0,
|
nl11O.c2_mode = "BYPASS",
|
nl01O.c2_mode = "BYPASS",
|
nl11O.c2_ph = 0,
|
nl01O.c2_ph = 0,
|
nl11O.c2_test_source = 5,
|
nl01O.c2_test_source = 5,
|
nl11O.c2_use_casc_in = "OFF",
|
nl01O.c2_use_casc_in = "OFF",
|
nl11O.c3_high = 0,
|
nl01O.c3_high = 0,
|
nl11O.c3_initial = 0,
|
nl01O.c3_initial = 0,
|
nl11O.c3_low = 0,
|
nl01O.c3_low = 0,
|
nl11O.c3_mode = "BYPASS",
|
nl01O.c3_mode = "BYPASS",
|
nl11O.c3_ph = 0,
|
nl01O.c3_ph = 0,
|
nl11O.c3_test_source = 5,
|
nl01O.c3_test_source = 5,
|
nl11O.c3_use_casc_in = "OFF",
|
nl01O.c3_use_casc_in = "OFF",
|
nl11O.c4_high = 0,
|
nl01O.c4_high = 0,
|
nl11O.c4_initial = 0,
|
nl01O.c4_initial = 0,
|
nl11O.c4_low = 0,
|
nl01O.c4_low = 0,
|
nl11O.c4_mode = "BYPASS",
|
nl01O.c4_mode = "BYPASS",
|
nl11O.c4_ph = 0,
|
nl01O.c4_ph = 0,
|
nl11O.c4_test_source = 5,
|
nl01O.c4_test_source = 5,
|
nl11O.c4_use_casc_in = "OFF",
|
nl01O.c4_use_casc_in = "OFF",
|
nl11O.c5_high = 0,
|
nl01O.c5_high = 0,
|
nl11O.c5_initial = 0,
|
nl01O.c5_initial = 0,
|
nl11O.c5_low = 0,
|
nl01O.c5_low = 0,
|
nl11O.c5_mode = "BYPASS",
|
nl01O.c5_mode = "BYPASS",
|
nl11O.c5_ph = 0,
|
nl01O.c5_ph = 0,
|
nl11O.c5_test_source = 5,
|
nl01O.c5_test_source = 5,
|
nl11O.c5_use_casc_in = "OFF",
|
nl01O.c5_use_casc_in = "OFF",
|
nl11O.c6_high = 0,
|
nl01O.c6_high = 0,
|
nl11O.c6_initial = 0,
|
nl01O.c6_initial = 0,
|
nl11O.c6_low = 0,
|
nl01O.c6_low = 0,
|
nl11O.c6_mode = "BYPASS",
|
nl01O.c6_mode = "BYPASS",
|
nl11O.c6_ph = 0,
|
nl01O.c6_ph = 0,
|
nl11O.c6_test_source = 5,
|
nl01O.c6_test_source = 5,
|
nl11O.c6_use_casc_in = "OFF",
|
nl01O.c6_use_casc_in = "OFF",
|
nl11O.c7_high = 0,
|
nl01O.c7_high = 0,
|
nl11O.c7_initial = 0,
|
nl01O.c7_initial = 0,
|
nl11O.c7_low = 0,
|
nl01O.c7_low = 0,
|
nl11O.c7_mode = "BYPASS",
|
nl01O.c7_mode = "BYPASS",
|
nl11O.c7_ph = 0,
|
nl01O.c7_ph = 0,
|
nl11O.c7_test_source = 5,
|
nl01O.c7_test_source = 5,
|
nl11O.c7_use_casc_in = "OFF",
|
nl01O.c7_use_casc_in = "OFF",
|
nl11O.c8_high = 0,
|
nl01O.c8_high = 0,
|
nl11O.c8_initial = 0,
|
nl01O.c8_initial = 0,
|
nl11O.c8_low = 0,
|
nl01O.c8_low = 0,
|
nl11O.c8_mode = "BYPASS",
|
nl01O.c8_mode = "BYPASS",
|
nl11O.c8_ph = 0,
|
nl01O.c8_ph = 0,
|
nl11O.c8_test_source = 5,
|
nl01O.c8_test_source = 5,
|
nl11O.c8_use_casc_in = "OFF",
|
nl01O.c8_use_casc_in = "OFF",
|
nl11O.c9_high = 0,
|
nl01O.c9_high = 0,
|
nl11O.c9_initial = 0,
|
nl01O.c9_initial = 0,
|
nl11O.c9_low = 0,
|
nl01O.c9_low = 0,
|
nl11O.c9_mode = "BYPASS",
|
nl01O.c9_mode = "BYPASS",
|
nl11O.c9_ph = 0,
|
nl01O.c9_ph = 0,
|
nl11O.c9_test_source = 5,
|
nl01O.c9_test_source = 5,
|
nl11O.c9_use_casc_in = "OFF",
|
nl01O.c9_use_casc_in = "OFF",
|
nl11O.charge_pump_current = 2,
|
nl01O.charge_pump_current = 2,
|
nl11O.charge_pump_current_bits = 9999,
|
nl01O.charge_pump_current_bits = 9999,
|
nl11O.clk0_counter = "G0",
|
nl01O.clk0_counter = "G0",
|
nl11O.clk0_divide_by = 1,
|
nl01O.clk0_divide_by = 1,
|
nl11O.clk0_duty_cycle = 50,
|
nl01O.clk0_duty_cycle = 50,
|
nl11O.clk0_multiply_by = 5,
|
nl01O.clk0_multiply_by = 5,
|
nl11O.clk0_output_frequency = 0,
|
nl01O.clk0_output_frequency = 0,
|
nl11O.clk0_phase_shift = "0",
|
nl01O.clk0_phase_shift = "0",
|
nl11O.clk0_time_delay = "0",
|
nl01O.clk0_time_delay = "0",
|
nl11O.clk0_use_even_counter_mode = "OFF",
|
nl01O.clk0_use_even_counter_mode = "OFF",
|
nl11O.clk0_use_even_counter_value = "OFF",
|
nl01O.clk0_use_even_counter_value = "OFF",
|
nl11O.clk1_counter = "G0",
|
nl01O.clk1_counter = "G0",
|
nl11O.clk1_divide_by = 5,
|
nl01O.clk1_divide_by = 5,
|
nl11O.clk1_duty_cycle = 50,
|
nl01O.clk1_duty_cycle = 50,
|
nl11O.clk1_multiply_by = 5,
|
nl01O.clk1_multiply_by = 5,
|
nl11O.clk1_output_frequency = 0,
|
nl01O.clk1_output_frequency = 0,
|
nl11O.clk1_phase_shift = "0",
|
nl01O.clk1_phase_shift = "0",
|
nl11O.clk1_time_delay = "0",
|
nl01O.clk1_time_delay = "0",
|
nl11O.clk1_use_even_counter_mode = "OFF",
|
nl01O.clk1_use_even_counter_mode = "OFF",
|
nl11O.clk1_use_even_counter_value = "OFF",
|
nl01O.clk1_use_even_counter_value = "OFF",
|
nl11O.clk2_counter = "G0",
|
nl01O.clk2_counter = "G0",
|
nl11O.clk2_divide_by = 5,
|
nl01O.clk2_divide_by = 5,
|
nl11O.clk2_duty_cycle = 20,
|
nl01O.clk2_duty_cycle = 20,
|
nl11O.clk2_multiply_by = 5,
|
nl01O.clk2_multiply_by = 5,
|
nl11O.clk2_output_frequency = 0,
|
nl01O.clk2_output_frequency = 0,
|
nl11O.clk2_phase_shift = "0",
|
nl01O.clk2_phase_shift = "0",
|
nl11O.clk2_time_delay = "0",
|
nl01O.clk2_time_delay = "0",
|
nl11O.clk2_use_even_counter_mode = "OFF",
|
nl01O.clk2_use_even_counter_mode = "OFF",
|
nl11O.clk2_use_even_counter_value = "OFF",
|
nl01O.clk2_use_even_counter_value = "OFF",
|
nl11O.clk3_counter = "G0",
|
nl01O.clk3_counter = "G0",
|
nl11O.clk3_divide_by = 1,
|
nl01O.clk3_divide_by = 1,
|
nl11O.clk3_duty_cycle = 50,
|
nl01O.clk3_duty_cycle = 50,
|
nl11O.clk3_multiply_by = 1,
|
nl01O.clk3_multiply_by = 1,
|
nl11O.clk3_phase_shift = "0",
|
nl01O.clk3_phase_shift = "0",
|
nl11O.clk3_time_delay = "0",
|
nl01O.clk3_time_delay = "0",
|
nl11O.clk3_use_even_counter_mode = "OFF",
|
nl01O.clk3_use_even_counter_mode = "OFF",
|
nl11O.clk3_use_even_counter_value = "OFF",
|
nl01O.clk3_use_even_counter_value = "OFF",
|
nl11O.clk4_counter = "G0",
|
nl01O.clk4_counter = "G0",
|
nl11O.clk4_divide_by = 1,
|
nl01O.clk4_divide_by = 1,
|
nl11O.clk4_duty_cycle = 50,
|
nl01O.clk4_duty_cycle = 50,
|
nl11O.clk4_multiply_by = 1,
|
nl01O.clk4_multiply_by = 1,
|
nl11O.clk4_phase_shift = "0",
|
nl01O.clk4_phase_shift = "0",
|
nl11O.clk4_time_delay = "0",
|
nl01O.clk4_time_delay = "0",
|
nl11O.clk4_use_even_counter_mode = "OFF",
|
nl01O.clk4_use_even_counter_mode = "OFF",
|
nl11O.clk4_use_even_counter_value = "OFF",
|
nl01O.clk4_use_even_counter_value = "OFF",
|
nl11O.clk5_counter = "G0",
|
nl01O.clk5_counter = "G0",
|
nl11O.clk5_divide_by = 1,
|
nl01O.clk5_divide_by = 1,
|
nl11O.clk5_duty_cycle = 50,
|
nl01O.clk5_duty_cycle = 50,
|
nl11O.clk5_multiply_by = 1,
|
nl01O.clk5_multiply_by = 1,
|
nl11O.clk5_phase_shift = "0",
|
nl01O.clk5_phase_shift = "0",
|
nl11O.clk5_time_delay = "0",
|
nl01O.clk5_time_delay = "0",
|
nl11O.clk5_use_even_counter_mode = "OFF",
|
nl01O.clk5_use_even_counter_mode = "OFF",
|
nl11O.clk5_use_even_counter_value = "OFF",
|
nl01O.clk5_use_even_counter_value = "OFF",
|
nl11O.clk6_counter = "E0",
|
nl01O.clk6_counter = "E0",
|
nl11O.clk6_divide_by = 0,
|
nl01O.clk6_divide_by = 0,
|
nl11O.clk6_duty_cycle = 50,
|
nl01O.clk6_duty_cycle = 50,
|
nl11O.clk6_multiply_by = 0,
|
nl01O.clk6_multiply_by = 0,
|
nl11O.clk6_phase_shift = "0",
|
nl01O.clk6_phase_shift = "0",
|
nl11O.clk6_use_even_counter_mode = "OFF",
|
nl01O.clk6_use_even_counter_mode = "OFF",
|
nl11O.clk6_use_even_counter_value = "OFF",
|
nl01O.clk6_use_even_counter_value = "OFF",
|
nl11O.clk7_counter = "E1",
|
nl01O.clk7_counter = "E1",
|
nl11O.clk7_divide_by = 0,
|
nl01O.clk7_divide_by = 0,
|
nl11O.clk7_duty_cycle = 50,
|
nl01O.clk7_duty_cycle = 50,
|
nl11O.clk7_multiply_by = 0,
|
nl01O.clk7_multiply_by = 0,
|
nl11O.clk7_phase_shift = "0",
|
nl01O.clk7_phase_shift = "0",
|
nl11O.clk7_use_even_counter_mode = "OFF",
|
nl01O.clk7_use_even_counter_mode = "OFF",
|
nl11O.clk7_use_even_counter_value = "OFF",
|
nl01O.clk7_use_even_counter_value = "OFF",
|
nl11O.clk8_counter = "E2",
|
nl01O.clk8_counter = "E2",
|
nl11O.clk8_divide_by = 0,
|
nl01O.clk8_divide_by = 0,
|
nl11O.clk8_duty_cycle = 50,
|
nl01O.clk8_duty_cycle = 50,
|
nl11O.clk8_multiply_by = 0,
|
nl01O.clk8_multiply_by = 0,
|
nl11O.clk8_phase_shift = "0",
|
nl01O.clk8_phase_shift = "0",
|
nl11O.clk8_use_even_counter_mode = "OFF",
|
nl01O.clk8_use_even_counter_mode = "OFF",
|
nl11O.clk8_use_even_counter_value = "OFF",
|
nl01O.clk8_use_even_counter_value = "OFF",
|
nl11O.clk9_counter = "E3",
|
nl01O.clk9_counter = "E3",
|
nl11O.clk9_divide_by = 0,
|
nl01O.clk9_divide_by = 0,
|
nl11O.clk9_duty_cycle = 50,
|
nl01O.clk9_duty_cycle = 50,
|
nl11O.clk9_multiply_by = 0,
|
nl01O.clk9_multiply_by = 0,
|
nl11O.clk9_phase_shift = "0",
|
nl01O.clk9_phase_shift = "0",
|
nl11O.clk9_use_even_counter_mode = "OFF",
|
nl01O.clk9_use_even_counter_mode = "OFF",
|
nl11O.clk9_use_even_counter_value = "OFF",
|
nl01O.clk9_use_even_counter_value = "OFF",
|
nl11O.compensate_clock = "CLK0",
|
nl01O.compensate_clock = "CLK0",
|
nl11O.down_spread = "0",
|
nl01O.down_spread = "0",
|
nl11O.dpa_divide_by = 1,
|
nl01O.dpa_divide_by = 1,
|
nl11O.dpa_divider = 0,
|
nl01O.dpa_divider = 0,
|
nl11O.dpa_multiply_by = 5,
|
nl01O.dpa_multiply_by = 5,
|
nl11O.e0_high = 1,
|
nl01O.e0_high = 1,
|
nl11O.e0_initial = 1,
|
nl01O.e0_initial = 1,
|
nl11O.e0_low = 1,
|
nl01O.e0_low = 1,
|
nl11O.e0_mode = "BYPASS",
|
nl01O.e0_mode = "BYPASS",
|
nl11O.e0_ph = 0,
|
nl01O.e0_ph = 0,
|
nl11O.e0_time_delay = 0,
|
nl01O.e0_time_delay = 0,
|
nl11O.e1_high = 1,
|
nl01O.e1_high = 1,
|
nl11O.e1_initial = 1,
|
nl01O.e1_initial = 1,
|
nl11O.e1_low = 1,
|
nl01O.e1_low = 1,
|
nl11O.e1_mode = "BYPASS",
|
nl01O.e1_mode = "BYPASS",
|
nl11O.e1_ph = 0,
|
nl01O.e1_ph = 0,
|
nl11O.e1_time_delay = 0,
|
nl01O.e1_time_delay = 0,
|
nl11O.e2_high = 1,
|
nl01O.e2_high = 1,
|
nl11O.e2_initial = 1,
|
nl01O.e2_initial = 1,
|
nl11O.e2_low = 1,
|
nl01O.e2_low = 1,
|
nl11O.e2_mode = "BYPASS",
|
nl01O.e2_mode = "BYPASS",
|
nl11O.e2_ph = 0,
|
nl01O.e2_ph = 0,
|
nl11O.e2_time_delay = 0,
|
nl01O.e2_time_delay = 0,
|
nl11O.e3_high = 1,
|
nl01O.e3_high = 1,
|
nl11O.e3_initial = 1,
|
nl01O.e3_initial = 1,
|
nl11O.e3_low = 1,
|
nl01O.e3_low = 1,
|
nl11O.e3_mode = "BYPASS",
|
nl01O.e3_mode = "BYPASS",
|
nl11O.e3_ph = 0,
|
nl01O.e3_ph = 0,
|
nl11O.e3_time_delay = 0,
|
nl01O.e3_time_delay = 0,
|
nl11O.enable0_counter = "L0",
|
nl01O.enable0_counter = "L0",
|
nl11O.enable1_counter = "L0",
|
nl01O.enable1_counter = "L0",
|
nl11O.enable_switch_over_counter = "OFF",
|
nl01O.enable_switch_over_counter = "OFF",
|
nl11O.extclk0_counter = "E0",
|
nl01O.extclk0_counter = "E0",
|
nl11O.extclk0_divide_by = 1,
|
nl01O.extclk0_divide_by = 1,
|
nl11O.extclk0_duty_cycle = 50,
|
nl01O.extclk0_duty_cycle = 50,
|
nl11O.extclk0_multiply_by = 1,
|
nl01O.extclk0_multiply_by = 1,
|
nl11O.extclk0_phase_shift = "0",
|
nl01O.extclk0_phase_shift = "0",
|
nl11O.extclk0_time_delay = "0",
|
nl01O.extclk0_time_delay = "0",
|
nl11O.extclk1_counter = "E1",
|
nl01O.extclk1_counter = "E1",
|
nl11O.extclk1_divide_by = 1,
|
nl01O.extclk1_divide_by = 1,
|
nl11O.extclk1_duty_cycle = 50,
|
nl01O.extclk1_duty_cycle = 50,
|
nl11O.extclk1_multiply_by = 1,
|
nl01O.extclk1_multiply_by = 1,
|
nl11O.extclk1_phase_shift = "0",
|
nl01O.extclk1_phase_shift = "0",
|
nl11O.extclk1_time_delay = "0",
|
nl01O.extclk1_time_delay = "0",
|
nl11O.extclk2_counter = "E2",
|
nl01O.extclk2_counter = "E2",
|
nl11O.extclk2_divide_by = 1,
|
nl01O.extclk2_divide_by = 1,
|
nl11O.extclk2_duty_cycle = 50,
|
nl01O.extclk2_duty_cycle = 50,
|
nl11O.extclk2_multiply_by = 1,
|
nl01O.extclk2_multiply_by = 1,
|
nl11O.extclk2_phase_shift = "0",
|
nl01O.extclk2_phase_shift = "0",
|
nl11O.extclk2_time_delay = "0",
|
nl01O.extclk2_time_delay = "0",
|
nl11O.extclk3_counter = "E3",
|
nl01O.extclk3_counter = "E3",
|
nl11O.extclk3_divide_by = 1,
|
nl01O.extclk3_divide_by = 1,
|
nl11O.extclk3_duty_cycle = 50,
|
nl01O.extclk3_duty_cycle = 50,
|
nl11O.extclk3_multiply_by = 1,
|
nl01O.extclk3_multiply_by = 1,
|
nl11O.extclk3_phase_shift = "0",
|
nl01O.extclk3_phase_shift = "0",
|
nl11O.extclk3_time_delay = "0",
|
nl01O.extclk3_time_delay = "0",
|
nl11O.feedback_source = "EXTCLK0",
|
nl01O.feedback_source = "EXTCLK0",
|
nl11O.g0_high = 1,
|
nl01O.g0_high = 1,
|
nl11O.g0_initial = 1,
|
nl01O.g0_initial = 1,
|
nl11O.g0_low = 1,
|
nl01O.g0_low = 1,
|
nl11O.g0_mode = "BYPASS",
|
nl01O.g0_mode = "BYPASS",
|
nl11O.g0_ph = 0,
|
nl01O.g0_ph = 0,
|
nl11O.g0_time_delay = 0,
|
nl01O.g0_time_delay = 0,
|
nl11O.g1_high = 1,
|
nl01O.g1_high = 1,
|
nl11O.g1_initial = 1,
|
nl01O.g1_initial = 1,
|
nl11O.g1_low = 1,
|
nl01O.g1_low = 1,
|
nl11O.g1_mode = "BYPASS",
|
nl01O.g1_mode = "BYPASS",
|
nl11O.g1_ph = 0,
|
nl01O.g1_ph = 0,
|
nl11O.g1_time_delay = 0,
|
nl01O.g1_time_delay = 0,
|
nl11O.g2_high = 1,
|
nl01O.g2_high = 1,
|
nl11O.g2_initial = 1,
|
nl01O.g2_initial = 1,
|
nl11O.g2_low = 1,
|
nl01O.g2_low = 1,
|
nl11O.g2_mode = "BYPASS",
|
nl01O.g2_mode = "BYPASS",
|
nl11O.g2_ph = 0,
|
nl01O.g2_ph = 0,
|
nl11O.g2_time_delay = 0,
|
nl01O.g2_time_delay = 0,
|
nl11O.g3_high = 1,
|
nl01O.g3_high = 1,
|
nl11O.g3_initial = 1,
|
nl01O.g3_initial = 1,
|
nl11O.g3_low = 1,
|
nl01O.g3_low = 1,
|
nl11O.g3_mode = "BYPASS",
|
nl01O.g3_mode = "BYPASS",
|
nl11O.g3_ph = 0,
|
nl01O.g3_ph = 0,
|
nl11O.g3_time_delay = 0,
|
nl01O.g3_time_delay = 0,
|
nl11O.gate_lock_counter = 0,
|
nl01O.gate_lock_counter = 0,
|
nl11O.gate_lock_signal = "NO",
|
nl01O.gate_lock_signal = "NO",
|
nl11O.inclk0_input_frequency = 8000,
|
nl01O.inclk0_input_frequency = 8000,
|
nl11O.inclk1_input_frequency = 0,
|
nl01O.inclk1_input_frequency = 0,
|
nl11O.intended_device_family = "CYCLONEIVGX",
|
nl01O.intended_device_family = "CYCLONEIVGX",
|
nl11O.invalid_lock_multiplier = 5,
|
nl01O.invalid_lock_multiplier = 5,
|
nl11O.l0_high = 1,
|
nl01O.l0_high = 1,
|
nl11O.l0_initial = 1,
|
nl01O.l0_initial = 1,
|
nl11O.l0_low = 1,
|
nl01O.l0_low = 1,
|
nl11O.l0_mode = "BYPASS",
|
nl01O.l0_mode = "BYPASS",
|
nl11O.l0_ph = 0,
|
nl01O.l0_ph = 0,
|
nl11O.l0_time_delay = 0,
|
nl01O.l0_time_delay = 0,
|
nl11O.l1_high = 1,
|
nl01O.l1_high = 1,
|
nl11O.l1_initial = 1,
|
nl01O.l1_initial = 1,
|
nl11O.l1_low = 1,
|
nl01O.l1_low = 1,
|
nl11O.l1_mode = "BYPASS",
|
nl01O.l1_mode = "BYPASS",
|
nl11O.l1_ph = 0,
|
nl01O.l1_ph = 0,
|
nl11O.l1_time_delay = 0,
|
nl01O.l1_time_delay = 0,
|
nl11O.lock_high = 1,
|
nl01O.lock_high = 1,
|
nl11O.lock_low = 1,
|
nl01O.lock_low = 1,
|
nl11O.lock_window_ui = " 0.05",
|
nl01O.lock_window_ui = " 0.05",
|
nl11O.loop_filter_c = 5,
|
nl01O.loop_filter_c = 5,
|
nl11O.loop_filter_c_bits = 9999,
|
nl01O.loop_filter_c_bits = 9999,
|
nl11O.loop_filter_r = " 1.000000",
|
nl01O.loop_filter_r = " 1.000000",
|
nl11O.loop_filter_r_bits = 9999,
|
nl01O.loop_filter_r_bits = 9999,
|
nl11O.m = 0,
|
nl01O.m = 0,
|
nl11O.m2 = 1,
|
nl01O.m2 = 1,
|
nl11O.m_initial = 0,
|
nl01O.m_initial = 0,
|
nl11O.m_ph = 0,
|
nl01O.m_ph = 0,
|
nl11O.m_test_source = 5,
|
nl01O.m_test_source = 5,
|
nl11O.m_time_delay = 0,
|
nl01O.m_time_delay = 0,
|
nl11O.n = 1,
|
nl01O.n = 1,
|
nl11O.n2 = 1,
|
nl01O.n2 = 1,
|
nl11O.n_time_delay = 0,
|
nl01O.n_time_delay = 0,
|
nl11O.operation_mode = "no_compensation",
|
nl01O.operation_mode = "no_compensation",
|
nl11O.pfd_max = 0,
|
nl01O.pfd_max = 0,
|
nl11O.pfd_min = 0,
|
nl01O.pfd_min = 0,
|
nl11O.pll_type = "AUTO",
|
nl01O.pll_type = "AUTO",
|
nl11O.port_activeclock = "PORT_CONNECTIVITY",
|
nl01O.port_activeclock = "PORT_CONNECTIVITY",
|
nl11O.port_areset = "PORT_CONNECTIVITY",
|
nl01O.port_areset = "PORT_CONNECTIVITY",
|
nl11O.port_clk0 = "PORT_CONNECTIVITY",
|
nl01O.port_clk0 = "PORT_CONNECTIVITY",
|
nl11O.port_clk1 = "PORT_CONNECTIVITY",
|
nl01O.port_clk1 = "PORT_CONNECTIVITY",
|
nl11O.port_clk2 = "PORT_CONNECTIVITY",
|
nl01O.port_clk2 = "PORT_CONNECTIVITY",
|
nl11O.port_clk3 = "PORT_CONNECTIVITY",
|
nl01O.port_clk3 = "PORT_CONNECTIVITY",
|
nl11O.port_clk4 = "PORT_CONNECTIVITY",
|
nl01O.port_clk4 = "PORT_CONNECTIVITY",
|
nl11O.port_clk5 = "PORT_CONNECTIVITY",
|
nl01O.port_clk5 = "PORT_CONNECTIVITY",
|
nl11O.port_clk6 = "PORT_UNUSED",
|
nl01O.port_clk6 = "PORT_UNUSED",
|
nl11O.port_clk7 = "PORT_UNUSED",
|
nl01O.port_clk7 = "PORT_UNUSED",
|
nl11O.port_clk8 = "PORT_UNUSED",
|
nl01O.port_clk8 = "PORT_UNUSED",
|
nl11O.port_clk9 = "PORT_UNUSED",
|
nl01O.port_clk9 = "PORT_UNUSED",
|
nl11O.port_clkbad0 = "PORT_CONNECTIVITY",
|
nl01O.port_clkbad0 = "PORT_CONNECTIVITY",
|
nl11O.port_clkbad1 = "PORT_CONNECTIVITY",
|
nl01O.port_clkbad1 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena0 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena0 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena1 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena1 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena2 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena2 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena3 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena3 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena4 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena4 = "PORT_CONNECTIVITY",
|
nl11O.port_clkena5 = "PORT_CONNECTIVITY",
|
nl01O.port_clkena5 = "PORT_CONNECTIVITY",
|
nl11O.port_clkloss = "PORT_CONNECTIVITY",
|
nl01O.port_clkloss = "PORT_CONNECTIVITY",
|
nl11O.port_clkswitch = "PORT_CONNECTIVITY",
|
nl01O.port_clkswitch = "PORT_CONNECTIVITY",
|
nl11O.port_configupdate = "PORT_CONNECTIVITY",
|
nl01O.port_configupdate = "PORT_CONNECTIVITY",
|
nl11O.port_enable0 = "PORT_CONNECTIVITY",
|
nl01O.port_enable0 = "PORT_CONNECTIVITY",
|
nl11O.port_enable1 = "PORT_CONNECTIVITY",
|
nl01O.port_enable1 = "PORT_CONNECTIVITY",
|
nl11O.port_extclk0 = "PORT_CONNECTIVITY",
|
nl01O.port_extclk0 = "PORT_CONNECTIVITY",
|
nl11O.port_extclk1 = "PORT_CONNECTIVITY",
|
nl01O.port_extclk1 = "PORT_CONNECTIVITY",
|
nl11O.port_extclk2 = "PORT_CONNECTIVITY",
|
nl01O.port_extclk2 = "PORT_CONNECTIVITY",
|
nl11O.port_extclk3 = "PORT_CONNECTIVITY",
|
nl01O.port_extclk3 = "PORT_CONNECTIVITY",
|
nl11O.port_extclkena0 = "PORT_CONNECTIVITY",
|
nl01O.port_extclkena0 = "PORT_CONNECTIVITY",
|
nl11O.port_extclkena1 = "PORT_CONNECTIVITY",
|
nl01O.port_extclkena1 = "PORT_CONNECTIVITY",
|
nl11O.port_extclkena2 = "PORT_CONNECTIVITY",
|
nl01O.port_extclkena2 = "PORT_CONNECTIVITY",
|
nl11O.port_extclkena3 = "PORT_CONNECTIVITY",
|
nl01O.port_extclkena3 = "PORT_CONNECTIVITY",
|
nl11O.port_fbin = "PORT_CONNECTIVITY",
|
nl01O.port_fbin = "PORT_CONNECTIVITY",
|
nl11O.port_fbout = "PORT_CONNECTIVITY",
|
nl01O.port_fbout = "PORT_CONNECTIVITY",
|
nl11O.port_inclk0 = "PORT_CONNECTIVITY",
|
nl01O.port_inclk0 = "PORT_CONNECTIVITY",
|
nl11O.port_inclk1 = "PORT_CONNECTIVITY",
|
nl01O.port_inclk1 = "PORT_CONNECTIVITY",
|
nl11O.port_locked = "PORT_CONNECTIVITY",
|
nl01O.port_locked = "PORT_CONNECTIVITY",
|
nl11O.port_pfdena = "PORT_CONNECTIVITY",
|
nl01O.port_pfdena = "PORT_CONNECTIVITY",
|
nl11O.port_phasecounterselect = "PORT_CONNECTIVITY",
|
nl01O.port_phasecounterselect = "PORT_CONNECTIVITY",
|
nl11O.port_phasedone = "PORT_CONNECTIVITY",
|
nl01O.port_phasedone = "PORT_CONNECTIVITY",
|
nl11O.port_phasestep = "PORT_CONNECTIVITY",
|
nl01O.port_phasestep = "PORT_CONNECTIVITY",
|
nl11O.port_phaseupdown = "PORT_CONNECTIVITY",
|
nl01O.port_phaseupdown = "PORT_CONNECTIVITY",
|
nl11O.port_pllena = "PORT_CONNECTIVITY",
|
nl01O.port_pllena = "PORT_CONNECTIVITY",
|
nl11O.port_scanaclr = "PORT_CONNECTIVITY",
|
nl01O.port_scanaclr = "PORT_CONNECTIVITY",
|
nl11O.port_scanclk = "PORT_CONNECTIVITY",
|
nl01O.port_scanclk = "PORT_CONNECTIVITY",
|
nl11O.port_scanclkena = "PORT_CONNECTIVITY",
|
nl01O.port_scanclkena = "PORT_CONNECTIVITY",
|
nl11O.port_scandata = "PORT_CONNECTIVITY",
|
nl01O.port_scandata = "PORT_CONNECTIVITY",
|
nl11O.port_scandataout = "PORT_CONNECTIVITY",
|
nl01O.port_scandataout = "PORT_CONNECTIVITY",
|
nl11O.port_scandone = "PORT_CONNECTIVITY",
|
nl01O.port_scandone = "PORT_CONNECTIVITY",
|
nl11O.port_scanread = "PORT_CONNECTIVITY",
|
nl01O.port_scanread = "PORT_CONNECTIVITY",
|
nl11O.port_scanwrite = "PORT_CONNECTIVITY",
|
nl01O.port_scanwrite = "PORT_CONNECTIVITY",
|
nl11O.port_sclkout0 = "PORT_CONNECTIVITY",
|
nl01O.port_sclkout0 = "PORT_CONNECTIVITY",
|
nl11O.port_sclkout1 = "PORT_CONNECTIVITY",
|
nl01O.port_sclkout1 = "PORT_CONNECTIVITY",
|
nl11O.port_vcooverrange = "PORT_CONNECTIVITY",
|
nl01O.port_vcooverrange = "PORT_CONNECTIVITY",
|
nl11O.port_vcounderrange = "PORT_CONNECTIVITY",
|
nl01O.port_vcounderrange = "PORT_CONNECTIVITY",
|
nl11O.primary_clock = "INCLK0",
|
nl01O.primary_clock = "INCLK0",
|
nl11O.qualify_conf_done = "OFF",
|
nl01O.qualify_conf_done = "OFF",
|
nl11O.scan_chain = "LONG",
|
nl01O.scan_chain = "LONG",
|
nl11O.sclkout0_phase_shift = "0",
|
nl01O.sclkout0_phase_shift = "0",
|
nl11O.sclkout1_phase_shift = "0",
|
nl01O.sclkout1_phase_shift = "0",
|
nl11O.self_reset_on_gated_loss_lock = "OFF",
|
nl01O.self_reset_on_gated_loss_lock = "OFF",
|
nl11O.self_reset_on_loss_lock = "OFF",
|
nl01O.self_reset_on_loss_lock = "OFF",
|
nl11O.sim_gate_lock_device_behavior = "OFF",
|
nl01O.sim_gate_lock_device_behavior = "OFF",
|
nl11O.skip_vco = "OFF",
|
nl01O.skip_vco = "OFF",
|
nl11O.spread_frequency = 0,
|
nl01O.spread_frequency = 0,
|
nl11O.ss = 1,
|
nl01O.ss = 1,
|
nl11O.switch_over_counter = 0,
|
nl01O.switch_over_counter = 0,
|
nl11O.switch_over_on_gated_lock = "OFF",
|
nl01O.switch_over_on_gated_lock = "OFF",
|
nl11O.switch_over_on_lossclk = "OFF",
|
nl01O.switch_over_on_lossclk = "OFF",
|
nl11O.switch_over_type = "AUTO",
|
nl01O.switch_over_type = "AUTO",
|
nl11O.using_fbmimicbidir_port = "OFF",
|
nl01O.using_fbmimicbidir_port = "OFF",
|
nl11O.valid_lock_multiplier = 1,
|
nl01O.valid_lock_multiplier = 1,
|
nl11O.vco_center = 0,
|
nl01O.vco_center = 0,
|
nl11O.vco_divide_by = 0,
|
nl01O.vco_divide_by = 0,
|
nl11O.vco_frequency_control = "AUTO",
|
nl01O.vco_frequency_control = "AUTO",
|
nl11O.vco_max = 0,
|
nl01O.vco_max = 0,
|
nl11O.vco_min = 0,
|
nl01O.vco_min = 0,
|
nl11O.vco_multiply_by = 0,
|
nl01O.vco_multiply_by = 0,
|
nl11O.vco_phase_shift_step = 0,
|
nl01O.vco_phase_shift_step = 0,
|
nl11O.vco_post_scale = 0,
|
nl01O.vco_post_scale = 0,
|
nl11O.width_clock = 6,
|
nl01O.width_clock = 6,
|
nl11O.width_phasecounterselect = 4;
|
nl01O.width_phasecounterselect = 4;
|
altsyncram n00OOO
|
altsyncram n00OOO
|
(
|
(
|
.aclr0(1'b0),
|
.aclr0(1'b0),
|
.aclr1(1'b0),
|
.aclr1(1'b0),
|
.address_a({n0i1ll, n0i1li, n0i1iO, n0i10i}),
|
.address_a({n0i1ll, n0i1li, n0i1iO, n0i10i}),
|
.address_b({n0ii0i, n0ii1O, n0ii1l, n0i0lO}),
|
.address_b({n0ii0i, n0ii1O, n0ii1l, n0i0lO}),
|
.addressstall_a(1'b0),
|
.addressstall_a(1'b0),
|
.addressstall_b(1'b0),
|
.addressstall_b(1'b0),
|
.byteena_a({1'b1}),
|
.byteena_a({1'b1}),
|
.byteena_b({1'b1}),
|
.byteena_b({1'b1}),
|
.clock0(wire_nl1ii_clkout),
|
.clock0(wire_nl0ii_clkout),
|
.clock1(wire_nl10l_clkout),
|
.clock1(wire_nl00l_clkout),
|
.clocken0(1'b1),
|
.clocken0(1'b1),
|
.clocken1(1'b1),
|
.clocken1(1'b1),
|
.clocken2(1'b1),
|
.clocken2(1'b1),
|
.clocken3(1'b1),
|
.clocken3(1'b1),
|
.data_a({n01Oil, n01Oii, n01O0O, n01O0l, n01O0i, n01O1O, n01O1l, n01O1i, n01lOO, n0011O}),
|
.data_a({n01O0O, n01O0l, n01O0i, n01O1O, n01O1l, n01O1i, n01lOO, n01lOl, n01lOi, n01l0O}),
|
.data_b({10{1'b1}}),
|
.data_b({10{1'b1}}),
|
.eccstatus(),
|
.eccstatus(),
|
.q_a(),
|
.q_a(),
|
.q_b(wire_n00OOO_q_b),
|
.q_b(wire_n00OOO_q_b),
|
.rden_a(1'b1),
|
.rden_a(1'b1),
|
.rden_b(1'b1),
|
.rden_b(1'b1),
|
.wren_a(n01OiO),
|
.wren_a(n01Oii),
|
.wren_b(1'b0));
|
.wren_b(1'b0));
|
defparam
|
defparam
|
n00OOO.address_aclr_a = "NONE",
|
n00OOO.address_aclr_a = "NONE",
|
n00OOO.address_aclr_b = "NONE",
|
n00OOO.address_aclr_b = "NONE",
|
n00OOO.address_reg_b = "CLOCK1",
|
n00OOO.address_reg_b = "CLOCK1",
|
| Line 3055... |
Line 3074... |
n00OOO.clock_enable_core_b = "USE_INPUT_CLKEN",
|
n00OOO.clock_enable_core_b = "USE_INPUT_CLKEN",
|
n00OOO.clock_enable_input_a = "NORMAL",
|
n00OOO.clock_enable_input_a = "NORMAL",
|
n00OOO.clock_enable_input_b = "NORMAL",
|
n00OOO.clock_enable_input_b = "NORMAL",
|
n00OOO.clock_enable_output_a = "NORMAL",
|
n00OOO.clock_enable_output_a = "NORMAL",
|
n00OOO.clock_enable_output_b = "NORMAL",
|
n00OOO.clock_enable_output_b = "NORMAL",
|
|
n00OOO.ecc_pipeline_stage_enabled = "FALSE",
|
n00OOO.enable_ecc = "FALSE",
|
n00OOO.enable_ecc = "FALSE",
|
n00OOO.indata_aclr_a = "NONE",
|
n00OOO.indata_aclr_a = "NONE",
|
n00OOO.indata_aclr_b = "NONE",
|
n00OOO.indata_aclr_b = "NONE",
|
n00OOO.indata_reg_b = "CLOCK1",
|
n00OOO.indata_reg_b = "CLOCK1",
|
n00OOO.init_file_layout = "PORT_A",
|
n00OOO.init_file_layout = "PORT_A",
|
| Line 3095... |
Line 3115... |
.address_b({ni00iO, ni00il, ni00ii, ni001l}),
|
.address_b({ni00iO, ni00il, ni00ii, ni001l}),
|
.addressstall_a(1'b0),
|
.addressstall_a(1'b0),
|
.addressstall_b(1'b0),
|
.addressstall_b(1'b0),
|
.byteena_a({1'b1}),
|
.byteena_a({1'b1}),
|
.byteena_b({1'b1}),
|
.byteena_b({1'b1}),
|
.clock0(wire_nl10l_clkout),
|
.clock0(wire_nl00l_clkout),
|
.clock1(wire_nl10l_clkout),
|
.clock1(wire_nl00l_clkout),
|
.clocken0(1'b1),
|
.clocken0(1'b1),
|
.clocken1(1'b1),
|
.clocken1(1'b1),
|
.clocken2(1'b1),
|
.clocken2(1'b1),
|
.clocken3(1'b1),
|
.clocken3(1'b1),
|
.data_a({nill0i, nill1O, nill1l, nill1i, niliOO, niliOl, niliOi, nililO, nilill, niliil}),
|
.data_a({nill0i, nill1O, nill1l, nill1i, niliOO, niliOl, niliOi, nililO, nilill, niliil}),
|
| Line 3108... |
Line 3128... |
.eccstatus(),
|
.eccstatus(),
|
.q_a(),
|
.q_a(),
|
.q_b(wire_ni1O0i_q_b),
|
.q_b(wire_ni1O0i_q_b),
|
.rden_a(1'b1),
|
.rden_a(1'b1),
|
.rden_b(1'b1),
|
.rden_b(1'b1),
|
.wren_a(nli1lOO),
|
.wren_a(nli1l1O),
|
.wren_b(1'b0));
|
.wren_b(1'b0));
|
defparam
|
defparam
|
ni1O0i.address_aclr_a = "NONE",
|
ni1O0i.address_aclr_a = "NONE",
|
ni1O0i.address_aclr_b = "NONE",
|
ni1O0i.address_aclr_b = "NONE",
|
ni1O0i.address_reg_b = "CLOCK1",
|
ni1O0i.address_reg_b = "CLOCK1",
|
| Line 3124... |
Line 3144... |
ni1O0i.clock_enable_core_b = "USE_INPUT_CLKEN",
|
ni1O0i.clock_enable_core_b = "USE_INPUT_CLKEN",
|
ni1O0i.clock_enable_input_a = "NORMAL",
|
ni1O0i.clock_enable_input_a = "NORMAL",
|
ni1O0i.clock_enable_input_b = "NORMAL",
|
ni1O0i.clock_enable_input_b = "NORMAL",
|
ni1O0i.clock_enable_output_a = "NORMAL",
|
ni1O0i.clock_enable_output_a = "NORMAL",
|
ni1O0i.clock_enable_output_b = "NORMAL",
|
ni1O0i.clock_enable_output_b = "NORMAL",
|
|
ni1O0i.ecc_pipeline_stage_enabled = "FALSE",
|
ni1O0i.enable_ecc = "FALSE",
|
ni1O0i.enable_ecc = "FALSE",
|
ni1O0i.indata_aclr_a = "NONE",
|
ni1O0i.indata_aclr_a = "NONE",
|
ni1O0i.indata_aclr_b = "NONE",
|
ni1O0i.indata_aclr_b = "NONE",
|
ni1O0i.indata_reg_b = "CLOCK1",
|
ni1O0i.indata_reg_b = "CLOCK1",
|
ni1O0i.init_file_layout = "PORT_A",
|
ni1O0i.init_file_layout = "PORT_A",
|
| Line 3154... |
Line 3175... |
ni1O0i.widthad_b = 4,
|
ni1O0i.widthad_b = 4,
|
ni1O0i.wrcontrol_aclr_a = "NONE",
|
ni1O0i.wrcontrol_aclr_a = "NONE",
|
ni1O0i.wrcontrol_aclr_b = "NONE",
|
ni1O0i.wrcontrol_aclr_b = "NONE",
|
ni1O0i.wrcontrol_wraddress_reg_b = "CLOCK1",
|
ni1O0i.wrcontrol_wraddress_reg_b = "CLOCK1",
|
ni1O0i.lpm_hint = "WIDTH_BYTEENA=1";
|
ni1O0i.lpm_hint = "WIDTH_BYTEENA=1";
|
cycloneiv_hssi_calibration_block nl1iO
|
cycloneiv_hssi_calibration_block nl0iO
|
(
|
(
|
.calibrationstatus(),
|
.calibrationstatus(),
|
.clk(gxb_cal_blk_clk),
|
.clk(gxb_cal_blk_clk),
|
.nonusertocmu(wire_nl1iO_nonusertocmu),
|
.nonusertocmu(wire_nl0iO_nonusertocmu),
|
.powerdn(1'b0),
|
.powerdn(1'b0),
|
.testctrl()
|
.testctrl()
|
);
|
);
|
cycloneiv_hssi_cmu nl1il
|
cycloneiv_hssi_cmu nl0il
|
(
|
(
|
.adet({4{1'b0}}),
|
.adet({4{1'b0}}),
|
.alignstatus(),
|
.alignstatus(),
|
.coreclkout(),
|
.coreclkout(),
|
.digitaltestout(),
|
.digitaltestout(),
|
.dpclk(reconfig_clk),
|
.dpclk(reconfig_clk),
|
.dpriodisable(reconfig_togxb[1]),
|
.dpriodisable(reconfig_togxb[1]),
|
.dpriodisableout(wire_nl1il_dpriodisableout),
|
.dpriodisableout(wire_nl0il_dpriodisableout),
|
.dprioin(reconfig_togxb[0]),
|
.dprioin(reconfig_togxb[0]),
|
.dprioload(reconfig_togxb[2]),
|
.dprioload(reconfig_togxb[2]),
|
.dpriooe(),
|
.dpriooe(),
|
.dprioout(wire_nl1il_dprioout),
|
.dprioout(wire_nl0il_dprioout),
|
.enabledeskew(),
|
.enabledeskew(),
|
.fiforesetrd(),
|
.fiforesetrd(),
|
.fixedclk({{3{1'b0}}, ((reconfig_clk & ((~ nl1lO) & (~ nl1li))) & (nlii0iO18 ^ nlii0iO17))}),
|
.fixedclk({{3{1'b0}}, (reconfig_clk & ((~ nl0lO) & (~ nl0li)))}),
|
.nonuserfromcal(wire_nl1iO_nonusertocmu),
|
.nonuserfromcal(wire_nl0iO_nonusertocmu),
|
.quadreset(gxb_pwrdn_in),
|
.quadreset(gxb_pwrdn_in),
|
.quadresetout(wire_nl1il_quadresetout),
|
.quadresetout(wire_nl0il_quadresetout),
|
.rdalign({4{1'b0}}),
|
.rdalign({4{1'b0}}),
|
.rdenablesync(1'b0),
|
.rdenablesync(1'b0),
|
.recovclk(1'b0),
|
.recovclk(1'b0),
|
.refclkout(),
|
.refclkout(),
|
.rxanalogreset({{3{1'b0}}, ((~ reconfig_togxb[3]) & n1i0O)}),
|
.rxanalogreset({{3{1'b0}}, ((~ reconfig_togxb[3]) & n1l1i)}),
|
.rxanalogresetout(wire_nl1il_rxanalogresetout),
|
.rxanalogresetout(wire_nl0il_rxanalogresetout),
|
.rxcrupowerdown(wire_nl1il_rxcrupowerdown),
|
.rxcrupowerdown(wire_nl0il_rxcrupowerdown),
|
.rxctrl({4{1'b0}}),
|
.rxctrl({4{1'b0}}),
|
.rxctrlout(),
|
.rxctrlout(),
|
.rxdatain({32{1'b0}}),
|
.rxdatain({32{1'b0}}),
|
.rxdataout(),
|
.rxdataout(),
|
.rxdatavalid({4{1'b0}}),
|
.rxdatavalid({4{1'b0}}),
|
.rxdigitalreset({{3{1'b0}}, nliiiOl}),
|
.rxdigitalreset({{3{1'b0}}, nliii0O}),
|
.rxdigitalresetout(wire_nl1il_rxdigitalresetout),
|
.rxdigitalresetout(wire_nl0il_rxdigitalresetout),
|
.rxibpowerdown(wire_nl1il_rxibpowerdown),
|
.rxibpowerdown(wire_nl0il_rxibpowerdown),
|
.rxpcsdprioin({{1200{1'b0}}, wire_nl1ii_dprioout[399:0]}),
|
.rxpcsdprioin({{1200{1'b0}}, wire_nl0ii_dprioout[399:0]}),
|
.rxpcsdprioout(wire_nl1il_rxpcsdprioout),
|
.rxpcsdprioout(wire_nl0il_rxpcsdprioout),
|
.rxphfifox4byteselout(),
|
.rxphfifox4byteselout(),
|
.rxphfifox4rdenableout(),
|
.rxphfifox4rdenableout(),
|
.rxphfifox4wrclkout(),
|
.rxphfifox4wrclkout(),
|
.rxphfifox4wrenableout(),
|
.rxphfifox4wrenableout(),
|
.rxpmadprioin({{900{1'b0}}, wire_nl10O_dprioout[299:0]}),
|
.rxpmadprioin({{900{1'b0}}, wire_nl00O_dprioout[299:0]}),
|
.rxpmadprioout(wire_nl1il_rxpmadprioout),
|
.rxpmadprioout(wire_nl0il_rxpmadprioout),
|
.rxpowerdown({4{1'b0}}),
|
.rxpowerdown({4{1'b0}}),
|
.rxrunningdisp({4{1'b0}}),
|
.rxrunningdisp({4{1'b0}}),
|
.syncstatus({4{1'b0}}),
|
.syncstatus({4{1'b0}}),
|
.testout(),
|
.testout(),
|
.txanalogresetout(wire_nl1il_txanalogresetout),
|
.txanalogresetout(wire_nl0il_txanalogresetout),
|
.txctrl({4{1'b0}}),
|
.txctrl({4{1'b0}}),
|
.txctrlout(),
|
.txctrlout(),
|
.txdatain({32{1'b0}}),
|
.txdatain({32{1'b0}}),
|
.txdataout(),
|
.txdataout(),
|
.txdetectrxpowerdown(wire_nl1il_txdetectrxpowerdown),
|
.txdetectrxpowerdown(wire_nl0il_txdetectrxpowerdown),
|
.txdigitalreset({{3{1'b0}}, nliil1l}),
|
.txdigitalreset({{3{1'b0}}, nliiiiO}),
|
.txdigitalresetout(wire_nl1il_txdigitalresetout),
|
.txdigitalresetout(wire_nl0il_txdigitalresetout),
|
.txdividerpowerdown(wire_nl1il_txdividerpowerdown),
|
.txdividerpowerdown(wire_nl0il_txdividerpowerdown),
|
.txobpowerdown(wire_nl1il_txobpowerdown),
|
.txobpowerdown(wire_nl0il_txobpowerdown),
|
.txpcsdprioin({{450{1'b0}}, wire_nl10l_dprioout[149:0]}),
|
.txpcsdprioin({{450{1'b0}}, wire_nl00l_dprioout[149:0]}),
|
.txpcsdprioout(wire_nl1il_txpcsdprioout),
|
.txpcsdprioout(wire_nl0il_txpcsdprioout),
|
.txphfifox4byteselout(),
|
.txphfifox4byteselout(),
|
.txphfifox4rdclkout(),
|
.txphfifox4rdclkout(),
|
.txphfifox4rdenableout(),
|
.txphfifox4rdenableout(),
|
.txphfifox4wrenableout(),
|
.txphfifox4wrenableout(),
|
.txpmadprioin({{900{1'b0}}, wire_nl10i_dprioout[299:0]}),
|
.txpmadprioin({{900{1'b0}}, wire_nl00i_dprioout[299:0]}),
|
.txpmadprioout(wire_nl1il_txpmadprioout),
|
.txpmadprioout(wire_nl0il_txpmadprioout),
|
.pmacramtest(),
|
.pmacramtest(),
|
.refclkdig(),
|
.refclkdig(),
|
.rxcoreclk(),
|
.rxcoreclk(),
|
.rxphfifordenable(),
|
.rxphfifordenable(),
|
.rxphfiforeset(),
|
.rxphfiforeset(),
|
| Line 3243... |
Line 3264... |
.txphfiforddisable(),
|
.txphfiforddisable(),
|
.txphfiforeset(),
|
.txphfiforeset(),
|
.txphfifowrenable()
|
.txphfifowrenable()
|
);
|
);
|
defparam
|
defparam
|
nl1il.auto_spd_deassert_ph_fifo_rst_count = 8,
|
nl0il.auto_spd_deassert_ph_fifo_rst_count = 8,
|
nl1il.auto_spd_phystatus_notify_count = 0,
|
nl0il.auto_spd_phystatus_notify_count = 0,
|
nl1il.devaddr = 1,
|
nl0il.devaddr = 1,
|
nl1il.dprio_config_mode = 6'h01,
|
nl0il.dprio_config_mode = 6'h01,
|
nl1il.in_xaui_mode = "false",
|
nl0il.in_xaui_mode = "false",
|
nl1il.lpm_type = "cycloneiv_hssi_cmu",
|
nl0il.lpm_type = "cycloneiv_hssi_cmu",
|
nl1il.portaddr = 1,
|
nl0il.portaddr = 1,
|
nl1il.rx0_channel_bonding = "none",
|
nl0il.rx0_channel_bonding = "none",
|
nl1il.rx0_clk1_mux_select = "recovered clock",
|
nl0il.rx0_clk1_mux_select = "recovered clock",
|
nl1il.rx0_clk2_mux_select = "recovered clock",
|
nl0il.rx0_clk2_mux_select = "recovered clock",
|
nl1il.rx0_ph_fifo_reg_mode = "false",
|
nl0il.rx0_ph_fifo_reg_mode = "false",
|
nl1il.rx0_rd_clk_mux_select = "core clock",
|
nl0il.rx0_rd_clk_mux_select = "core clock",
|
nl1il.rx0_recovered_clk_mux_select = "recovered clock",
|
nl0il.rx0_recovered_clk_mux_select = "recovered clock",
|
nl1il.rx0_reset_clock_output_during_digital_reset = "false",
|
nl0il.rx0_reset_clock_output_during_digital_reset = "false",
|
nl1il.rx0_use_double_data_mode = "false",
|
nl0il.rx0_use_double_data_mode = "false",
|
nl1il.tx0_channel_bonding = "none",
|
nl0il.tx0_channel_bonding = "none",
|
nl1il.tx0_rd_clk_mux_select = "central",
|
nl0il.tx0_rd_clk_mux_select = "central",
|
nl1il.tx0_reset_clock_output_during_digital_reset = "false",
|
nl0il.tx0_reset_clock_output_during_digital_reset = "false",
|
nl1il.tx0_use_double_data_mode = "false",
|
nl0il.tx0_use_double_data_mode = "false",
|
nl1il.tx0_wr_clk_mux_select = "core_clk",
|
nl0il.tx0_wr_clk_mux_select = "core_clk",
|
nl1il.use_coreclk_out_post_divider = "false",
|
nl0il.use_coreclk_out_post_divider = "false",
|
nl1il.use_deskew_fifo = "false";
|
nl0il.use_deskew_fifo = "false";
|
cycloneiv_hssi_rx_pcs nl1ii
|
cycloneiv_hssi_rx_pcs nl0ii
|
(
|
(
|
.a1a2size(1'b0),
|
.a1a2size(1'b0),
|
.a1a2sizeout(),
|
.a1a2sizeout(),
|
.a1detect(),
|
.a1detect(),
|
.a2detect(),
|
.a2detect(),
|
| Line 3281... |
Line 3302... |
.bisterr(),
|
.bisterr(),
|
.bitslipboundaryselectout(),
|
.bitslipboundaryselectout(),
|
.byteorderalignstatus(),
|
.byteorderalignstatus(),
|
.cdrctrlearlyeios(),
|
.cdrctrlearlyeios(),
|
.cdrctrllocktorefcl(reconfig_togxb[3]),
|
.cdrctrllocktorefcl(reconfig_togxb[3]),
|
.cdrctrllocktorefclkout(wire_nl1ii_cdrctrllocktorefclkout),
|
.cdrctrllocktorefclkout(wire_nl0ii_cdrctrllocktorefclkout),
|
.clkout(wire_nl1ii_clkout),
|
.clkout(wire_nl0ii_clkout),
|
.coreclk(wire_nl1ii_clkout),
|
.coreclk(wire_nl0ii_clkout),
|
.coreclkout(),
|
.coreclkout(),
|
.ctrldetect(wire_nl1ii_ctrldetect),
|
.ctrldetect(wire_nl0ii_ctrldetect),
|
.datain({wire_nl10O_recoverdataout[9:0]}),
|
.datain({wire_nl00O_recoverdataout[9:0]}),
|
.dataout(wire_nl1ii_dataout),
|
.dataout(wire_nl0ii_dataout),
|
.dataoutfull(),
|
.dataoutfull(),
|
.digitalreset(wire_nl1il_rxdigitalresetout[0]),
|
.digitalreset(wire_nl0il_rxdigitalresetout[0]),
|
.disperr(wire_nl1ii_disperr),
|
.disperr(wire_nl0ii_disperr),
|
.dpriodisable(wire_nl1il_dpriodisableout),
|
.dpriodisable(wire_nl0il_dpriodisableout),
|
.dprioin({wire_nl1il_rxpcsdprioout[399:0]}),
|
.dprioin({wire_nl0il_rxpcsdprioout[399:0]}),
|
.dprioout(wire_nl1ii_dprioout),
|
.dprioout(wire_nl0ii_dprioout),
|
.enabledeskew(1'b0),
|
.enabledeskew(1'b0),
|
.enabyteord(1'b0),
|
.enabyteord(1'b0),
|
.enapatternalign(1'b0),
|
.enapatternalign(1'b0),
|
.errdetect(wire_nl1ii_errdetect),
|
.errdetect(wire_nl0ii_errdetect),
|
.fifordin(1'b0),
|
.fifordin(1'b0),
|
.fifordout(),
|
.fifordout(),
|
.fiforesetrd(1'b0),
|
.fiforesetrd(1'b0),
|
.hipdataout(),
|
.hipdataout(),
|
.hipdatavalid(),
|
.hipdatavalid(),
|
| Line 3311... |
Line 3332... |
.invpol(1'b0),
|
.invpol(1'b0),
|
.k1detect(),
|
.k1detect(),
|
.k2detect(),
|
.k2detect(),
|
.masterclk(1'b0),
|
.masterclk(1'b0),
|
.parallelfdbk({20{1'b0}}),
|
.parallelfdbk({20{1'b0}}),
|
.patterndetect(wire_nl1ii_patterndetect),
|
.patterndetect(wire_nl0ii_patterndetect),
|
.phfifooverflow(),
|
.phfifooverflow(),
|
.phfifordenable(1'b1),
|
.phfifordenable(1'b1),
|
.phfifordenableout(),
|
.phfifordenableout(),
|
.phfiforeset(1'b0),
|
.phfiforeset(1'b0),
|
.phfiforesetout(),
|
.phfiforesetout(),
|
| Line 3329... |
Line 3350... |
.pipepowerdown({2{1'b0}}),
|
.pipepowerdown({2{1'b0}}),
|
.pipepowerstate({4{1'b0}}),
|
.pipepowerstate({4{1'b0}}),
|
.pipestatetransdoneout(),
|
.pipestatetransdoneout(),
|
.pipestatus(),
|
.pipestatus(),
|
.prbscidenable(1'b0),
|
.prbscidenable(1'b0),
|
.quadreset(wire_nl1il_quadresetout),
|
.quadreset(wire_nl0il_quadresetout),
|
.rdalign(),
|
.rdalign(),
|
.recoveredclk(wire_nl10O_clockout),
|
.recoveredclk(wire_nl00O_clockout),
|
.revbitorderwa(1'b0),
|
.revbitorderwa(1'b0),
|
.revparallelfdbkdata(),
|
.revparallelfdbkdata(),
|
.rlv(wire_nl1ii_rlv),
|
.rlv(wire_nl0ii_rlv),
|
.rmfifodatadeleted(),
|
.rmfifodatadeleted(),
|
.rmfifodatainserted(),
|
.rmfifodatainserted(),
|
.rmfifoempty(),
|
.rmfifoempty(),
|
.rmfifofull(),
|
.rmfifofull(),
|
.rmfifordena(1'b0),
|
.rmfifordena(1'b0),
|
.rmfiforeset(1'b0),
|
.rmfiforeset(1'b0),
|
.rmfifowrena(1'b0),
|
.rmfifowrena(1'b0),
|
.runningdisp(wire_nl1ii_runningdisp),
|
.runningdisp(wire_nl0ii_runningdisp),
|
.rxdetectvalid(1'b0),
|
.rxdetectvalid(1'b0),
|
.rxfound({2{1'b0}}),
|
.rxfound({2{1'b0}}),
|
.signaldetect(),
|
.signaldetect(),
|
.signaldetected(wire_nl10O_signaldetect),
|
.signaldetected(wire_nl00O_signaldetect),
|
.syncstatus(wire_nl1ii_syncstatus),
|
.syncstatus(wire_nl0ii_syncstatus),
|
.syncstatusdeskew(),
|
.syncstatusdeskew(),
|
.xauidelcondmetout(),
|
.xauidelcondmetout(),
|
.xauififoovrout(),
|
.xauififoovrout(),
|
.xauiinsertincompleteout(),
|
.xauiinsertincompleteout(),
|
.xauilatencycompout(),
|
.xauilatencycompout(),
|
| Line 3383... |
Line 3404... |
.xauififoovr(),
|
.xauififoovr(),
|
.xauiinsertincomplete(),
|
.xauiinsertincomplete(),
|
.xauilatencycomp()
|
.xauilatencycomp()
|
);
|
);
|
defparam
|
defparam
|
nl1ii.align_pattern = "0101111100",
|
nl0ii.align_pattern = "1111100",
|
nl1ii.align_pattern_length = 10,
|
nl0ii.align_pattern_length = 7,
|
nl1ii.allow_align_polarity_inversion = "false",
|
nl0ii.allow_align_polarity_inversion = "false",
|
nl1ii.allow_pipe_polarity_inversion = "false",
|
nl0ii.allow_pipe_polarity_inversion = "false",
|
nl1ii.auto_spd_deassert_ph_fifo_rst_count = 8,
|
nl0ii.auto_spd_deassert_ph_fifo_rst_count = 8,
|
nl1ii.auto_spd_phystatus_notify_count = 0,
|
nl0ii.auto_spd_phystatus_notify_count = 0,
|
nl1ii.bit_slip_enable = "false",
|
nl0ii.bit_slip_enable = "false",
|
nl1ii.byte_order_mode = "none",
|
nl0ii.byte_order_mode = "none",
|
nl1ii.byte_order_pad_pattern = "0",
|
nl0ii.byte_order_pad_pattern = "0",
|
nl1ii.byte_order_pattern = "0",
|
nl0ii.byte_order_pattern = "0",
|
nl1ii.byte_order_pld_ctrl_enable = "false",
|
nl0ii.byte_order_pld_ctrl_enable = "false",
|
nl1ii.cdrctrl_bypass_ppm_detector_cycle = 1000,
|
nl0ii.cdrctrl_bypass_ppm_detector_cycle = 1000,
|
nl1ii.cdrctrl_enable = "false",
|
nl0ii.cdrctrl_enable = "false",
|
nl1ii.cdrctrl_mask_cycle = 800,
|
nl0ii.cdrctrl_mask_cycle = 800,
|
nl1ii.cdrctrl_min_lock_to_ref_cycle = 63,
|
nl0ii.cdrctrl_min_lock_to_ref_cycle = 63,
|
nl1ii.cdrctrl_rxvalid_mask = "false",
|
nl0ii.cdrctrl_rxvalid_mask = "false",
|
nl1ii.channel_bonding = "none",
|
nl0ii.channel_bonding = "none",
|
nl1ii.channel_number = 0,
|
nl0ii.channel_number = 0,
|
nl1ii.channel_width = 8,
|
nl0ii.channel_width = 8,
|
nl1ii.clk1_mux_select = "recovered clock",
|
nl0ii.clk1_mux_select = "recovered clock",
|
nl1ii.clk2_mux_select = "recovered clock",
|
nl0ii.clk2_mux_select = "recovered clock",
|
nl1ii.core_clock_0ppm = "false",
|
nl0ii.core_clock_0ppm = "false",
|
nl1ii.datapath_low_latency_mode = "false",
|
nl0ii.datapath_low_latency_mode = "false",
|
nl1ii.datapath_protocol = "basic",
|
nl0ii.datapath_protocol = "basic",
|
nl1ii.dec_8b_10b_compatibility_mode = "true",
|
nl0ii.dec_8b_10b_compatibility_mode = "true",
|
nl1ii.dec_8b_10b_mode = "normal",
|
nl0ii.dec_8b_10b_mode = "normal",
|
nl1ii.deskew_pattern = "0",
|
nl0ii.deskew_pattern = "0",
|
nl1ii.disable_auto_idle_insertion = "true",
|
nl0ii.disable_auto_idle_insertion = "true",
|
nl1ii.disable_running_disp_in_word_align = "false",
|
nl0ii.disable_running_disp_in_word_align = "false",
|
nl1ii.disallow_kchar_after_pattern_ordered_set = "false",
|
nl0ii.disallow_kchar_after_pattern_ordered_set = "false",
|
nl1ii.dprio_config_mode = 6'h01,
|
nl0ii.dprio_config_mode = 6'h01,
|
nl1ii.elec_idle_infer_enable = "false",
|
nl0ii.elec_idle_infer_enable = "false",
|
nl1ii.elec_idle_num_com_detect = 3,
|
nl0ii.elec_idle_num_com_detect = 3,
|
nl1ii.enable_bit_reversal = "false",
|
nl0ii.enable_bit_reversal = "false",
|
nl1ii.enable_self_test_mode = "false",
|
nl0ii.enable_self_test_mode = "false",
|
nl1ii.force_signal_detect_dig = "true",
|
nl0ii.force_signal_detect_dig = "true",
|
nl1ii.hip_enable = "false",
|
nl0ii.hip_enable = "false",
|
nl1ii.infiniband_invalid_code = 0,
|
nl0ii.infiniband_invalid_code = 0,
|
nl1ii.insert_pad_on_underflow = "false",
|
nl0ii.insert_pad_on_underflow = "false",
|
nl1ii.lpm_type = "cycloneiv_hssi_rx_pcs",
|
nl0ii.lpm_type = "cycloneiv_hssi_rx_pcs",
|
nl1ii.num_align_code_groups_in_ordered_set = 1,
|
nl0ii.num_align_code_groups_in_ordered_set = 1,
|
nl1ii.num_align_cons_good_data = 4,
|
nl0ii.num_align_cons_good_data = 4,
|
nl1ii.num_align_cons_pat = 3,
|
nl0ii.num_align_cons_pat = 3,
|
nl1ii.num_align_loss_sync_error = 4,
|
nl0ii.num_align_loss_sync_error = 4,
|
nl1ii.ph_fifo_low_latency_enable = "true",
|
nl0ii.ph_fifo_low_latency_enable = "true",
|
nl1ii.ph_fifo_reg_mode = "false",
|
nl0ii.ph_fifo_reg_mode = "false",
|
nl1ii.protocol_hint = "gige",
|
nl0ii.protocol_hint = "gige",
|
nl1ii.rate_match_back_to_back = "true",
|
nl0ii.rate_match_back_to_back = "true",
|
nl1ii.rate_match_delete_threshold = 13,
|
nl0ii.rate_match_delete_threshold = 13,
|
nl1ii.rate_match_empty_threshold = 5,
|
nl0ii.rate_match_empty_threshold = 5,
|
nl1ii.rate_match_fifo_mode = "false",
|
nl0ii.rate_match_fifo_mode = "false",
|
nl1ii.rate_match_full_threshold = 20,
|
nl0ii.rate_match_full_threshold = 20,
|
nl1ii.rate_match_insert_threshold = 11,
|
nl0ii.rate_match_insert_threshold = 11,
|
nl1ii.rate_match_ordered_set_based = "true",
|
nl0ii.rate_match_ordered_set_based = "true",
|
nl1ii.rate_match_pattern1 = "10100010010101111100",
|
nl0ii.rate_match_pattern1 = "10100010010101111100",
|
nl1ii.rate_match_pattern2 = "10101011011010000011",
|
nl0ii.rate_match_pattern2 = "10101011011010000011",
|
nl1ii.rate_match_pattern_size = 20,
|
nl0ii.rate_match_pattern_size = 20,
|
nl1ii.rate_match_reset_enable = "false",
|
nl0ii.rate_match_reset_enable = "false",
|
nl1ii.rate_match_skip_set_based = "false",
|
nl0ii.rate_match_skip_set_based = "false",
|
nl1ii.rate_match_start_threshold = 7,
|
nl0ii.rate_match_start_threshold = 7,
|
nl1ii.rd_clk_mux_select = "core clock",
|
nl0ii.rd_clk_mux_select = "core clock",
|
nl1ii.recovered_clk_mux_select = "recovered clock",
|
nl0ii.recovered_clk_mux_select = "recovered clock",
|
nl1ii.run_length = 5,
|
nl0ii.run_length = 5,
|
nl1ii.run_length_enable = "true",
|
nl0ii.run_length_enable = "true",
|
nl1ii.rx_detect_bypass = "false",
|
nl0ii.rx_detect_bypass = "false",
|
nl1ii.rx_phfifo_wait_cnt = 15,
|
nl0ii.rx_phfifo_wait_cnt = 15,
|
nl1ii.rxstatus_error_report_mode = 0,
|
nl0ii.rxstatus_error_report_mode = 0,
|
nl1ii.self_test_mode = "incremental",
|
nl0ii.self_test_mode = "incremental",
|
nl1ii.use_alignment_state_machine = "true",
|
nl0ii.use_alignment_state_machine = "true",
|
nl1ii.use_deskew_fifo = "false",
|
nl0ii.use_deskew_fifo = "false",
|
nl1ii.use_double_data_mode = "false",
|
nl0ii.use_double_data_mode = "false",
|
nl1ii.use_parallel_loopback = "false";
|
nl0ii.use_parallel_loopback = "false";
|
cycloneiv_hssi_rx_pma nl10O
|
cycloneiv_hssi_rx_pma nl00O
|
(
|
(
|
.analogtestbus(),
|
.analogtestbus(),
|
.clockout(wire_nl10O_clockout),
|
.clockout(wire_nl00O_clockout),
|
.crupowerdn(wire_nl1il_rxcrupowerdown[0]),
|
.crupowerdn(wire_nl0il_rxcrupowerdown[0]),
|
.datain(rxp),
|
.datain(rxp),
|
.datastrobeout(),
|
.datastrobeout(),
|
.deserclock(wire_nl11O_icdrclk),
|
.deserclock(wire_nl01O_icdrclk),
|
.diagnosticlpbkout(wire_nl10O_diagnosticlpbkout),
|
.diagnosticlpbkout(wire_nl00O_diagnosticlpbkout),
|
.dpriodisable(wire_nl1il_dpriodisableout),
|
.dpriodisable(wire_nl0il_dpriodisableout),
|
.dprioin({wire_nl1il_rxpmadprioout[299:0]}),
|
.dprioin({wire_nl0il_rxpmadprioout[299:0]}),
|
.dprioout(wire_nl10O_dprioout),
|
.dprioout(wire_nl00O_dprioout),
|
.freqlocked(wire_nl10O_freqlocked),
|
.freqlocked(wire_nl00O_freqlocked),
|
.locktodata(1'b0),
|
.locktodata(1'b0),
|
.locktoref(wire_nl1ii_cdrctrllocktorefclkout),
|
.locktoref(wire_nl0ii_cdrctrllocktorefclkout),
|
.locktorefout(),
|
.locktorefout(),
|
.powerdn(wire_nl1il_rxibpowerdown[0]),
|
.powerdn(wire_nl0il_rxibpowerdown[0]),
|
.ppmdetectrefclk(wire_nl11O_fref),
|
.ppmdetectrefclk(wire_nl01O_fref),
|
.recoverdataout(wire_nl10O_recoverdataout),
|
.recoverdataout(wire_nl00O_recoverdataout),
|
.reverselpbkout(wire_nl10O_reverselpbkout),
|
.reverselpbkout(wire_nl00O_reverselpbkout),
|
.rxpmareset(wire_nl1il_rxanalogresetout[0]),
|
.rxpmareset(wire_nl0il_rxanalogresetout[0]),
|
.seriallpbkin(wire_nl10i_seriallpbkout),
|
.seriallpbkin(wire_nl00i_seriallpbkout),
|
.signaldetect(wire_nl10O_signaldetect),
|
.signaldetect(wire_nl00O_signaldetect),
|
.testbussel({1'b0, {2{1'b1}}, 1'b0}),
|
.testbussel({1'b0, {2{1'b1}}, 1'b0}),
|
.dpashift()
|
.dpashift()
|
);
|
);
|
defparam
|
defparam
|
nl10O.allow_serial_loopback = "false",
|
nl00O.allow_serial_loopback = "false",
|
nl10O.channel_number = 0,
|
nl00O.channel_number = 0,
|
nl10O.common_mode = "0.82V",
|
nl00O.common_mode = "0.82V",
|
nl10O.deserialization_factor = 10,
|
nl00O.deserialization_factor = 10,
|
nl10O.dprio_config_mode = 6'h01,
|
nl00O.dprio_config_mode = 6'h01,
|
nl10O.effective_data_rate = "1250.0 Mbps",
|
nl00O.effective_data_rate = "1250.0 Mbps",
|
nl10O.enable_local_divider = "false",
|
nl00O.enable_local_divider = "false",
|
nl10O.enable_ltd = "false",
|
nl00O.enable_ltd = "false",
|
nl10O.enable_ltr = "false",
|
nl00O.enable_ltr = "false",
|
nl10O.enable_second_order_loop = "false",
|
nl00O.enable_second_order_loop = "false",
|
nl10O.eq_dc_gain = 0,
|
nl00O.eq_dc_gain = 0,
|
nl10O.eq_setting = 1,
|
nl00O.eq_setting = 1,
|
nl10O.force_signal_detect = "true",
|
nl00O.force_signal_detect = "true",
|
nl10O.logical_channel_address = 0,
|
nl00O.logical_channel_address = 0,
|
nl10O.loop_1_digital_filter = 8,
|
nl00O.loop_1_digital_filter = 8,
|
nl10O.lpm_type = "cycloneiv_hssi_rx_pma",
|
nl00O.lpm_type = "cycloneiv_hssi_rx_pma",
|
nl10O.offset_cancellation = 1,
|
nl00O.offset_cancellation = 1,
|
nl10O.ppm_gen1_2_xcnt_en = 1,
|
nl00O.ppm_gen1_2_xcnt_en = 1,
|
nl10O.ppm_post_eidle = 0,
|
nl00O.ppm_post_eidle = 0,
|
nl10O.ppmselect = 8,
|
nl00O.ppmselect = 8,
|
nl10O.protocol_hint = "gige",
|
nl00O.protocol_hint = "gige",
|
nl10O.signal_detect_hysteresis = 8,
|
nl00O.signal_detect_hysteresis = 8,
|
nl10O.signal_detect_hysteresis_valid_threshold = 14,
|
nl00O.signal_detect_hysteresis_valid_threshold = 14,
|
nl10O.signal_detect_loss_threshold = 1,
|
nl00O.signal_detect_loss_threshold = 1,
|
nl10O.termination = "OCT 100 Ohms",
|
nl00O.termination = "OCT 100 Ohms",
|
nl10O.use_external_termination = "false";
|
nl00O.use_external_termination = "false";
|
cycloneiv_hssi_tx_pcs nl10l
|
cycloneiv_hssi_tx_pcs nl00l
|
(
|
(
|
.clkout(wire_nl10l_clkout),
|
.clkout(wire_nl00l_clkout),
|
.coreclk(wire_nl10l_clkout),
|
.coreclk(wire_nl00l_clkout),
|
.coreclkout(),
|
.coreclkout(),
|
.ctrlenable({1'b0, n1i01i}),
|
.ctrlenable({1'b0, n1i1lO}),
|
.datain({{12{1'b0}}, n1i0Oi, n1i0lO, n1i0ll, n1i0li, n1i0iO, n1i0il, n1i0ii, n1i00O}),
|
.datain({{12{1'b0}}, n1i0iO, n1i0il, n1i0ii, n1i00O, n1i00l, n1i00i, n1i01O, n1i01l}),
|
.datainfull({22{1'b0}}),
|
.datainfull({22{1'b0}}),
|
.dataout(wire_nl10l_dataout),
|
.dataout(wire_nl00l_dataout),
|
.detectrxloop(1'b0),
|
.detectrxloop(1'b0),
|
.digitalreset(wire_nl1il_txdigitalresetout[0]),
|
.digitalreset(wire_nl0il_txdigitalresetout[0]),
|
.dpriodisable(wire_nl1il_dpriodisableout),
|
.dpriodisable(wire_nl0il_dpriodisableout),
|
.dprioin({wire_nl1il_txpcsdprioout[149:0]}),
|
.dprioin({wire_nl0il_txpcsdprioout[149:0]}),
|
.dprioout(wire_nl10l_dprioout),
|
.dprioout(wire_nl00l_dprioout),
|
.enrevparallellpbk(1'b0),
|
.enrevparallellpbk(1'b0),
|
.forcedisp({2{1'b0}}),
|
.forcedisp({2{1'b0}}),
|
.forceelecidleout(),
|
.forceelecidleout(),
|
.grayelecidleinferselout(),
|
.grayelecidleinferselout(),
|
.hiptxclkout(),
|
.hiptxclkout(),
|
.invpol(1'b0),
|
.invpol(1'b0),
|
.localrefclk(wire_nl10i_clockout),
|
.localrefclk(wire_nl00i_clockout),
|
.parallelfdbkout(),
|
.parallelfdbkout(),
|
.phfifooverflow(),
|
.phfifooverflow(),
|
.phfiforddisable(1'b0),
|
.phfiforddisable(1'b0),
|
.phfiforddisableout(),
|
.phfiforddisableout(),
|
.phfiforeset(1'b0),
|
.phfiforeset(1'b0),
|
| Line 3543... |
Line 3564... |
.pipeenrevparallellpbkout(),
|
.pipeenrevparallellpbkout(),
|
.pipepowerdownout(),
|
.pipepowerdownout(),
|
.pipepowerstateout(),
|
.pipepowerstateout(),
|
.pipestatetransdone(1'b0),
|
.pipestatetransdone(1'b0),
|
.powerdn({2{1'b0}}),
|
.powerdn({2{1'b0}}),
|
.quadreset(wire_nl1il_quadresetout),
|
.quadreset(wire_nl0il_quadresetout),
|
.rdenablesync(),
|
.rdenablesync(),
|
.revparallelfdbk({20{1'b0}}),
|
.revparallelfdbk({20{1'b0}}),
|
.txdetectrx(wire_nl10l_txdetectrx),
|
.txdetectrx(wire_nl00l_txdetectrx),
|
.xgmctrlenable(),
|
.xgmctrlenable(),
|
.xgmdataout(),
|
.xgmdataout(),
|
.bitslipboundaryselect(),
|
.bitslipboundaryselect(),
|
.dispval(),
|
.dispval(),
|
.elecidleinfersel(),
|
.elecidleinfersel(),
|
| Line 3569... |
Line 3590... |
.refclk(),
|
.refclk(),
|
.xgmctrl(),
|
.xgmctrl(),
|
.xgmdatain()
|
.xgmdatain()
|
);
|
);
|
defparam
|
defparam
|
nl10l.allow_polarity_inversion = "false",
|
nl00l.allow_polarity_inversion = "false",
|
nl10l.bitslip_enable = "false",
|
nl00l.bitslip_enable = "false",
|
nl10l.channel_bonding = "none",
|
nl00l.channel_bonding = "none",
|
nl10l.channel_number = 0,
|
nl00l.channel_number = 0,
|
nl10l.channel_width = 8,
|
nl00l.channel_width = 8,
|
nl10l.core_clock_0ppm = "false",
|
nl00l.core_clock_0ppm = "false",
|
nl10l.datapath_low_latency_mode = "false",
|
nl00l.datapath_low_latency_mode = "false",
|
nl10l.datapath_protocol = "basic",
|
nl00l.datapath_protocol = "basic",
|
nl10l.disable_ph_low_latency_mode = "false",
|
nl00l.disable_ph_low_latency_mode = "false",
|
nl10l.disparity_mode = "none",
|
nl00l.disparity_mode = "none",
|
nl10l.dprio_config_mode = 6'h01,
|
nl00l.dprio_config_mode = 6'h01,
|
nl10l.elec_idle_delay = 6,
|
nl00l.elec_idle_delay = 6,
|
nl10l.enable_bit_reversal = "false",
|
nl00l.enable_bit_reversal = "false",
|
nl10l.enable_idle_selection = "true",
|
nl00l.enable_idle_selection = "true",
|
nl10l.enable_reverse_parallel_loopback = "false",
|
nl00l.enable_reverse_parallel_loopback = "false",
|
nl10l.enable_self_test_mode = "false",
|
nl00l.enable_self_test_mode = "false",
|
nl10l.enc_8b_10b_compatibility_mode = "true",
|
nl00l.enc_8b_10b_compatibility_mode = "true",
|
nl10l.enc_8b_10b_mode = "normal",
|
nl00l.enc_8b_10b_mode = "normal",
|
nl10l.hip_enable = "false",
|
nl00l.hip_enable = "false",
|
nl10l.lpm_type = "cycloneiv_hssi_tx_pcs",
|
nl00l.lpm_type = "cycloneiv_hssi_tx_pcs",
|
nl10l.ph_fifo_reg_mode = "false",
|
nl00l.ph_fifo_reg_mode = "false",
|
nl10l.prbs_cid_pattern = "false",
|
nl00l.prbs_cid_pattern = "false",
|
nl10l.protocol_hint = "gige",
|
nl00l.protocol_hint = "gige",
|
nl10l.refclk_select = "local",
|
nl00l.refclk_select = "local",
|
nl10l.self_test_mode = "incremental",
|
nl00l.self_test_mode = "incremental",
|
nl10l.use_double_data_mode = "false",
|
nl00l.use_double_data_mode = "false",
|
nl10l.wr_clk_mux_select = "core_clk";
|
nl00l.wr_clk_mux_select = "core_clk";
|
cycloneiv_hssi_tx_pma nl10i
|
cycloneiv_hssi_tx_pma nl00i
|
(
|
(
|
.cgbpowerdn(wire_nl1il_txdividerpowerdown[0]),
|
.cgbpowerdn(wire_nl0il_txdividerpowerdown[0]),
|
.clockout(wire_nl10i_clockout),
|
.clockout(wire_nl00i_clockout),
|
.datain({wire_nl10l_dataout[9:0]}),
|
.datain({wire_nl00l_dataout[9:0]}),
|
.dataout(wire_nl10i_dataout),
|
.dataout(wire_nl00i_dataout),
|
.detectrxpowerdown(wire_nl1il_txdetectrxpowerdown[0]),
|
.detectrxpowerdown(wire_nl0il_txdetectrxpowerdown[0]),
|
.diagnosticlpbkin(wire_nl10O_diagnosticlpbkout),
|
.diagnosticlpbkin(wire_nl00O_diagnosticlpbkout),
|
.dpriodisable(wire_nl1il_dpriodisableout),
|
.dpriodisable(wire_nl0il_dpriodisableout),
|
.dprioin({wire_nl1il_txpmadprioout[299:0]}),
|
.dprioin({wire_nl0il_txpmadprioout[299:0]}),
|
.dprioout(wire_nl10i_dprioout),
|
.dprioout(wire_nl00i_dprioout),
|
.fastrefclk0in(wire_nl11O_clk[0]),
|
.fastrefclk0in(wire_nl01O_clk[0]),
|
.forceelecidle(1'b0),
|
.forceelecidle(1'b0),
|
.powerdn(wire_nl1il_txobpowerdown[0]),
|
.powerdn(wire_nl0il_txobpowerdown[0]),
|
.refclk0in(wire_nl11O_clk[1]),
|
.refclk0in(wire_nl01O_clk[1]),
|
.refclk0inpulse(wire_nl11O_clk[2]),
|
.refclk0inpulse(wire_nl01O_clk[2]),
|
.reverselpbkin(wire_nl10O_reverselpbkout),
|
.reverselpbkin(wire_nl00O_reverselpbkout),
|
.rxdetecten(wire_nl10l_txdetectrx),
|
.rxdetecten(wire_nl00l_txdetectrx),
|
.rxdetectvalidout(),
|
.rxdetectvalidout(),
|
.rxfoundout(),
|
.rxfoundout(),
|
.seriallpbkout(wire_nl10i_seriallpbkout),
|
.seriallpbkout(wire_nl00i_seriallpbkout),
|
.txpmareset(wire_nl1il_txanalogresetout[0]),
|
.txpmareset(wire_nl0il_txanalogresetout[0]),
|
.rxdetectclk()
|
.rxdetectclk()
|
);
|
);
|
defparam
|
defparam
|
nl10i.channel_number = 0,
|
nl00i.channel_number = 0,
|
nl10i.common_mode = "0.65V",
|
nl00i.common_mode = "0.65V",
|
nl10i.dprio_config_mode = 6'h01,
|
nl00i.dprio_config_mode = 6'h01,
|
nl10i.effective_data_rate = "1250.0 Mbps",
|
nl00i.effective_data_rate = "1250.0 Mbps",
|
nl10i.enable_diagnostic_loopback = "false",
|
nl00i.enable_diagnostic_loopback = "false",
|
nl10i.enable_reverse_serial_loopback = "false",
|
nl00i.enable_reverse_serial_loopback = "false",
|
nl10i.logical_channel_address = 0,
|
nl00i.logical_channel_address = 0,
|
nl10i.lpm_type = "cycloneiv_hssi_tx_pma",
|
nl00i.lpm_type = "cycloneiv_hssi_tx_pma",
|
nl10i.preemp_tap_1 = 1,
|
nl00i.preemp_tap_1 = 1,
|
nl10i.protocol_hint = "gige",
|
nl00i.protocol_hint = "gige",
|
nl10i.rx_detect = 0,
|
nl00i.rx_detect = 0,
|
nl10i.serialization_factor = 10,
|
nl00i.serialization_factor = 10,
|
nl10i.slew_rate = "medium",
|
nl00i.slew_rate = "medium",
|
nl10i.termination = "OCT 100 Ohms",
|
nl00i.termination = "OCT 100 Ohms",
|
nl10i.use_external_termination = "false",
|
nl00i.use_external_termination = "false",
|
nl10i.use_rx_detect = "false",
|
nl00i.use_rx_detect = "false",
|
nl10i.vod_selection = 1;
|
nl00i.vod_selection = 1;
|
initial
|
initial
|
nli00Oi61 = 0;
|
nli000i55 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00Oi61 <= nli00Oi62;
|
nli000i55 <= nli000i56;
|
event nli00Oi61_event;
|
event nli000i55_event;
|
initial
|
initial
|
#1 ->nli00Oi61_event;
|
#1 ->nli000i55_event;
|
always @(nli00Oi61_event)
|
always @(nli000i55_event)
|
nli00Oi61 <= {1{1'b1}};
|
nli000i55 <= {1{1'b1}};
|
initial
|
initial
|
nli00Oi62 = 0;
|
nli000i56 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00Oi62 <= nli00Oi61;
|
nli000i56 <= nli000i55;
|
initial
|
initial
|
nli00Ol59 = 0;
|
nli001O57 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00Ol59 <= nli00Ol60;
|
nli001O57 <= nli001O58;
|
event nli00Ol59_event;
|
event nli001O57_event;
|
initial
|
initial
|
#1 ->nli00Ol59_event;
|
#1 ->nli001O57_event;
|
always @(nli00Ol59_event)
|
always @(nli001O57_event)
|
nli00Ol59 <= {1{1'b1}};
|
nli001O57 <= {1{1'b1}};
|
initial
|
initial
|
nli00Ol60 = 0;
|
nli001O58 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00Ol60 <= nli00Ol59;
|
nli001O58 <= nli001O57;
|
initial
|
initial
|
nli00OO57 = 0;
|
nli010i59 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00OO57 <= nli00OO58;
|
nli010i59 <= nli010i60;
|
event nli00OO57_event;
|
event nli010i59_event;
|
initial
|
initial
|
#1 ->nli00OO57_event;
|
#1 ->nli010i59_event;
|
always @(nli00OO57_event)
|
always @(nli010i59_event)
|
nli00OO57 <= {1{1'b1}};
|
nli010i59 <= {1{1'b1}};
|
initial
|
initial
|
nli00OO58 = 0;
|
nli010i60 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli00OO58 <= nli00OO57;
|
nli010i60 <= nli010i59;
|
initial
|
initial
|
nli010l71 = 0;
|
nli011l63 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli010l71 <= nli010l72;
|
nli011l63 <= nli011l64;
|
event nli010l71_event;
|
event nli011l63_event;
|
initial
|
initial
|
#1 ->nli010l71_event;
|
#1 ->nli011l63_event;
|
always @(nli010l71_event)
|
always @(nli011l63_event)
|
nli010l71 <= {1{1'b1}};
|
nli011l63 <= {1{1'b1}};
|
initial
|
initial
|
nli010l72 = 0;
|
nli011l64 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli010l72 <= nli010l71;
|
nli011l64 <= nli011l63;
|
initial
|
initial
|
nli010O69 = 0;
|
nli011O61 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli010O69 <= nli010O70;
|
nli011O61 <= nli011O62;
|
event nli010O69_event;
|
event nli011O61_event;
|
initial
|
initial
|
#1 ->nli010O69_event;
|
#1 ->nli011O61_event;
|
always @(nli010O69_event)
|
always @(nli011O61_event)
|
nli010O69 <= {1{1'b1}};
|
nli011O61 <= {1{1'b1}};
|
initial
|
initial
|
nli010O70 = 0;
|
nli011O62 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli010O70 <= nli010O69;
|
nli011O62 <= nli011O61;
|
initial
|
initial
|
nli011i73 = 0;
|
nli0l0i53 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli011i73 <= nli011i74;
|
nli0l0i53 <= nli0l0i54;
|
event nli011i73_event;
|
event nli0l0i53_event;
|
initial
|
initial
|
#1 ->nli011i73_event;
|
#1 ->nli0l0i53_event;
|
always @(nli011i73_event)
|
always @(nli0l0i53_event)
|
nli011i73 <= {1{1'b1}};
|
nli0l0i53 <= {1{1'b1}};
|
initial
|
initial
|
nli011i74 = 0;
|
nli0l0i54 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli011i74 <= nli011i73;
|
nli0l0i54 <= nli0l0i53;
|
initial
|
initial
|
nli01li67 = 0;
|
nli0lii51 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01li67 <= nli01li68;
|
nli0lii51 <= nli0lii52;
|
event nli01li67_event;
|
event nli0lii51_event;
|
initial
|
initial
|
#1 ->nli01li67_event;
|
#1 ->nli0lii51_event;
|
always @(nli01li67_event)
|
always @(nli0lii51_event)
|
nli01li67 <= {1{1'b1}};
|
nli0lii51 <= {1{1'b1}};
|
initial
|
initial
|
nli01li68 = 0;
|
nli0lii52 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01li68 <= nli01li67;
|
nli0lii52 <= nli0lii51;
|
initial
|
initial
|
nli01ll65 = 0;
|
nli0liO49 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01ll65 <= nli01ll66;
|
nli0liO49 <= nli0liO50;
|
event nli01ll65_event;
|
event nli0liO49_event;
|
initial
|
initial
|
#1 ->nli01ll65_event;
|
#1 ->nli0liO49_event;
|
always @(nli01ll65_event)
|
always @(nli0liO49_event)
|
nli01ll65 <= {1{1'b1}};
|
nli0liO49 <= {1{1'b1}};
|
initial
|
initial
|
nli01ll66 = 0;
|
nli0liO50 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01ll66 <= nli01ll65;
|
nli0liO50 <= nli0liO49;
|
initial
|
initial
|
nli01Ol63 = 0;
|
nli0lll47 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01Ol63 <= nli01Ol64;
|
nli0lll47 <= nli0lll48;
|
event nli01Ol63_event;
|
event nli0lll47_event;
|
initial
|
initial
|
#1 ->nli01Ol63_event;
|
#1 ->nli0lll47_event;
|
always @(nli01Ol63_event)
|
always @(nli0lll47_event)
|
nli01Ol63 <= {1{1'b1}};
|
nli0lll47 <= {1{1'b1}};
|
initial
|
initial
|
nli01Ol64 = 0;
|
nli0lll48 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli01Ol64 <= nli01Ol63;
|
nli0lll48 <= nli0lll47;
|
initial
|
initial
|
nli0iOO55 = 0;
|
nli0lOi45 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0iOO55 <= nli0iOO56;
|
nli0lOi45 <= nli0lOi46;
|
event nli0iOO55_event;
|
event nli0lOi45_event;
|
initial
|
initial
|
#1 ->nli0iOO55_event;
|
#1 ->nli0lOi45_event;
|
always @(nli0iOO55_event)
|
always @(nli0lOi45_event)
|
nli0iOO55 <= {1{1'b1}};
|
nli0lOi45 <= {1{1'b1}};
|
initial
|
initial
|
nli0iOO56 = 0;
|
nli0lOi46 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0iOO56 <= nli0iOO55;
|
nli0lOi46 <= nli0lOi45;
|
initial
|
initial
|
nli0llO53 = 0;
|
nli0O0i41 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0llO53 <= nli0llO54;
|
nli0O0i41 <= nli0O0i42;
|
event nli0llO53_event;
|
event nli0O0i41_event;
|
initial
|
initial
|
#1 ->nli0llO53_event;
|
#1 ->nli0O0i41_event;
|
always @(nli0llO53_event)
|
always @(nli0O0i41_event)
|
nli0llO53 <= {1{1'b1}};
|
nli0O0i41 <= {1{1'b1}};
|
initial
|
initial
|
nli0llO54 = 0;
|
nli0O0i42 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0llO54 <= nli0llO53;
|
nli0O0i42 <= nli0O0i41;
|
initial
|
initial
|
nli0lOO51 = 0;
|
nli0O1l43 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0lOO51 <= nli0lOO52;
|
nli0O1l43 <= nli0O1l44;
|
event nli0lOO51_event;
|
event nli0O1l43_event;
|
initial
|
initial
|
#1 ->nli0lOO51_event;
|
#1 ->nli0O1l43_event;
|
always @(nli0lOO51_event)
|
always @(nli0O1l43_event)
|
nli0lOO51 <= {1{1'b1}};
|
nli0O1l43 <= {1{1'b1}};
|
initial
|
initial
|
nli0lOO52 = 0;
|
nli0O1l44 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0lOO52 <= nli0lOO51;
|
nli0O1l44 <= nli0O1l43;
|
initial
|
initial
|
nli0O0i47 = 0;
|
nli0Oii39 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0O0i47 <= nli0O0i48;
|
nli0Oii39 <= nli0Oii40;
|
event nli0O0i47_event;
|
event nli0Oii39_event;
|
initial
|
initial
|
#1 ->nli0O0i47_event;
|
#1 ->nli0Oii39_event;
|
always @(nli0O0i47_event)
|
always @(nli0Oii39_event)
|
nli0O0i47 <= {1{1'b1}};
|
nli0Oii39 <= {1{1'b1}};
|
initial
|
initial
|
nli0O0i48 = 0;
|
nli0Oii40 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0O0i48 <= nli0O0i47;
|
nli0Oii40 <= nli0Oii39;
|
initial
|
initial
|
nli0O1l49 = 0;
|
nli0OiO37 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0O1l49 <= nli0O1l50;
|
nli0OiO37 <= nli0OiO38;
|
event nli0O1l49_event;
|
event nli0OiO37_event;
|
initial
|
initial
|
#1 ->nli0O1l49_event;
|
#1 ->nli0OiO37_event;
|
always @(nli0O1l49_event)
|
always @(nli0OiO37_event)
|
nli0O1l49 <= {1{1'b1}};
|
nli0OiO37 <= {1{1'b1}};
|
initial
|
initial
|
nli0O1l50 = 0;
|
nli0OiO38 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0O1l50 <= nli0O1l49;
|
nli0OiO38 <= nli0OiO37;
|
initial
|
initial
|
nli0Oii45 = 0;
|
nli0OlO35 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0Oii45 <= nli0Oii46;
|
nli0OlO35 <= nli0OlO36;
|
event nli0Oii45_event;
|
event nli0OlO35_event;
|
initial
|
initial
|
#1 ->nli0Oii45_event;
|
#1 ->nli0OlO35_event;
|
always @(nli0Oii45_event)
|
always @(nli0OlO35_event)
|
nli0Oii45 <= {1{1'b1}};
|
nli0OlO35 <= {1{1'b1}};
|
initial
|
initial
|
nli0Oii46 = 0;
|
nli0OlO36 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0Oii46 <= nli0Oii45;
|
nli0OlO36 <= nli0OlO35;
|
initial
|
initial
|
nli0Oli43 = 0;
|
nli0OOl33 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0Oli43 <= nli0Oli44;
|
nli0OOl33 <= nli0OOl34;
|
event nli0Oli43_event;
|
event nli0OOl33_event;
|
initial
|
initial
|
#1 ->nli0Oli43_event;
|
#1 ->nli0OOl33_event;
|
always @(nli0Oli43_event)
|
always @(nli0OOl33_event)
|
nli0Oli43 <= {1{1'b1}};
|
nli0OOl33 <= {1{1'b1}};
|
initial
|
initial
|
nli0Oli44 = 0;
|
nli0OOl34 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0Oli44 <= nli0Oli43;
|
nli0OOl34 <= nli0OOl33;
|
initial
|
initial
|
nli0OlO41 = 0;
|
nli1llO79 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0OlO41 <= nli0OlO42;
|
nli1llO79 <= nli1llO80;
|
event nli0OlO41_event;
|
event nli1llO79_event;
|
initial
|
initial
|
#1 ->nli0OlO41_event;
|
#1 ->nli1llO79_event;
|
always @(nli0OlO41_event)
|
always @(nli1llO79_event)
|
nli0OlO41 <= {1{1'b1}};
|
nli1llO79 <= {1{1'b1}};
|
initial
|
initial
|
nli0OlO42 = 0;
|
nli1llO80 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0OlO42 <= nli0OlO41;
|
nli1llO80 <= nli1llO79;
|
initial
|
initial
|
nli0OOO39 = 0;
|
nli1lOi77 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0OOO39 <= nli0OOO40;
|
nli1lOi77 <= nli1lOi78;
|
event nli0OOO39_event;
|
event nli1lOi77_event;
|
initial
|
initial
|
#1 ->nli0OOO39_event;
|
#1 ->nli1lOi77_event;
|
always @(nli0OOO39_event)
|
always @(nli1lOi77_event)
|
nli0OOO39 <= {1{1'b1}};
|
nli1lOi77 <= {1{1'b1}};
|
initial
|
initial
|
nli0OOO40 = 0;
|
nli1lOi78 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli0OOO40 <= nli0OOO39;
|
nli1lOi78 <= nli1lOi77;
|
initial
|
initial
|
nli1OiO79 = 0;
|
nli1O0O75 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1OiO79 <= nli1OiO80;
|
nli1O0O75 <= nli1O0O76;
|
event nli1OiO79_event;
|
event nli1O0O75_event;
|
initial
|
initial
|
#1 ->nli1OiO79_event;
|
#1 ->nli1O0O75_event;
|
always @(nli1OiO79_event)
|
always @(nli1O0O75_event)
|
nli1OiO79 <= {1{1'b1}};
|
nli1O0O75 <= {1{1'b1}};
|
initial
|
initial
|
nli1OiO80 = 0;
|
nli1O0O76 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1OiO80 <= nli1OiO79;
|
nli1O0O76 <= nli1O0O75;
|
initial
|
initial
|
nli1Oli77 = 0;
|
nli1Oii73 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1Oli77 <= nli1Oli78;
|
nli1Oii73 <= nli1Oii74;
|
event nli1Oli77_event;
|
event nli1Oii73_event;
|
initial
|
initial
|
#1 ->nli1Oli77_event;
|
#1 ->nli1Oii73_event;
|
always @(nli1Oli77_event)
|
always @(nli1Oii73_event)
|
nli1Oli77 <= {1{1'b1}};
|
nli1Oii73 <= {1{1'b1}};
|
initial
|
initial
|
nli1Oli78 = 0;
|
nli1Oii74 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1Oli78 <= nli1Oli77;
|
nli1Oii74 <= nli1Oii73;
|
initial
|
initial
|
nli1OOO75 = 0;
|
nli1Oil71 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1OOO75 <= nli1OOO76;
|
nli1Oil71 <= nli1Oil72;
|
event nli1OOO75_event;
|
event nli1Oil71_event;
|
initial
|
initial
|
#1 ->nli1OOO75_event;
|
#1 ->nli1Oil71_event;
|
always @(nli1OOO75_event)
|
always @(nli1Oil71_event)
|
nli1OOO75 <= {1{1'b1}};
|
nli1Oil71 <= {1{1'b1}};
|
initial
|
initial
|
nli1OOO76 = 0;
|
nli1Oil72 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nli1OOO76 <= nli1OOO75;
|
nli1Oil72 <= nli1Oil71;
|
initial
|
initial
|
nlii00i23 = 0;
|
nli1OlO69 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii00i23 <= nlii00i24;
|
nli1OlO69 <= nli1OlO70;
|
event nlii00i23_event;
|
event nli1OlO69_event;
|
initial
|
initial
|
#1 ->nlii00i23_event;
|
#1 ->nli1OlO69_event;
|
always @(nlii00i23_event)
|
always @(nli1OlO69_event)
|
nlii00i23 <= {1{1'b1}};
|
nli1OlO69 <= {1{1'b1}};
|
initial
|
initial
|
nlii00i24 = 0;
|
nli1OlO70 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii00i24 <= nlii00i23;
|
nli1OlO70 <= nli1OlO69;
|
initial
|
initial
|
nlii01l25 = 0;
|
nli1OOi67 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii01l25 <= nlii01l26;
|
nli1OOi67 <= nli1OOi68;
|
event nlii01l25_event;
|
event nli1OOi67_event;
|
initial
|
initial
|
#1 ->nlii01l25_event;
|
#1 ->nli1OOi67_event;
|
always @(nlii01l25_event)
|
always @(nli1OOi67_event)
|
nlii01l25 <= {1{1'b1}};
|
nli1OOi67 <= {1{1'b1}};
|
initial
|
initial
|
nlii01l26 = 0;
|
nli1OOi68 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii01l26 <= nlii01l25;
|
nli1OOi68 <= nli1OOi67;
|
initial
|
initial
|
nlii0ii21 = 0;
|
nli1OOl65 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0ii21 <= nlii0ii22;
|
nli1OOl65 <= nli1OOl66;
|
event nlii0ii21_event;
|
event nli1OOl65_event;
|
initial
|
initial
|
#1 ->nlii0ii21_event;
|
#1 ->nli1OOl65_event;
|
always @(nlii0ii21_event)
|
always @(nli1OOl65_event)
|
nlii0ii21 <= {1{1'b1}};
|
nli1OOl65 <= {1{1'b1}};
|
initial
|
initial
|
nlii0ii22 = 0;
|
nli1OOl66 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0ii22 <= nlii0ii21;
|
nli1OOl66 <= nli1OOl65;
|
initial
|
initial
|
nlii0il19 = 0;
|
nlii00l13 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0il19 <= nlii0il20;
|
nlii00l13 <= nlii00l14;
|
event nlii0il19_event;
|
event nlii00l13_event;
|
initial
|
initial
|
#1 ->nlii0il19_event;
|
#1 ->nlii00l13_event;
|
always @(nlii0il19_event)
|
always @(nlii00l13_event)
|
nlii0il19 <= {1{1'b1}};
|
nlii00l13 <= {1{1'b1}};
|
initial
|
initial
|
nlii0il20 = 0;
|
nlii00l14 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0il20 <= nlii0il19;
|
nlii00l14 <= nlii00l13;
|
initial
|
initial
|
nlii0iO17 = 0;
|
nlii01i19 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0iO17 <= nlii0iO18;
|
nlii01i19 <= nlii01i20;
|
event nlii0iO17_event;
|
event nlii01i19_event;
|
initial
|
initial
|
#1 ->nlii0iO17_event;
|
#1 ->nlii01i19_event;
|
always @(nlii0iO17_event)
|
always @(nlii01i19_event)
|
nlii0iO17 <= {1{1'b1}};
|
nlii01i19 <= {1{1'b1}};
|
initial
|
initial
|
nlii0iO18 = 0;
|
nlii01i20 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0iO18 <= nlii0iO17;
|
nlii01i20 <= nlii01i19;
|
initial
|
initial
|
nlii0ll15 = 0;
|
nlii01l17 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0ll15 <= nlii0ll16;
|
nlii01l17 <= nlii01l18;
|
event nlii0ll15_event;
|
event nlii01l17_event;
|
initial
|
initial
|
#1 ->nlii0ll15_event;
|
#1 ->nlii01l17_event;
|
always @(nlii0ll15_event)
|
always @(nlii01l17_event)
|
nlii0ll15 <= {1{1'b1}};
|
nlii01l17 <= {1{1'b1}};
|
initial
|
initial
|
nlii0ll16 = 0;
|
nlii01l18 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0ll16 <= nlii0ll15;
|
nlii01l18 <= nlii01l17;
|
initial
|
initial
|
nlii0Ol13 = 0;
|
nlii01O15 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0Ol13 <= nlii0Ol14;
|
nlii01O15 <= nlii01O16;
|
event nlii0Ol13_event;
|
event nlii01O15_event;
|
initial
|
initial
|
#1 ->nlii0Ol13_event;
|
#1 ->nlii01O15_event;
|
always @(nlii0Ol13_event)
|
always @(nlii01O15_event)
|
nlii0Ol13 <= {1{1'b1}};
|
nlii01O15 <= {1{1'b1}};
|
initial
|
initial
|
nlii0Ol14 = 0;
|
nlii01O16 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0Ol14 <= nlii0Ol13;
|
nlii01O16 <= nlii01O15;
|
initial
|
initial
|
nlii0OO11 = 0;
|
nlii0ii11 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0OO11 <= nlii0OO12;
|
nlii0ii11 <= nlii0ii12;
|
event nlii0OO11_event;
|
event nlii0ii11_event;
|
initial
|
initial
|
#1 ->nlii0OO11_event;
|
#1 ->nlii0ii11_event;
|
always @(nlii0OO11_event)
|
always @(nlii0ii11_event)
|
nlii0OO11 <= {1{1'b1}};
|
nlii0ii11 <= {1{1'b1}};
|
initial
|
initial
|
nlii0OO12 = 0;
|
nlii0ii12 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii0OO12 <= nlii0OO11;
|
nlii0ii12 <= nlii0ii11;
|
initial
|
initial
|
nlii10l35 = 0;
|
nlii0il10 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii10l35 <= nlii10l36;
|
nlii0il10 <= nlii0il9;
|
event nlii10l35_event;
|
initial
|
initial
|
nlii0il9 = 0;
|
#1 ->nlii10l35_event;
|
always @ ( posedge wire_nl0ii_clkout)
|
always @(nlii10l35_event)
|
nlii0il9 <= nlii0il10;
|
nlii10l35 <= {1{1'b1}};
|
event nlii0il9_event;
|
initial
|
initial
|
nlii10l36 = 0;
|
#1 ->nlii0il9_event;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @(nlii0il9_event)
|
nlii10l36 <= nlii10l35;
|
nlii0il9 <= {1{1'b1}};
|
initial
|
initial
|
nlii11O37 = 0;
|
nlii0Oi7 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii11O37 <= nlii11O38;
|
nlii0Oi7 <= nlii0Oi8;
|
event nlii11O37_event;
|
event nlii0Oi7_event;
|
initial
|
initial
|
#1 ->nlii11O37_event;
|
#1 ->nlii0Oi7_event;
|
always @(nlii11O37_event)
|
always @(nlii0Oi7_event)
|
nlii11O37 <= {1{1'b1}};
|
nlii0Oi7 <= {1{1'b1}};
|
initial
|
initial
|
nlii11O38 = 0;
|
nlii0Oi8 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii11O38 <= nlii11O37;
|
nlii0Oi8 <= nlii0Oi7;
|
initial
|
initial
|
nlii1il33 = 0;
|
nlii0Ol5 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1il33 <= nlii1il34;
|
nlii0Ol5 <= nlii0Ol6;
|
event nlii1il33_event;
|
event nlii0Ol5_event;
|
initial
|
initial
|
#1 ->nlii1il33_event;
|
#1 ->nlii0Ol5_event;
|
always @(nlii1il33_event)
|
always @(nlii0Ol5_event)
|
nlii1il33 <= {1{1'b1}};
|
nlii0Ol5 <= {1{1'b1}};
|
initial
|
initial
|
nlii1il34 = 0;
|
nlii0Ol6 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1il34 <= nlii1il33;
|
nlii0Ol6 <= nlii0Ol5;
|
initial
|
initial
|
nlii1li31 = 0;
|
nlii0OO3 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1li31 <= nlii1li32;
|
nlii0OO3 <= nlii0OO4;
|
event nlii1li31_event;
|
event nlii0OO3_event;
|
initial
|
initial
|
#1 ->nlii1li31_event;
|
#1 ->nlii0OO3_event;
|
always @(nlii1li31_event)
|
always @(nlii0OO3_event)
|
nlii1li31 <= {1{1'b1}};
|
nlii0OO3 <= {1{1'b1}};
|
initial
|
initial
|
nlii1li32 = 0;
|
nlii0OO4 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1li32 <= nlii1li31;
|
nlii0OO4 <= nlii0OO3;
|
initial
|
initial
|
nlii1lO29 = 0;
|
nlii10i29 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1lO29 <= nlii1lO30;
|
nlii10i29 <= nlii10i30;
|
event nlii1lO29_event;
|
event nlii10i29_event;
|
initial
|
initial
|
#1 ->nlii1lO29_event;
|
#1 ->nlii10i29_event;
|
always @(nlii1lO29_event)
|
always @(nlii10i29_event)
|
nlii1lO29 <= {1{1'b1}};
|
nlii10i29 <= {1{1'b1}};
|
initial
|
initial
|
nlii1lO30 = 0;
|
nlii10i30 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1lO30 <= nlii1lO29;
|
nlii10i30 <= nlii10i29;
|
initial
|
initial
|
nlii1OO27 = 0;
|
nlii10O27 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1OO27 <= nlii1OO28;
|
nlii10O27 <= nlii10O28;
|
event nlii1OO27_event;
|
event nlii10O27_event;
|
initial
|
initial
|
#1 ->nlii1OO27_event;
|
#1 ->nlii10O27_event;
|
always @(nlii1OO27_event)
|
always @(nlii10O27_event)
|
nlii1OO27 <= {1{1'b1}};
|
nlii10O27 <= {1{1'b1}};
|
initial
|
initial
|
nlii1OO28 = 0;
|
nlii10O28 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nlii1OO28 <= nlii1OO27;
|
nlii10O28 <= nlii10O27;
|
initial
|
initial
|
nliii0O7 = 0;
|
nlii11l31 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliii0O7 <= nliii0O8;
|
nlii11l31 <= nlii11l32;
|
event nliii0O7_event;
|
event nlii11l31_event;
|
initial
|
initial
|
#1 ->nliii0O7_event;
|
#1 ->nlii11l31_event;
|
always @(nliii0O7_event)
|
always @(nlii11l31_event)
|
nliii0O7 <= {1{1'b1}};
|
nlii11l31 <= {1{1'b1}};
|
initial
|
initial
|
nliii0O8 = 0;
|
nlii11l32 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliii0O8 <= nliii0O7;
|
nlii11l32 <= nlii11l31;
|
initial
|
initial
|
nliii1i10 = 0;
|
nlii1iO25 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliii1i10 <= nliii1i9;
|
nlii1iO25 <= nlii1iO26;
|
initial
|
event nlii1iO25_event;
|
nliii1i9 = 0;
|
initial
|
always @ ( posedge wire_nl1ii_clkout)
|
#1 ->nlii1iO25_event;
|
nliii1i9 <= nliii1i10;
|
always @(nlii1iO25_event)
|
event nliii1i9_event;
|
nlii1iO25 <= {1{1'b1}};
|
initial
|
initial
|
#1 ->nliii1i9_event;
|
nlii1iO26 = 0;
|
always @(nliii1i9_event)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliii1i9 <= {1{1'b1}};
|
nlii1iO26 <= nlii1iO25;
|
initial
|
initial
|
nliiiii5 = 0;
|
nlii1ll23 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiiii5 <= nliiiii6;
|
nlii1ll23 <= nlii1ll24;
|
event nliiiii5_event;
|
event nlii1ll23_event;
|
initial
|
initial
|
#1 ->nliiiii5_event;
|
#1 ->nlii1ll23_event;
|
always @(nliiiii5_event)
|
always @(nlii1ll23_event)
|
nliiiii5 <= {1{1'b1}};
|
nlii1ll23 <= {1{1'b1}};
|
initial
|
initial
|
nliiiii6 = 0;
|
nlii1ll24 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiiii6 <= nliiiii5;
|
nlii1ll24 <= nlii1ll23;
|
initial
|
initial
|
nliiiil3 = 0;
|
nlii1Ol21 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiiil3 <= nliiiil4;
|
nlii1Ol21 <= nlii1Ol22;
|
event nliiiil3_event;
|
event nlii1Ol21_event;
|
initial
|
initial
|
#1 ->nliiiil3_event;
|
#1 ->nlii1Ol21_event;
|
always @(nliiiil3_event)
|
always @(nlii1Ol21_event)
|
nliiiil3 <= {1{1'b1}};
|
nlii1Ol21 <= {1{1'b1}};
|
initial
|
initial
|
nliiiil4 = 0;
|
nlii1Ol22 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiiil4 <= nliiiil3;
|
nlii1Ol22 <= nlii1Ol21;
|
initial
|
initial
|
nliiili1 = 0;
|
nliii1l1 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiili1 <= nliiili2;
|
nliii1l1 <= nliii1l2;
|
event nliiili1_event;
|
event nliii1l1_event;
|
initial
|
initial
|
#1 ->nliiili1_event;
|
#1 ->nliii1l1_event;
|
always @(nliiili1_event)
|
always @(nliii1l1_event)
|
nliiili1 <= {1{1'b1}};
|
nliii1l1 <= {1{1'b1}};
|
initial
|
initial
|
nliiili2 = 0;
|
nliii1l2 = 0;
|
always @ ( posedge wire_nl1ii_clkout)
|
always @ ( posedge wire_nl0ii_clkout)
|
nliiili2 <= nliiili1;
|
nliii1l2 <= nliii1l1;
|
initial
|
initial
|
begin
|
begin
|
n000l = 0;
|
n00iO = 0;
|
n00ii = 0;
|
n011l = 0;
|
|
n011O = 0;
|
|
n01ll = 0;
|
|
n01Ol = 0;
|
|
n01OO = 0;
|
|
n10ii = 0;
|
|
n10il = 0;
|
|
n11OO = 0;
|
|
n1i1l = 0;
|
|
n1l1i = 0;
|
|
n1O0i = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or negedge wire_n000O_PRN)
|
always @ ( posedge clk or posedge n110l)
|
begin
|
begin
|
if (wire_n000O_PRN == 1'b0)
|
if (n110l == 1'b1)
|
begin
|
begin
|
n000l <= 1;
|
n00iO <= 1;
|
n00ii <= 1;
|
n011l <= 1;
|
|
n011O <= 1;
|
|
n01ll <= 1;
|
|
n01Ol <= 1;
|
|
n01OO <= 1;
|
|
n10ii <= 1;
|
|
n10il <= 1;
|
|
n11OO <= 1;
|
|
n1i1l <= 1;
|
|
n1l1i <= 1;
|
|
n1O0i <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n000l <= n00ii;
|
n00iO <= wire_n001i_dataout;
|
n00ii <= nlii0Oi;
|
n011l <= wire_n010l_dataout;
|
|
n011O <= wire_n010O_dataout;
|
|
n01ll <= wire_n010i_dataout;
|
|
n01Ol <= wire_n001l_dataout;
|
|
n01OO <= wire_n001O_dataout;
|
|
n10ii <= wire_n101l_dataout;
|
|
n10il <= nli000l;
|
|
n11OO <= wire_n101O_dataout;
|
|
n1i1l <= nli00ii;
|
|
n1l1i <= nli00li;
|
|
n1O0i <= nli00Oi;
|
|
end
|
|
end
|
|
initial
|
|
begin
|
|
n00ll = 0;
|
|
n01lO = 0;
|
|
n101i = 0;
|
|
n10lO = 0;
|
|
n1i0O = 0;
|
|
n1iiO = 0;
|
|
n1ill = 0;
|
|
n1iOO = 0;
|
|
n1l0O = 0;
|
|
n1lii = 0;
|
|
n1llO = 0;
|
|
n1O1i = 0;
|
|
n1O1l = 0;
|
|
n1O1O = 0;
|
|
n1Oll = 0;
|
|
n1OlO = 0;
|
|
end
|
|
always @ ( posedge clk or posedge n110l)
|
|
begin
|
|
if (n110l == 1'b1)
|
|
begin
|
|
n00ll <= 0;
|
|
n01lO <= 0;
|
|
n101i <= 0;
|
|
n10lO <= 0;
|
|
n1i0O <= 0;
|
|
n1iiO <= 0;
|
|
n1ill <= 0;
|
|
n1iOO <= 0;
|
|
n1l0O <= 0;
|
|
n1lii <= 0;
|
|
n1llO <= 0;
|
|
n1O1i <= 0;
|
|
n1O1l <= 0;
|
|
n1O1O <= 0;
|
|
n1Oll <= 0;
|
|
n1OlO <= 0;
|
|
end
|
|
else
|
|
begin
|
|
n00ll <= nli0i1O;
|
|
n01lO <= nlii00i;
|
|
n101i <= ((~ nli000O) & (((~ nli000l) & n10il) | n101i));
|
|
n10lO <= nlii00i;
|
|
n1i0O <= nlii00i;
|
|
n1iiO <= ((~ nli00il) & (n1iiO | ((~ nli00ii) & n1i1l)));
|
|
n1ill <= wire_n1l1l_dataout;
|
|
n1iOO <= wire_n1l1O_dataout;
|
|
n1l0O <= nlii00i;
|
|
n1lii <= ((~ nli00ll) & (n1lii | ((~ nli00li) & n1l1i)));
|
|
n1llO <= wire_n1O0l_dataout;
|
|
n1O1i <= wire_n1O0O_dataout;
|
|
n1O1l <= wire_n1Oii_dataout;
|
|
n1O1O <= wire_n1Oil_dataout;
|
|
n1Oll <= nli0i0l;
|
|
n1OlO <= ((~ nli00Ol) & (n1OlO | ((~ nli00Oi) & n1O0i)));
|
end
|
end
|
end
|
end
|
assign
|
|
wire_n000O_PRN = ((nli0iOO56 ^ nli0iOO55) & (~ nli0l1i));
|
|
event n000l_event;
|
|
event n00ii_event;
|
|
initial
|
|
#1 ->n000l_event;
|
|
initial
|
|
#1 ->n00ii_event;
|
|
always @(n000l_event)
|
|
n000l <= 1;
|
|
always @(n00ii_event)
|
|
n00ii <= 1;
|
|
initial
|
initial
|
begin
|
begin
|
n00Oii = 0;
|
n00Oii = 0;
|
n00Oll = 0;
|
n00Oll = 0;
|
n00OOl = 0;
|
n00OOl = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge n0O0Oi)
|
always @ ( posedge wire_nl0ii_clkout or posedge n0O0Oi)
|
begin
|
begin
|
if (n0O0Oi == 1'b1)
|
if (n0O0Oi == 1'b1)
|
begin
|
begin
|
n00Oii <= 1;
|
n00Oii <= 1;
|
n00Oll <= 1;
|
n00Oll <= 1;
|
| Line 4226... |
Line 4325... |
n00Oll <= 1;
|
n00Oll <= 1;
|
always @(n00OOl_event)
|
always @(n00OOl_event)
|
n00OOl <= 1;
|
n00OOl <= 1;
|
initial
|
initial
|
begin
|
begin
|
n01l0l = 0;
|
n01iil = 0;
|
n01l1O = 0;
|
n01ili = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge nlilOl)
|
always @ ( posedge wire_nl0ii_clkout or posedge nlilOl)
|
begin
|
begin
|
if (nlilOl == 1'b1)
|
if (nlilOl == 1'b1)
|
begin
|
begin
|
n01l0l <= 1;
|
n01iil <= 1;
|
n01l1O <= 1;
|
n01ili <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n01l0l <= nlii0Oi;
|
n01iil <= n01ili;
|
n01l1O <= n01l0l;
|
n01ili <= nlii0iO;
|
end
|
end
|
end
|
end
|
event n01l0l_event;
|
event n01iil_event;
|
event n01l1O_event;
|
event n01ili_event;
|
initial
|
|
#1 ->n01l0l_event;
|
|
initial
|
initial
|
#1 ->n01l1O_event;
|
#1 ->n01iil_event;
|
always @(n01l0l_event)
|
|
n01l0l <= 1;
|
|
always @(n01l1O_event)
|
|
n01l1O <= 1;
|
|
initial
|
initial
|
begin
|
#1 ->n01ili_event;
|
n011i = 0;
|
always @(n01iil_event)
|
n01iO = 0;
|
n01iil <= 1;
|
n01ll = 0;
|
always @(n01ili_event)
|
n101l = 0;
|
n01ili <= 1;
|
n10ii = 0;
|
|
n10ll = 0;
|
|
n10Ol = 0;
|
|
n110l = 0;
|
|
n110O = 0;
|
|
n11lO = 0;
|
|
n11Oi = 0;
|
|
n1i0l = 0;
|
|
n1i0O = 0;
|
|
n1i1i = 0;
|
|
n1ill = 0;
|
|
n1ilO = 0;
|
|
n1l0i = 0;
|
|
n1l0l = 0;
|
|
n1l0O = 0;
|
|
n1l1l = 0;
|
|
n1l1O = 0;
|
|
n1lOi = 0;
|
|
n1O0i = 0;
|
|
n1O1O = 0;
|
|
n1OlO = 0;
|
|
n1OOi = 0;
|
|
n1OOO = 0;
|
|
end
|
|
always @ ( posedge clk or posedge nl0il)
|
|
begin
|
|
if (nl0il == 1'b1)
|
|
begin
|
|
n011i <= 0;
|
|
n01iO <= 0;
|
|
n01ll <= 0;
|
|
n101l <= 0;
|
|
n10ii <= 0;
|
|
n10ll <= 0;
|
|
n10Ol <= 0;
|
|
n110l <= 0;
|
|
n110O <= 0;
|
|
n11lO <= 0;
|
|
n11Oi <= 0;
|
|
n1i0l <= 0;
|
|
n1i0O <= 0;
|
|
n1i1i <= 0;
|
|
n1ill <= 0;
|
|
n1ilO <= 0;
|
|
n1l0i <= 0;
|
|
n1l0l <= 0;
|
|
n1l0O <= 0;
|
|
n1l1l <= 0;
|
|
n1l1O <= 0;
|
|
n1lOi <= 0;
|
|
n1O0i <= 0;
|
|
n1O1O <= 0;
|
|
n1OlO <= 0;
|
|
n1OOi <= 0;
|
|
n1OOO <= 0;
|
|
end
|
|
else
|
|
begin
|
|
n011i <= wire_n010i_dataout;
|
|
n01iO <= wire_n011l_dataout;
|
|
n01ll <= nlii0lO;
|
|
n101l <= nlii0lO;
|
|
n10ii <= nli0i1O;
|
|
n10ll <= nlii0lO;
|
|
n10Ol <= ((~ nli0i0i) & (n10Ol | ((~ nli0i1O) & n10ii)));
|
|
n110l <= wire_n11il_dataout;
|
|
n110O <= ((~ nli0i1l) & (((~ nli0i1i) & n11Oi) | n110O));
|
|
n11lO <= wire_n11ii_dataout;
|
|
n11Oi <= nli0i1i;
|
|
n1i0l <= wire_n1iil_dataout;
|
|
n1i0O <= nli0i0O;
|
|
n1i1i <= wire_n1iii_dataout;
|
|
n1ill <= nlii0lO;
|
|
n1ilO <= ((~ nli0iii) & (n1ilO | ((~ nli0i0O) & n1i0O)));
|
|
n1l0i <= wire_n1liO_dataout;
|
|
n1l0l <= wire_n1lli_dataout;
|
|
n1l0O <= ((nli0iOi & (~ n1lOi)) | (((~ nli0ilO) | n1l0l) & n1l0O));
|
|
n1l1l <= wire_n1lii_dataout;
|
|
n1l1O <= wire_n1lil_dataout;
|
|
n1lOi <= nli0iOi;
|
|
n1O0i <= wire_n1Oii_dataout;
|
|
n1O1O <= wire_n1O0O_dataout;
|
|
n1OlO <= wire_n1O0l_dataout;
|
|
n1OOi <= nlii0lO;
|
|
n1OOO <= wire_n011O_dataout;
|
|
end
|
|
end
|
|
initial
|
initial
|
begin
|
begin
|
n0i01l = 0;
|
n0i01l = 0;
|
n0i10i = 0;
|
n0i10i = 0;
|
n0i10l = 0;
|
n0i10l = 0;
|
| Line 4359... |
Line 4365... |
n0i1li = 0;
|
n0i1li = 0;
|
n0i1ll = 0;
|
n0i1ll = 0;
|
n0i1Ol = 0;
|
n0i1Ol = 0;
|
n0i1OO = 0;
|
n0i1OO = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge n0O0Oi)
|
always @ ( posedge wire_nl0ii_clkout or posedge n0O0Oi)
|
begin
|
begin
|
if (n0O0Oi == 1'b1)
|
if (n0O0Oi == 1'b1)
|
begin
|
begin
|
n0i01l <= 0;
|
n0i01l <= 0;
|
n0i10i <= 0;
|
n0i10i <= 0;
|
| Line 4375... |
Line 4381... |
n0i1li <= 0;
|
n0i1li <= 0;
|
n0i1ll <= 0;
|
n0i1ll <= 0;
|
n0i1Ol <= 0;
|
n0i1Ol <= 0;
|
n0i1OO <= 0;
|
n0i1OO <= 0;
|
end
|
end
|
else if (n01OiO == 1'b1)
|
else if (n01Oii == 1'b1)
|
begin
|
begin
|
n0i01l <= wire_n0i00O_dataout;
|
n0i01l <= wire_n0i00O_dataout;
|
n0i10i <= n0i1Oi;
|
n0i10i <= n0i1Oi;
|
n0i10l <= (n0i1Ol ^ n0i1Oi);
|
n0i10l <= (n0i1Ol ^ n0i1Oi);
|
n0i11i <= (n0i1OO ^ n0i1Ol);
|
n0i11i <= (n0i1OO ^ n0i1Ol);
|
| Line 4392... |
Line 4398... |
n0i1OO <= wire_n0i00l_dataout;
|
n0i1OO <= wire_n0i00l_dataout;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
|
n0i0l = 0;
|
|
n0iii = 0;
|
|
end
|
|
always @ ( posedge wire_nl0ii_clkout or posedge nli0iil)
|
|
begin
|
|
if (nli0iil == 1'b1)
|
|
begin
|
|
n0i0l <= 1;
|
|
n0iii <= 1;
|
|
end
|
|
else
|
|
begin
|
|
n0i0l <= n0iii;
|
|
n0iii <= nlii0iO;
|
|
end
|
|
end
|
|
event n0i0l_event;
|
|
event n0iii_event;
|
|
initial
|
|
#1 ->n0i0l_event;
|
|
initial
|
|
#1 ->n0iii_event;
|
|
always @(n0i0l_event)
|
|
n0i0l <= 1;
|
|
always @(n0iii_event)
|
|
n0iii <= 1;
|
|
initial
|
|
begin
|
n0i1Oi = 0;
|
n0i1Oi = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge n0O0Oi)
|
always @ ( posedge wire_nl0ii_clkout or posedge n0O0Oi)
|
begin
|
begin
|
if (n0O0Oi == 1'b1)
|
if (n0O0Oi == 1'b1)
|
begin
|
begin
|
n0i1Oi <= 1;
|
n0i1Oi <= 1;
|
end
|
end
|
else if (n01OiO == 1'b1)
|
else if (n01Oii == 1'b1)
|
begin
|
begin
|
n0i1Oi <= wire_n0i01O_dataout;
|
n0i1Oi <= wire_n0i01O_dataout;
|
end
|
end
|
end
|
end
|
event n0i1Oi_event;
|
event n0i1Oi_event;
|
| Line 4414... |
Line 4448... |
n0i1Oi <= 1;
|
n0i1Oi <= 1;
|
initial
|
initial
|
begin
|
begin
|
n0ii0O = 0;
|
n0ii0O = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0ii0O <= 1;
|
n0ii0O <= 1;
|
end
|
end
|
else if (nli1ili == 1'b1)
|
else if (nli10Oi == 1'b1)
|
begin
|
begin
|
n0ii0O <= wire_n0iilO_dataout;
|
n0ii0O <= wire_n0iilO_dataout;
|
end
|
end
|
end
|
end
|
event n0ii0O_event;
|
event n0ii0O_event;
|
| Line 4444... |
Line 4478... |
n0ii1O = 0;
|
n0ii1O = 0;
|
n0iiil = 0;
|
n0iiil = 0;
|
n0iiiO = 0;
|
n0iiiO = 0;
|
n0iill = 0;
|
n0iill = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0i0iO <= 0;
|
n0i0iO <= 0;
|
n0i0li <= 0;
|
n0i0li <= 0;
|
| Line 4460... |
Line 4494... |
n0ii1O <= 0;
|
n0ii1O <= 0;
|
n0iiil <= 0;
|
n0iiil <= 0;
|
n0iiiO <= 0;
|
n0iiiO <= 0;
|
n0iill <= 0;
|
n0iill <= 0;
|
end
|
end
|
else if (nli1ili == 1'b1)
|
else if (nli10Oi == 1'b1)
|
begin
|
begin
|
n0i0iO <= (n0iiiO ^ n0iiil);
|
n0i0iO <= (n0iiiO ^ n0iiil);
|
n0i0li <= (n0iill ^ n0iiiO);
|
n0i0li <= (n0iill ^ n0iiiO);
|
n0i0ll <= n0iill;
|
n0i0ll <= n0iill;
|
n0i0lO <= n0ii0O;
|
n0i0lO <= n0ii0O;
|
| Line 4479... |
Line 4513... |
end
|
end
|
initial
|
initial
|
begin
|
begin
|
n0iOii = 0;
|
n0iOii = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0iOii <= 0;
|
n0iOii <= 0;
|
end
|
end
|
else if (n0iO0i == 1'b0)
|
else if (n0iO0i == 1'b0)
|
begin
|
begin
|
n0iOii <= nliii0l;
|
n0iOii <= nlii0lO;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
n0iO0i = 0;
|
n0iO0i = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0iO0i <= 1;
|
n0iO0i <= 1;
|
end
|
end
|
else if (nlil01i == 1'b1)
|
else if (nlil1il == 1'b1)
|
begin
|
begin
|
n0iO0i <= wire_n0iOiO_o;
|
n0iO0i <= wire_n0iOiO_o;
|
end
|
end
|
end
|
end
|
event n0iO0i_event;
|
event n0iO0i_event;
|
| Line 4515... |
Line 4549... |
initial
|
initial
|
begin
|
begin
|
n0010i = 0;
|
n0010i = 0;
|
n0010l = 0;
|
n0010l = 0;
|
n0010O = 0;
|
n0010O = 0;
|
n0011O = 0;
|
n0011i = 0;
|
n001ii = 0;
|
n001ii = 0;
|
n001il = 0;
|
n001il = 0;
|
n001iO = 0;
|
n001iO = 0;
|
n001li = 0;
|
n001li = 0;
|
n00lOO = 0;
|
n00lOO = 0;
|
| Line 4528... |
Line 4562... |
n00O1i = 0;
|
n00O1i = 0;
|
n00Oil = 0;
|
n00Oil = 0;
|
n00OiO = 0;
|
n00OiO = 0;
|
n00Oli = 0;
|
n00Oli = 0;
|
n00OlO = 0;
|
n00OlO = 0;
|
|
n01l0l = 0;
|
|
n01l0O = 0;
|
|
n01lOi = 0;
|
|
n01lOl = 0;
|
n01lOO = 0;
|
n01lOO = 0;
|
n01O0i = 0;
|
n01O0i = 0;
|
n01O0l = 0;
|
n01O0l = 0;
|
n01O0O = 0;
|
n01O0O = 0;
|
n01O1i = 0;
|
n01O1i = 0;
|
n01O1l = 0;
|
n01O1l = 0;
|
n01O1O = 0;
|
n01O1O = 0;
|
n01Oii = 0;
|
n01Oii = 0;
|
n01Oil = 0;
|
|
n01OiO = 0;
|
n01OiO = 0;
|
n01Oli = 0;
|
|
n01OOO = 0;
|
n01OOO = 0;
|
n0ilOi = 0;
|
n0ilOi = 0;
|
n0ilOO = 0;
|
n0ilOO = 0;
|
n0iO1i = 0;
|
n0iO1i = 0;
|
n0iO1l = 0;
|
n0iO1l = 0;
|
| Line 4554... |
Line 4590... |
n0l1lO = 0;
|
n0l1lO = 0;
|
n0l1Oi = 0;
|
n0l1Oi = 0;
|
n0l1Ol = 0;
|
n0l1Ol = 0;
|
n0l1OO = 0;
|
n0l1OO = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge n0O0Oi)
|
always @ ( posedge wire_nl0ii_clkout or posedge n0O0Oi)
|
begin
|
begin
|
if (n0O0Oi == 1'b1)
|
if (n0O0Oi == 1'b1)
|
begin
|
begin
|
n0010i <= 0;
|
n0010i <= 0;
|
n0010l <= 0;
|
n0010l <= 0;
|
n0010O <= 0;
|
n0010O <= 0;
|
n0011O <= 0;
|
n0011i <= 0;
|
n001ii <= 0;
|
n001ii <= 0;
|
n001il <= 0;
|
n001il <= 0;
|
n001iO <= 0;
|
n001iO <= 0;
|
n001li <= 0;
|
n001li <= 0;
|
n00lOO <= 0;
|
n00lOO <= 0;
|
| Line 4574... |
Line 4610... |
n00O1i <= 0;
|
n00O1i <= 0;
|
n00Oil <= 0;
|
n00Oil <= 0;
|
n00OiO <= 0;
|
n00OiO <= 0;
|
n00Oli <= 0;
|
n00Oli <= 0;
|
n00OlO <= 0;
|
n00OlO <= 0;
|
|
n01l0l <= 0;
|
|
n01l0O <= 0;
|
|
n01lOi <= 0;
|
|
n01lOl <= 0;
|
n01lOO <= 0;
|
n01lOO <= 0;
|
n01O0i <= 0;
|
n01O0i <= 0;
|
n01O0l <= 0;
|
n01O0l <= 0;
|
n01O0O <= 0;
|
n01O0O <= 0;
|
n01O1i <= 0;
|
n01O1i <= 0;
|
n01O1l <= 0;
|
n01O1l <= 0;
|
n01O1O <= 0;
|
n01O1O <= 0;
|
n01Oii <= 0;
|
n01Oii <= 0;
|
n01Oil <= 0;
|
|
n01OiO <= 0;
|
n01OiO <= 0;
|
n01Oli <= 0;
|
|
n01OOO <= 0;
|
n01OOO <= 0;
|
n0ilOi <= 0;
|
n0ilOi <= 0;
|
n0ilOO <= 0;
|
n0ilOO <= 0;
|
n0iO1i <= 0;
|
n0iO1i <= 0;
|
n0iO1l <= 0;
|
n0iO1l <= 0;
|
| Line 4605... |
Line 4643... |
else
|
else
|
begin
|
begin
|
n0010i <= wire_n001lO_dataout;
|
n0010i <= wire_n001lO_dataout;
|
n0010l <= wire_n001Oi_dataout;
|
n0010l <= wire_n001Oi_dataout;
|
n0010O <= wire_n001Ol_dataout;
|
n0010O <= wire_n001Ol_dataout;
|
n0011O <= nlOil1l;
|
n0011i <= wire_n001ll_dataout;
|
n001ii <= wire_n001OO_dataout;
|
n001ii <= wire_n001OO_dataout;
|
n001il <= wire_n0001i_dataout;
|
n001il <= wire_n0001i_dataout;
|
n001iO <= wire_n0001l_dataout;
|
n001iO <= wire_n0001l_dataout;
|
n001li <= wire_n00O1l_dataout;
|
n001li <= wire_n00O1l_dataout;
|
n00lOO <= wire_n00O1O_dataout;
|
n00lOO <= wire_n00O1O_dataout;
|
| Line 4618... |
Line 4656... |
n00O1i <= wire_n00ill_o;
|
n00O1i <= wire_n00ill_o;
|
n00Oil <= n00OiO;
|
n00Oil <= n00OiO;
|
n00OiO <= nlilOl;
|
n00OiO <= nlilOl;
|
n00Oli <= n00OlO;
|
n00Oli <= n00OlO;
|
n00OlO <= nl011O;
|
n00OlO <= nl011O;
|
n01lOO <= nlOiliO;
|
n01l0l <= wire_n01lil_dataout;
|
n01O0i <= nlOilOi;
|
n01l0O <= nlOiiOi;
|
n01O0l <= nlOilOl;
|
n01lOi <= nlOil0l;
|
n01O0O <= nlOilOO;
|
n01lOl <= nlOil0O;
|
n01O1i <= nlOilli;
|
n01lOO <= nlOilii;
|
n01O1l <= nlOilll;
|
n01O0i <= nlOilll;
|
n01O1O <= nlOillO;
|
n01O0l <= nli101i;
|
n01Oii <= nlOl10l;
|
n01O0O <= (nlOiOOi | n01OOO);
|
n01Oil <= nlOl11l;
|
n01O1i <= nlOilil;
|
n01OiO <= wire_n01Oll_dataout;
|
n01O1l <= nlOiliO;
|
n01Oli <= wire_n0011i_dataout;
|
n01O1O <= nlOilli;
|
n01OOO <= wire_n001ll_dataout;
|
n01Oii <= wire_n01Oli_dataout;
|
|
n01OiO <= wire_n0011l_dataout;
|
|
n01OOO <= wire_n01lii_dataout;
|
n0ilOi <= wire_n0iO0l_o[1];
|
n0ilOi <= wire_n0iO0l_o[1];
|
n0ilOO <= wire_n0iO0l_o[2];
|
n0ilOO <= wire_n0iO0l_o[2];
|
n0iO1i <= wire_n0iO0l_o[3];
|
n0iO1i <= wire_n0iO0l_o[3];
|
n0iO1l <= wire_n0iO0l_o[4];
|
n0iO1l <= wire_n0iO0l_o[4];
|
n0l01i <= n0i0li;
|
n0l01i <= n0i0li;
|
| Line 4659... |
Line 4699... |
n0l0ll = 0;
|
n0l0ll = 0;
|
n0l11i = 0;
|
n0l11i = 0;
|
n0li0O = 0;
|
n0li0O = 0;
|
n0liil = 0;
|
n0liil = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0iOil <= 0;
|
n0iOil <= 0;
|
n0iOli <= 0;
|
n0iOli <= 0;
|
| Line 4687... |
Line 4727... |
n0iOOl <= n0i11i;
|
n0iOOl <= n0i11i;
|
n0iOOO <= n0i11l;
|
n0iOOO <= n0i11l;
|
n0l0ll <= n0liil;
|
n0l0ll <= n0liil;
|
n0l11i <= n0i11O;
|
n0l11i <= n0i11O;
|
n0li0O <= wire_n0l0lO_dataout;
|
n0li0O <= wire_n0l0lO_dataout;
|
n0liil <= nlOl10l;
|
n0liil <= nlOl11i;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
n0lili = 0;
|
n0lili = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge n0O0lO)
|
always @ ( posedge wire_nl00l_clkout or posedge n0O0lO)
|
begin
|
begin
|
if (n0O0lO == 1'b1)
|
if (n0O0lO == 1'b1)
|
begin
|
begin
|
n0lili <= 0;
|
n0lili <= 0;
|
end
|
end
|
| Line 4730... |
Line 4770... |
n0O1iO = 0;
|
n0O1iO = 0;
|
n0O1li = 0;
|
n0O1li = 0;
|
n0O1ll = 0;
|
n0O1ll = 0;
|
n0O1Oi = 0;
|
n0O1Oi = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0ll)
|
begin
|
begin
|
if (nliii0i == 1'b1)
|
if (nlii0ll == 1'b1)
|
begin
|
begin
|
n0liOi <= 0;
|
n0liOi <= 0;
|
n0liOl <= 0;
|
n0liOl <= 0;
|
n0liOO <= 0;
|
n0liOO <= 0;
|
n0ll1i <= 0;
|
n0ll1i <= 0;
|
| Line 4757... |
Line 4797... |
n0O1iO <= 0;
|
n0O1iO <= 0;
|
n0O1li <= 0;
|
n0O1li <= 0;
|
n0O1ll <= 0;
|
n0O1ll <= 0;
|
n0O1Oi <= 0;
|
n0O1Oi <= 0;
|
end
|
end
|
else if (nlil01i == 1'b1)
|
else if (nlil1il == 1'b1)
|
begin
|
begin
|
n0liOi <= wire_n0ll0l_dataout;
|
n0liOi <= wire_n0ll0l_dataout;
|
n0liOl <= wire_n0ll0O_dataout;
|
n0liOl <= wire_n0ll0O_dataout;
|
n0liOO <= wire_n0llii_dataout;
|
n0liOO <= wire_n0llii_dataout;
|
n0ll1i <= wire_n0llil_dataout;
|
n0ll1i <= wire_n0llil_dataout;
|
| Line 4788... |
Line 4828... |
initial
|
initial
|
begin
|
begin
|
n0O0ll = 0;
|
n0O0ll = 0;
|
n0O0Oi = 0;
|
n0O0Oi = 0;
|
n0Oiil = 0;
|
n0Oiil = 0;
|
n101OO = 0;
|
n101ll = 0;
|
nlOi00O = 0;
|
nlOi01l = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge nlilill)
|
always @ ( posedge wire_nl0ii_clkout or posedge nlili1O)
|
begin
|
begin
|
if (nlilill == 1'b1)
|
if (nlili1O == 1'b1)
|
begin
|
begin
|
n0O0ll <= 1;
|
n0O0ll <= 1;
|
n0O0Oi <= 1;
|
n0O0Oi <= 1;
|
n0Oiil <= 1;
|
n0Oiil <= 1;
|
n101OO <= 1;
|
n101ll <= 1;
|
nlOi00O <= 1;
|
nlOi01l <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n0O0ll <= (~ (wire_n01lii_dout[1] & (~ wire_n01lii_dout[0])));
|
n0O0ll <= (~ (wire_n01ilO_dout[1] & (~ wire_n01ilO_dout[0])));
|
n0O0Oi <= ((nlilill | n0O11l) | n01l1O);
|
n0O0Oi <= ((nlili1O | n0O11l) | n01iil);
|
n0Oiil <= wire_n01lii_dout[1];
|
n0Oiil <= wire_n01ilO_dout[1];
|
n101OO <= wire_n10i0i_dataout;
|
n101ll <= wire_n100OO_dataout;
|
nlOi00O <= wire_nlOi0OO_dataout;
|
nlOi01l <= wire_nlOi0ll_dataout;
|
end
|
end
|
end
|
end
|
event n0O0ll_event;
|
event n0O0ll_event;
|
event n0O0Oi_event;
|
event n0O0Oi_event;
|
event n0Oiil_event;
|
event n0Oiil_event;
|
event n101OO_event;
|
event n101ll_event;
|
event nlOi00O_event;
|
event nlOi01l_event;
|
initial
|
initial
|
#1 ->n0O0ll_event;
|
#1 ->n0O0ll_event;
|
initial
|
initial
|
#1 ->n0O0Oi_event;
|
#1 ->n0O0Oi_event;
|
initial
|
initial
|
#1 ->n0Oiil_event;
|
#1 ->n0Oiil_event;
|
initial
|
initial
|
#1 ->n101OO_event;
|
#1 ->n101ll_event;
|
initial
|
initial
|
#1 ->nlOi00O_event;
|
#1 ->nlOi01l_event;
|
always @(n0O0ll_event)
|
always @(n0O0ll_event)
|
n0O0ll <= 1;
|
n0O0ll <= 1;
|
always @(n0O0Oi_event)
|
always @(n0O0Oi_event)
|
n0O0Oi <= 1;
|
n0O0Oi <= 1;
|
always @(n0Oiil_event)
|
always @(n0Oiil_event)
|
n0Oiil <= 1;
|
n0Oiil <= 1;
|
always @(n101OO_event)
|
always @(n101ll_event)
|
n101OO <= 1;
|
n101ll <= 1;
|
always @(nlOi00O_event)
|
always @(nlOi01l_event)
|
nlOi00O <= 1;
|
nlOi01l <= 1;
|
initial
|
initial
|
begin
|
begin
|
n0lO0O = 0;
|
n0lO0O = 0;
|
n0lO1i = 0;
|
n0lO1i = 0;
|
n0O0iO = 0;
|
n0O0iO = 0;
|
n0O11i = 0;
|
n0O11i = 0;
|
n0Oi1i = 0;
|
n0Oi1i = 0;
|
n0Oili = 0;
|
n0Oili = 0;
|
nlil00i = 0;
|
nlil01i = 0;
|
nlil00l = 0;
|
nlil01l = 0;
|
nlil00O = 0;
|
|
nlil01O = 0;
|
nlil01O = 0;
|
nlil0ii = 0;
|
nlil10i = 0;
|
nlil0il = 0;
|
nlil1li = 0;
|
nlil0iO = 0;
|
nlil1ll = 0;
|
nlil0li = 0;
|
|
nlil0ll = 0;
|
|
nlil1lO = 0;
|
nlil1lO = 0;
|
nliliiO = 0;
|
nlil1Oi = 0;
|
|
nlil1Ol = 0;
|
|
nlil1OO = 0;
|
|
nlili1i = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0ll)
|
begin
|
begin
|
if (nliii0i == 1'b1)
|
if (nlii0ll == 1'b1)
|
begin
|
begin
|
n0lO0O <= 0;
|
n0lO0O <= 0;
|
n0lO1i <= 0;
|
n0lO1i <= 0;
|
n0O0iO <= 0;
|
n0O0iO <= 0;
|
n0O11i <= 0;
|
n0O11i <= 0;
|
n0Oi1i <= 0;
|
n0Oi1i <= 0;
|
n0Oili <= 0;
|
n0Oili <= 0;
|
nlil00i <= 0;
|
nlil01i <= 0;
|
nlil00l <= 0;
|
nlil01l <= 0;
|
nlil00O <= 0;
|
|
nlil01O <= 0;
|
nlil01O <= 0;
|
nlil0ii <= 0;
|
nlil10i <= 0;
|
nlil0il <= 0;
|
nlil1li <= 0;
|
nlil0iO <= 0;
|
nlil1ll <= 0;
|
nlil0li <= 0;
|
|
nlil0ll <= 0;
|
|
nlil1lO <= 0;
|
nlil1lO <= 0;
|
nliliiO <= 0;
|
nlil1Oi <= 0;
|
|
nlil1Ol <= 0;
|
|
nlil1OO <= 0;
|
|
nlili1i <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n0lO0O <= (~ (wire_n01l0O_dout[1] & (~ wire_n01l0O_dout[0])));
|
n0lO0O <= (~ (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])));
|
n0lO1i <= n0lO0O;
|
n0lO1i <= n0lO0O;
|
n0O0iO <= (~ nli1ilO);
|
n0O0iO <= (~ nli10OO);
|
n0O11i <= (~ ((~ (n0Oili ^ wire_n01l0O_dout[0])) & (~ (n0OilO ^ wire_n01l0O_dout[1]))));
|
n0O11i <= (~ ((~ (n0Oili ^ wire_n01ill_dout[0])) & (~ (n0OilO ^ wire_n01ill_dout[1]))));
|
n0Oi1i <= wire_n0Oi0l_dataout;
|
n0Oi1i <= wire_n0Oi0l_dataout;
|
n0Oili <= wire_n01l0O_dout[0];
|
n0Oili <= wire_n01ill_dout[0];
|
nlil00i <= wire_nlil0Ol_dataout;
|
nlil01i <= wire_nlil0lO_dataout;
|
nlil00l <= wire_nlil0OO_dataout;
|
nlil01l <= wire_nlil0Oi_dataout;
|
nlil00O <= wire_nlili1i_dataout;
|
nlil01O <= nlili1i;
|
nlil01O <= wire_nlil0Oi_dataout;
|
nlil10i <= wire_nlil00i_dataout;
|
nlil0ii <= wire_nlili1l_dataout;
|
nlil1li <= wire_nlil00l_dataout;
|
nlil0il <= wire_nlili0i_dataout;
|
nlil1ll <= wire_nlil00O_dataout;
|
nlil0iO <= wire_nlili0l_dataout;
|
nlil1lO <= wire_nlil0ii_dataout;
|
nlil0li <= wire_nlili0O_dataout;
|
nlil1Oi <= wire_nlil0il_dataout;
|
nlil0ll <= nliliiO;
|
nlil1Ol <= wire_nlil0iO_dataout;
|
nlil1lO <= wire_nlil0lO_dataout;
|
nlil1OO <= wire_nlil0ll_dataout;
|
nliliiO <= nl011O;
|
nlili1i <= nl011O;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
n0O0li = 0;
|
n0O0li = 0;
|
n0O0lO = 0;
|
n0O0lO = 0;
|
n0OilO = 0;
|
n0OilO = 0;
|
nlil01i = 0;
|
nlil0OO = 0;
|
nliliil = 0;
|
nlil1il = 0;
|
nlilili = 0;
|
nlili1l = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0ll)
|
begin
|
begin
|
if (nliii0i == 1'b1)
|
if (nlii0ll == 1'b1)
|
begin
|
begin
|
n0O0li <= 1;
|
n0O0li <= 1;
|
n0O0lO <= 1;
|
n0O0lO <= 1;
|
n0OilO <= 1;
|
n0OilO <= 1;
|
nlil01i <= 1;
|
nlil0OO <= 1;
|
nliliil <= 1;
|
nlil1il <= 1;
|
nlilili <= 1;
|
nlili1l <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n0O0li <= nli1ilO;
|
n0O0li <= nli10OO;
|
n0O0lO <= ((nliii0i | n0O11i) | n01l1i);
|
n0O0lO <= ((nlii0ll | n0O11i) | n01i0O);
|
n0OilO <= wire_n01l0O_dout[1];
|
n0OilO <= wire_n01ill_dout[1];
|
nlil01i <= wire_nlil1Oi_dataout;
|
nlil0OO <= nlili1l;
|
nliliil <= nlilili;
|
nlil1il <= wire_nlil10l_dataout;
|
nlilili <= nl010i;
|
nlili1l <= nl010i;
|
end
|
end
|
end
|
end
|
event n0O0li_event;
|
event n0O0li_event;
|
event n0O0lO_event;
|
event n0O0lO_event;
|
event n0OilO_event;
|
event n0OilO_event;
|
event nlil01i_event;
|
event nlil0OO_event;
|
event nliliil_event;
|
event nlil1il_event;
|
event nlilili_event;
|
event nlili1l_event;
|
initial
|
initial
|
#1 ->n0O0li_event;
|
#1 ->n0O0li_event;
|
initial
|
initial
|
#1 ->n0O0lO_event;
|
#1 ->n0O0lO_event;
|
initial
|
initial
|
#1 ->n0OilO_event;
|
#1 ->n0OilO_event;
|
initial
|
initial
|
#1 ->nlil01i_event;
|
#1 ->nlil0OO_event;
|
initial
|
initial
|
#1 ->nliliil_event;
|
#1 ->nlil1il_event;
|
initial
|
initial
|
#1 ->nlilili_event;
|
#1 ->nlili1l_event;
|
always @(n0O0li_event)
|
always @(n0O0li_event)
|
n0O0li <= 1;
|
n0O0li <= 1;
|
always @(n0O0lO_event)
|
always @(n0O0lO_event)
|
n0O0lO <= 1;
|
n0O0lO <= 1;
|
always @(n0OilO_event)
|
always @(n0OilO_event)
|
n0OilO <= 1;
|
n0OilO <= 1;
|
always @(nlil01i_event)
|
always @(nlil0OO_event)
|
nlil01i <= 1;
|
nlil0OO <= 1;
|
always @(nliliil_event)
|
always @(nlil1il_event)
|
nliliil <= 1;
|
nlil1il <= 1;
|
always @(nlilili_event)
|
always @(nlili1l_event)
|
nlilili <= 1;
|
nlili1l <= 1;
|
initial
|
initial
|
begin
|
begin
|
n01l1i = 0;
|
n01i0O = 0;
|
n01l1l = 0;
|
n01iii = 0;
|
n0OiOi = 0;
|
n0OiOi = 0;
|
n0OiOl = 0;
|
n0OiOl = 0;
|
n0OiOO = 0;
|
n0OiOO = 0;
|
n0Ol1l = 0;
|
n0Ol1l = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nlilOl)
|
always @ ( posedge wire_nl00l_clkout or posedge nlilOl)
|
begin
|
begin
|
if (nlilOl == 1'b1)
|
if (nlilOl == 1'b1)
|
begin
|
begin
|
n01l1i <= 1;
|
n01i0O <= 1;
|
n01l1l <= 1;
|
n01iii <= 1;
|
n0OiOi <= 1;
|
n0OiOi <= 1;
|
n0OiOl <= 1;
|
n0OiOl <= 1;
|
n0OiOO <= 1;
|
n0OiOO <= 1;
|
n0Ol1l <= 1;
|
n0Ol1l <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n01l1i <= n01l1l;
|
n01i0O <= n01iii;
|
n01l1l <= nlii0Oi;
|
n01iii <= nlii0iO;
|
n0OiOi <= n0OiOl;
|
n0OiOi <= n0OiOl;
|
n0OiOl <= nlii0Oi;
|
n0OiOl <= nlii0iO;
|
n0OiOO <= n0Ol1l;
|
n0OiOO <= n0Ol1l;
|
n0Ol1l <= nlii0Oi;
|
n0Ol1l <= nlii0iO;
|
end
|
end
|
end
|
end
|
event n01l1i_event;
|
event n01i0O_event;
|
event n01l1l_event;
|
event n01iii_event;
|
event n0OiOi_event;
|
event n0OiOi_event;
|
event n0OiOl_event;
|
event n0OiOl_event;
|
event n0OiOO_event;
|
event n0OiOO_event;
|
event n0Ol1l_event;
|
event n0Ol1l_event;
|
initial
|
initial
|
#1 ->n01l1i_event;
|
#1 ->n01i0O_event;
|
initial
|
initial
|
#1 ->n01l1l_event;
|
#1 ->n01iii_event;
|
initial
|
initial
|
#1 ->n0OiOi_event;
|
#1 ->n0OiOi_event;
|
initial
|
initial
|
#1 ->n0OiOl_event;
|
#1 ->n0OiOl_event;
|
initial
|
initial
|
#1 ->n0OiOO_event;
|
#1 ->n0OiOO_event;
|
initial
|
initial
|
#1 ->n0Ol1l_event;
|
#1 ->n0Ol1l_event;
|
always @(n01l1i_event)
|
always @(n01i0O_event)
|
n01l1i <= 1;
|
n01i0O <= 1;
|
always @(n01l1l_event)
|
always @(n01iii_event)
|
n01l1l <= 1;
|
n01iii <= 1;
|
always @(n0OiOi_event)
|
always @(n0OiOi_event)
|
n0OiOi <= 1;
|
n0OiOi <= 1;
|
always @(n0OiOl_event)
|
always @(n0OiOl_event)
|
n0OiOl <= 1;
|
n0OiOl <= 1;
|
always @(n0OiOO_event)
|
always @(n0OiOO_event)
|
| Line 5031... |
Line 5071... |
n0OliO = 0;
|
n0OliO = 0;
|
n0Olli = 0;
|
n0Olli = 0;
|
n0Olll = 0;
|
n0Olll = 0;
|
n0OO1l = 0;
|
n0OO1l = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii1O)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0li)
|
begin
|
begin
|
if (nliii1O == 1'b1)
|
if (nlii0li == 1'b1)
|
begin
|
begin
|
n0Ol0i <= 0;
|
n0Ol0i <= 0;
|
n0Ol0l <= 0;
|
n0Ol0l <= 0;
|
n0Ol0O <= 0;
|
n0Ol0O <= 0;
|
n0Ol1O <= 0;
|
n0Ol1O <= 0;
|
| Line 5062... |
Line 5102... |
n0OO1l <= (ni1lOi | ni1llO);
|
n0OO1l <= (ni1lOi | ni1llO);
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
|
n110l = 0;
|
|
n11ii = 0;
|
|
nl010i = 0;
|
|
nllllO = 0;
|
|
nlOOll = 0;
|
|
end
|
|
always @ ( posedge clk or posedge reset)
|
|
begin
|
|
if (reset == 1'b1)
|
|
begin
|
|
n110l <= 1;
|
|
n11ii <= 1;
|
|
nl010i <= 1;
|
|
nllllO <= 1;
|
|
nlOOll <= 1;
|
|
end
|
|
else
|
|
begin
|
|
n110l <= n11ii;
|
|
n11ii <= nlii0iO;
|
|
nl010i <= wire_nl01il_dataout;
|
|
nllllO <= (~ nlOOli);
|
|
nlOOll <= wire_nlOilO_o;
|
|
end
|
|
end
|
|
event n110l_event;
|
|
event n11ii_event;
|
|
event nl010i_event;
|
|
event nllllO_event;
|
|
event nlOOll_event;
|
|
initial
|
|
#1 ->n110l_event;
|
|
initial
|
|
#1 ->n11ii_event;
|
|
initial
|
|
#1 ->nl010i_event;
|
|
initial
|
|
#1 ->nllllO_event;
|
|
initial
|
|
#1 ->nlOOll_event;
|
|
always @(n110l_event)
|
|
n110l <= 1;
|
|
always @(n11ii_event)
|
|
n11ii <= 1;
|
|
always @(nl010i_event)
|
|
nl010i <= 1;
|
|
always @(nllllO_event)
|
|
nllllO <= 1;
|
|
always @(nlOOll_event)
|
|
nlOOll <= 1;
|
|
initial
|
|
begin
|
|
n11il = 0;
|
|
n11iO = 0;
|
|
n11li = 0;
|
|
n11ll = 0;
|
|
n11lO = 0;
|
|
n11Ol = 0;
|
|
end
|
|
always @ ( posedge clk or negedge wire_n11Oi_CLRN)
|
|
begin
|
|
if (wire_n11Oi_CLRN == 1'b0)
|
|
begin
|
|
n11il <= 0;
|
|
n11iO <= 0;
|
|
n11li <= 0;
|
|
n11ll <= 0;
|
|
n11lO <= 0;
|
|
n11Ol <= 0;
|
|
end
|
|
else
|
|
begin
|
|
n11il <= reconfig_busy;
|
|
n11iO <= ((~ n1l1i) & wire_nl00O_freqlocked);
|
|
n11li <= wire_nli1l_dataout;
|
|
n11ll <= n11li;
|
|
n11lO <= n11il;
|
|
n11Ol <= n11iO;
|
|
end
|
|
end
|
|
assign
|
|
wire_n11Oi_CLRN = (nli000i56 ^ nli000i55);
|
|
initial
|
|
begin
|
ni00ll = 0;
|
ni00ll = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0i)
|
begin
|
begin
|
if (nili0i == 1'b1)
|
if (nili0i == 1'b1)
|
begin
|
begin
|
ni00ll <= 1;
|
ni00ll <= 1;
|
end
|
end
|
| Line 5094... |
Line 5218... |
ni00Oi = 0;
|
ni00Oi = 0;
|
ni00OO = 0;
|
ni00OO = 0;
|
ni01Ol = 0;
|
ni01Ol = 0;
|
ni01OO = 0;
|
ni01OO = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0i)
|
begin
|
begin
|
if (nili0i == 1'b1)
|
if (nili0i == 1'b1)
|
begin
|
begin
|
ni001i <= 0;
|
ni001i <= 0;
|
ni001l <= 0;
|
ni001l <= 0;
|
| Line 5139... |
Line 5263... |
ni1OiO = 0;
|
ni1OiO = 0;
|
ni1OOi = 0;
|
ni1OOi = 0;
|
ni1OOl = 0;
|
ni1OOl = 0;
|
ni1OOO = 0;
|
ni1OOO = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0l)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0l)
|
begin
|
begin
|
if (nili0l == 1'b1)
|
if (nili0l == 1'b1)
|
begin
|
begin
|
ni010i <= 0;
|
ni010i <= 0;
|
ni010l <= 0;
|
ni010l <= 0;
|
| Line 5155... |
Line 5279... |
ni1OiO <= 0;
|
ni1OiO <= 0;
|
ni1OOi <= 0;
|
ni1OOi <= 0;
|
ni1OOl <= 0;
|
ni1OOl <= 0;
|
ni1OOO <= 0;
|
ni1OOO <= 0;
|
end
|
end
|
else if (nli1l0i == 1'b1)
|
else if (nli1iii == 1'b1)
|
begin
|
begin
|
ni010i <= wire_ni01iO_dataout;
|
ni010i <= wire_ni01iO_dataout;
|
ni010l <= wire_ni01li_dataout;
|
ni010l <= wire_ni01li_dataout;
|
ni01ii <= wire_ni01ll_dataout;
|
ni01ii <= wire_ni01ll_dataout;
|
ni1O0l <= (ni010l ^ ni010i);
|
ni1O0l <= (ni010l ^ ni010i);
|
| Line 5174... |
Line 5298... |
end
|
end
|
initial
|
initial
|
begin
|
begin
|
ni011l = 0;
|
ni011l = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0l)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0l)
|
begin
|
begin
|
if (nili0l == 1'b1)
|
if (nili0l == 1'b1)
|
begin
|
begin
|
ni011l <= 1;
|
ni011l <= 1;
|
end
|
end
|
else if (nli1l0i == 1'b1)
|
else if (nli1iii == 1'b1)
|
begin
|
begin
|
ni011l <= wire_ni01il_dataout;
|
ni011l <= wire_ni01il_dataout;
|
end
|
end
|
end
|
end
|
event ni011l_event;
|
event ni011l_event;
|
| Line 5194... |
Line 5318... |
ni011l <= 1;
|
ni011l <= 1;
|
initial
|
initial
|
begin
|
begin
|
ni0lli = 0;
|
ni0lli = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0i)
|
begin
|
begin
|
if (nili0i == 1'b1)
|
if (nili0i == 1'b1)
|
begin
|
begin
|
ni0lli <= 0;
|
ni0lli <= 0;
|
end
|
end
|
else if (ni0lii == 1'b0)
|
else if (ni0lii == 1'b0)
|
begin
|
begin
|
ni0lli <= nliii0l;
|
ni0lli <= nlii0lO;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
ni0l0i = 0;
|
ni0l0i = 0;
|
ni0l0l = 0;
|
ni0l0l = 0;
|
ni0l0O = 0;
|
ni0l0O = 0;
|
ni0l1l = 0;
|
ni0l1l = 0;
|
ni0O0O = 0;
|
ni0O0O = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0l)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0l)
|
begin
|
begin
|
if (nili0l == 1'b1)
|
if (nili0l == 1'b1)
|
begin
|
begin
|
ni0l0i <= 0;
|
ni0l0i <= 0;
|
ni0l0l <= 0;
|
ni0l0l <= 0;
|
ni0l0O <= 0;
|
ni0l0O <= 0;
|
ni0l1l <= 0;
|
ni0l1l <= 0;
|
ni0O0O <= 0;
|
ni0O0O <= 0;
|
end
|
end
|
else if (nliilOi == 1'b1)
|
else if (nliil0l == 1'b1)
|
begin
|
begin
|
ni0l0i <= wire_ni0lil_o[2];
|
ni0l0i <= wire_ni0lil_o[2];
|
ni0l0l <= wire_ni0lil_o[3];
|
ni0l0l <= wire_ni0lil_o[3];
|
ni0l0O <= wire_ni0lil_o[4];
|
ni0l0O <= wire_ni0lil_o[4];
|
ni0l1l <= wire_ni0lil_o[1];
|
ni0l1l <= wire_ni0lil_o[1];
|
| Line 5236... |
Line 5360... |
end
|
end
|
initial
|
initial
|
begin
|
begin
|
ni1i1l = 0;
|
ni1i1l = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii1O)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0li)
|
begin
|
begin
|
if (nliii1O == 1'b1)
|
if (nlii0li == 1'b1)
|
begin
|
begin
|
ni1i1l <= 1;
|
ni1i1l <= 1;
|
end
|
end
|
else if (nliilOi == 1'b1)
|
else if (nliil0l == 1'b1)
|
begin
|
begin
|
ni1i1l <= wire_ni101l_o;
|
ni1i1l <= wire_ni101l_o;
|
end
|
end
|
end
|
end
|
event ni1i1l_event;
|
event ni1i1l_event;
|
| Line 5263... |
Line 5387... |
nii11i = 0;
|
nii11i = 0;
|
nii11l = 0;
|
nii11l = 0;
|
nii11O = 0;
|
nii11O = 0;
|
nii1ii = 0;
|
nii1ii = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0l)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0l)
|
begin
|
begin
|
if (nili0l == 1'b1)
|
if (nili0l == 1'b1)
|
begin
|
begin
|
ni0OOi <= 0;
|
ni0OOi <= 0;
|
ni0OOO <= 0;
|
ni0OOO <= 0;
|
| Line 5325... |
Line 5449... |
nil01O = 0;
|
nil01O = 0;
|
nil0ii = 0;
|
nil0ii = 0;
|
nil1Ol = 0;
|
nil1Ol = 0;
|
nil1OO = 0;
|
nil1OO = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0i)
|
begin
|
begin
|
if (nili0i == 1'b1)
|
if (nili0i == 1'b1)
|
begin
|
begin
|
ni0lll <= 0;
|
ni0lll <= 0;
|
ni0lOi <= 0;
|
ni0lOi <= 0;
|
| Line 5409... |
Line 5533... |
ni0lii = 0;
|
ni0lii = 0;
|
nil00l = 0;
|
nil00l = 0;
|
nil01i = 0;
|
nil01i = 0;
|
nil0iO = 0;
|
nil0iO = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nili0i)
|
always @ ( posedge wire_nl00l_clkout or posedge nili0i)
|
begin
|
begin
|
if (nili0i == 1'b1)
|
if (nili0i == 1'b1)
|
begin
|
begin
|
ni0lii <= 1;
|
ni0lii <= 1;
|
nil00l <= 1;
|
nil00l <= 1;
|
| Line 5448... |
Line 5572... |
nil01i <= 1;
|
nil01i <= 1;
|
always @(nil0iO_event)
|
always @(nil0iO_event)
|
nil0iO <= 1;
|
nil0iO <= 1;
|
initial
|
initial
|
begin
|
begin
|
n0l1i = 0;
|
n011il = 0;
|
nil0O = 0;
|
n1i00i = 0;
|
niliO = 0;
|
n1i00l = 0;
|
end
|
n1i00O = 0;
|
always @ (wire_nl1ii_clkout or wire_nilil_PRN or wire_nilil_CLRN)
|
n1i0ii = 0;
|
begin
|
|
if (wire_nilil_PRN == 1'b0)
|
|
begin
|
|
n0l1i <= 1;
|
|
nil0O <= 1;
|
|
niliO <= 1;
|
|
end
|
|
else if (wire_nilil_CLRN == 1'b0)
|
|
begin
|
|
n0l1i <= 0;
|
|
nil0O <= 0;
|
|
niliO <= 0;
|
|
end
|
|
else
|
|
if (wire_nl1ii_clkout != nilil_clk_prev && wire_nl1ii_clkout == 1'b1)
|
|
begin
|
|
n0l1i <= (~ ((((((((((((((((((((niO0i & (niOii & ((niO0l & ((niO0O & (niOil & nlii00O)) & (nlii00i24 ^ nlii00i23))) & (nlii01l26 ^ nlii01l25)))) & (~ n0iil)) & (nlii1OO28 ^ nlii1OO27)) | ((niO0i & ((niO0O & (niOil & nlii1Ol)) & (nlii1lO30 ^ nlii1lO29))) & (nlii1li32 ^ nlii1li31))) | (~ (nlii1il34 ^ nlii1il33))) | ((~ niO0i) & ((niO0O & (niOil & nlii1ii)) & (nlii10l36 ^ nlii10l35)))) | (~ (nlii11O38 ^ nlii11O37))) | (((~ niO0i) & ((~ niO0O) & (niOil & nlii11l))) & (nli0OOO40 ^ nli0OOO39))) | (((~ niO0i) & (((~ niO0O) & (niOil & nli0OOl)) & (nli0OlO42 ^ nli0OlO41))) & (nli0Oli44 ^ nli0Oli43))) | ((~ niO0i) & ((~ niO0O) & (niOil & nli0OiO)))) | (~ (nli0Oii46 ^ nli0Oii45))) | ((niO1O & (((~ niO0i) & (((~ niO0O) & (niOil & nli0O0O)) & (nli0O0i48 ^ nli0O0i47))) & (nli0O1l50 ^ nli0O1l49))) & (nli0lOO52 ^ nli0lOO51))) | ((niO1O & ((~ niO0i) & (((~ niO0O) & (niOil & nli0lOl)) & (nli0llO54 ^ nli0llO53)))) & n0iil)) | ((niO1O & ((~ niO0i) & ((~ niO0O) & (niOil & nli0lll)))) & ((niOii & nli0lli) | ((~ niOii) & nli0liO)))) | ((~ niO0i) & ((~ niO0O) & (niOil & nli0lil)))) | ((~ niO0i) & ((~ niO0O) & (niOil & nli0lii)))) | ((~ niO0i) & ((~ niO0O) & (niOil & nli0l0O)))) | ((~ niO1O) & ((~ niO0i) & ((~ niO0O) & (niOil & nli0l0l))))) | ((((~ niO1O) & ((~ niO0i) & ((~ niO0O) & (niOil & nli0l0i)))) & n0iil) & nli0l1O)) | (((~ niO1O) & ((~ niO0i) & ((~ niO0O) & (niOil & nli0l1l)))) & nli0l1O)));
|
|
nil0O <= niO0l;
|
|
niliO <= niOii;
|
|
end
|
|
nilil_clk_prev <= wire_nl1ii_clkout;
|
|
end
|
|
assign
|
|
wire_nilil_CLRN = (nlii0il20 ^ nlii0il19),
|
|
wire_nilil_PRN = ((nlii0ii22 ^ nlii0ii21) & (~ n000l));
|
|
event n0l1i_event;
|
|
event nil0O_event;
|
|
event niliO_event;
|
|
initial
|
|
#1 ->n0l1i_event;
|
|
initial
|
|
#1 ->nil0O_event;
|
|
initial
|
|
#1 ->niliO_event;
|
|
always @(n0l1i_event)
|
|
n0l1i <= 1;
|
|
always @(nil0O_event)
|
|
nil0O <= 1;
|
|
always @(niliO_event)
|
|
niliO <= 1;
|
|
initial
|
|
begin
|
|
n0101O = 0;
|
|
n1i01i = 0;
|
|
n1i0il = 0;
|
|
n1i0iO = 0;
|
n1i0iO = 0;
|
n1i0li = 0;
|
n1i1il = 0;
|
n1i0ll = 0;
|
|
n1i0Oi = 0;
|
|
n1i1lO = 0;
|
n1i1lO = 0;
|
nili0i = 0;
|
nili0i = 0;
|
nili0l = 0;
|
nili0l = 0;
|
niO00i = 0;
|
niO00i = 0;
|
niO01l = 0;
|
niO01l = 0;
|
niO0ii = 0;
|
niO0ii = 0;
|
niO1ll = 0;
|
niO1ll = 0;
|
niO1Oi = 0;
|
niO1Oi = 0;
|
niO1OO = 0;
|
niO1OO = 0;
|
nliilOi = 0;
|
nliil0l = 0;
|
nlil10l = 0;
|
nliiOlO = 0;
|
nlil1ii = 0;
|
nliiOOl = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii1O)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0li)
|
begin
|
begin
|
if (nliii1O == 1'b1)
|
if (nlii0li == 1'b1)
|
begin
|
begin
|
n0101O <= 1;
|
n011il <= 1;
|
n1i01i <= 1;
|
n1i00i <= 1;
|
n1i0il <= 1;
|
n1i00l <= 1;
|
|
n1i00O <= 1;
|
|
n1i0ii <= 1;
|
n1i0iO <= 1;
|
n1i0iO <= 1;
|
n1i0li <= 1;
|
n1i1il <= 1;
|
n1i0ll <= 1;
|
|
n1i0Oi <= 1;
|
|
n1i1lO <= 1;
|
n1i1lO <= 1;
|
nili0i <= 1;
|
nili0i <= 1;
|
nili0l <= 1;
|
nili0l <= 1;
|
niO00i <= 1;
|
niO00i <= 1;
|
niO01l <= 1;
|
niO01l <= 1;
|
niO0ii <= 1;
|
niO0ii <= 1;
|
niO1ll <= 1;
|
niO1ll <= 1;
|
niO1Oi <= 1;
|
niO1Oi <= 1;
|
niO1OO <= 1;
|
niO1OO <= 1;
|
nliilOi <= 1;
|
nliil0l <= 1;
|
nlil10l <= 1;
|
nliiOlO <= 1;
|
nlil1ii <= 1;
|
nliiOOl <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n0101O <= wire_n01i0i_dataout;
|
n011il <= wire_n010iO_dataout;
|
n1i01i <= wire_n1i0OO_dataout;
|
n1i00i <= wire_n1i0Ol_dataout;
|
n1i0il <= wire_n1ii1O_dataout;
|
n1i00l <= wire_n1i0OO_dataout;
|
|
n1i00O <= wire_n1ii1i_dataout;
|
|
n1i0ii <= wire_n1ii1l_dataout;
|
n1i0iO <= wire_n1ii0i_dataout;
|
n1i0iO <= wire_n1ii0i_dataout;
|
n1i0li <= wire_n1ii0l_dataout;
|
n1i1il <= wire_n1i1Oi_dataout;
|
n1i0ll <= wire_n1ii0O_dataout;
|
n1i1lO <= wire_n1i0ll_dataout;
|
n1i0Oi <= wire_n1iiil_dataout;
|
nili0i <= ((nlii0li | nili1O) | n0OiOO);
|
n1i1lO <= wire_n1i01l_dataout;
|
nili0l <= ((nlii0li | nili1l) | n0OiOi);
|
nili0i <= ((nliii1O | nili1O) | n0OiOO);
|
|
nili0l <= ((nliii1O | nili1l) | n0OiOi);
|
|
niO00i <= niO0ii;
|
niO00i <= niO0ii;
|
niO01l <= niO00i;
|
niO01l <= niO00i;
|
niO0ii <= nl010i;
|
niO0ii <= nl010i;
|
niO1ll <= niO1Oi;
|
niO1ll <= niO1Oi;
|
niO1Oi <= niO1OO;
|
niO1Oi <= niO1OO;
|
niO1OO <= nl010i;
|
niO1OO <= nl010i;
|
nliilOi <= wire_nliilli_dataout;
|
nliil0l <= wire_nliil1l_dataout;
|
nlil10l <= nlil1ii;
|
nliiOlO <= nliiOOl;
|
nlil1ii <= nl010i;
|
nliiOOl <= nl010i;
|
end
|
end
|
end
|
end
|
event n0101O_event;
|
event n011il_event;
|
event n1i01i_event;
|
event n1i00i_event;
|
event n1i0il_event;
|
event n1i00l_event;
|
|
event n1i00O_event;
|
|
event n1i0ii_event;
|
event n1i0iO_event;
|
event n1i0iO_event;
|
event n1i0li_event;
|
event n1i1il_event;
|
event n1i0ll_event;
|
|
event n1i0Oi_event;
|
|
event n1i1lO_event;
|
event n1i1lO_event;
|
event nili0i_event;
|
event nili0i_event;
|
event nili0l_event;
|
event nili0l_event;
|
event niO00i_event;
|
event niO00i_event;
|
event niO01l_event;
|
event niO01l_event;
|
event niO0ii_event;
|
event niO0ii_event;
|
event niO1ll_event;
|
event niO1ll_event;
|
event niO1Oi_event;
|
event niO1Oi_event;
|
event niO1OO_event;
|
event niO1OO_event;
|
event nliilOi_event;
|
event nliil0l_event;
|
event nlil10l_event;
|
event nliiOlO_event;
|
event nlil1ii_event;
|
event nliiOOl_event;
|
initial
|
initial
|
#1 ->n0101O_event;
|
#1 ->n011il_event;
|
initial
|
initial
|
#1 ->n1i01i_event;
|
#1 ->n1i00i_event;
|
initial
|
initial
|
#1 ->n1i0il_event;
|
#1 ->n1i00l_event;
|
initial
|
initial
|
#1 ->n1i0iO_event;
|
#1 ->n1i00O_event;
|
initial
|
initial
|
#1 ->n1i0li_event;
|
#1 ->n1i0ii_event;
|
initial
|
initial
|
#1 ->n1i0ll_event;
|
#1 ->n1i0iO_event;
|
initial
|
initial
|
#1 ->n1i0Oi_event;
|
#1 ->n1i1il_event;
|
initial
|
initial
|
#1 ->n1i1lO_event;
|
#1 ->n1i1lO_event;
|
initial
|
initial
|
#1 ->nili0i_event;
|
#1 ->nili0i_event;
|
initial
|
initial
|
| Line 5614... |
Line 5691... |
initial
|
initial
|
#1 ->niO1Oi_event;
|
#1 ->niO1Oi_event;
|
initial
|
initial
|
#1 ->niO1OO_event;
|
#1 ->niO1OO_event;
|
initial
|
initial
|
#1 ->nliilOi_event;
|
#1 ->nliil0l_event;
|
initial
|
initial
|
#1 ->nlil10l_event;
|
#1 ->nliiOlO_event;
|
initial
|
initial
|
#1 ->nlil1ii_event;
|
#1 ->nliiOOl_event;
|
always @(n0101O_event)
|
always @(n011il_event)
|
n0101O <= 1;
|
n011il <= 1;
|
always @(n1i01i_event)
|
always @(n1i00i_event)
|
n1i01i <= 1;
|
n1i00i <= 1;
|
always @(n1i0il_event)
|
always @(n1i00l_event)
|
n1i0il <= 1;
|
n1i00l <= 1;
|
|
always @(n1i00O_event)
|
|
n1i00O <= 1;
|
|
always @(n1i0ii_event)
|
|
n1i0ii <= 1;
|
always @(n1i0iO_event)
|
always @(n1i0iO_event)
|
n1i0iO <= 1;
|
n1i0iO <= 1;
|
always @(n1i0li_event)
|
always @(n1i1il_event)
|
n1i0li <= 1;
|
n1i1il <= 1;
|
always @(n1i0ll_event)
|
|
n1i0ll <= 1;
|
|
always @(n1i0Oi_event)
|
|
n1i0Oi <= 1;
|
|
always @(n1i1lO_event)
|
always @(n1i1lO_event)
|
n1i1lO <= 1;
|
n1i1lO <= 1;
|
always @(nili0i_event)
|
always @(nili0i_event)
|
nili0i <= 1;
|
nili0i <= 1;
|
always @(nili0l_event)
|
always @(nili0l_event)
|
| Line 5651... |
Line 5728... |
niO1ll <= 1;
|
niO1ll <= 1;
|
always @(niO1Oi_event)
|
always @(niO1Oi_event)
|
niO1Oi <= 1;
|
niO1Oi <= 1;
|
always @(niO1OO_event)
|
always @(niO1OO_event)
|
niO1OO <= 1;
|
niO1OO <= 1;
|
always @(nliilOi_event)
|
always @(nliil0l_event)
|
nliilOi <= 1;
|
nliil0l <= 1;
|
always @(nlil10l_event)
|
always @(nliiOlO_event)
|
nlil10l <= 1;
|
nliiOlO <= 1;
|
always @(nlil1ii_event)
|
always @(nliiOOl_event)
|
nlil1ii <= 1;
|
nliiOOl <= 1;
|
initial
|
initial
|
begin
|
begin
|
n0OllO = 0;
|
n0OllO = 0;
|
n0OlOl = 0;
|
n0OlOl = 0;
|
n0OlOO = 0;
|
n0OlOO = 0;
|
| Line 5716... |
Line 5793... |
niO10O = 0;
|
niO10O = 0;
|
niO11i = 0;
|
niO11i = 0;
|
niO11l = 0;
|
niO11l = 0;
|
niO11O = 0;
|
niO11O = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii1O)
|
always @ ( posedge wire_nl00l_clkout or posedge nlii0li)
|
begin
|
begin
|
if (nliii1O == 1'b1)
|
if (nlii0li == 1'b1)
|
begin
|
begin
|
n0OllO <= 0;
|
n0OllO <= 0;
|
n0OlOl <= 0;
|
n0OlOl <= 0;
|
n0OlOO <= 0;
|
n0OlOO <= 0;
|
n0OO0i <= 0;
|
n0OO0i <= 0;
|
| Line 5777... |
Line 5854... |
niO10O <= 0;
|
niO10O <= 0;
|
niO11i <= 0;
|
niO11i <= 0;
|
niO11l <= 0;
|
niO11l <= 0;
|
niO11O <= 0;
|
niO11O <= 0;
|
end
|
end
|
else if (nliilOi == 1'b1)
|
else if (nliil0l == 1'b1)
|
begin
|
begin
|
n0OllO <= n0OlOl;
|
n0OllO <= n0OlOl;
|
n0OlOl <= nli1iOl;
|
n0OlOl <= nli1i1l;
|
n0OlOO <= wire_n0OOll_dataout;
|
n0OlOO <= wire_n0OOll_dataout;
|
n0OO0i <= wire_n0OOOi_dataout;
|
n0OO0i <= wire_n0OOOi_dataout;
|
n0OO0l <= wire_n0OOOl_dataout;
|
n0OO0l <= wire_n0OOOl_dataout;
|
n0OO0O <= wire_n0OOOO_dataout;
|
n0OO0O <= wire_n0OOOO_dataout;
|
n0OO1O <= wire_n0OOlO_dataout;
|
n0OO1O <= wire_n0OOlO_dataout;
|
| Line 5839... |
Line 5916... |
niO11O <= gmii_tx_d[6];
|
niO11O <= gmii_tx_d[6];
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
|
n0O1i = 0;
|
|
niO0O = 0;
|
|
niOiO = 0;
|
|
end
|
|
always @ ( posedge wire_nl0ii_clkout or negedge wire_niOil_PRN)
|
|
begin
|
|
if (wire_niOil_PRN == 1'b0)
|
|
begin
|
|
n0O1i <= 1;
|
|
niO0O <= 1;
|
|
niOiO <= 1;
|
|
end
|
|
else
|
|
begin
|
|
n0O1i <= (~ ((((((((((((((((((((nl10i & ((nl1ii & ((nl10l & (nl10O & (nl1il & nlii1Oi))) & (nlii1ll24 ^ nlii1ll23))) & (nlii1iO26 ^ nlii1iO25))) & (~ n0lil)) | ((nl10i & (nl10O & ((nl1il & nlii1il) & (nlii10O28 ^ nlii10O27)))) & (nlii10i30 ^ nlii10i29))) | (~ (nlii11l32 ^ nlii11l31))) | (((~ nl10i) & (nl10O & ((nl1il & nlii11i) & (nli0OOl34 ^ nli0OOl33)))) & (nli0OlO36 ^ nli0OlO35))) | ((~ nl10i) & ((~ nl10O) & ((nl1il & nli0Oll) & (nli0OiO38 ^ nli0OiO37))))) | (~ (nli0Oii40 ^ nli0Oii39))) | (((~ nl10i) & ((~ nl10O) & (nl1il & nli0O0O))) & (nli0O0i42 ^ nli0O0i41))) | (~ (nli0O1l44 ^ nli0O1l43))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0O1i)))) | ((nl11O & (((~ nl10i) & ((~ nl10O) & ((nl1il & nli0lOO) & (nli0lOi46 ^ nli0lOi45)))) & (nli0lll48 ^ nli0lll47))) & (nli0liO50 ^ nli0liO49))) | (~ (nli0lii52 ^ nli0lii51))) | ((nl11O & (((~ nl10i) & ((~ nl10O) & (nl1il & nli0l0O))) & (nli0l0i54 ^ nli0l0i53))) & n0lil)) | ((nl11O & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0l1O)))) & ((nl1ii & nli0l1l) | ((~ nl1ii) & nli0l1i)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOO)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOl)))) | ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iOi)))) | ((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0ilO))))) | ((((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0ill)))) & n0lil) & nli0ili)) | (((~ nl11O) & ((~ nl10i) & ((~ nl10O) & (nl1il & nli0iiO)))) & nli0ili)));
|
|
niO0O <= nl10l;
|
|
niOiO <= nl1ii;
|
|
end
|
|
end
|
|
assign
|
|
wire_niOil_PRN = ((nlii01i20 ^ nlii01i19) & (~ n0i0l));
|
|
event n0O1i_event;
|
|
event niO0O_event;
|
|
event niOiO_event;
|
|
initial
|
|
#1 ->n0O1i_event;
|
|
initial
|
|
#1 ->niO0O_event;
|
|
initial
|
|
#1 ->niOiO_event;
|
|
always @(n0O1i_event)
|
|
n0O1i <= 1;
|
|
always @(niO0O_event)
|
|
niO0O <= 1;
|
|
always @(niOiO_event)
|
|
niOiO <= 1;
|
|
initial
|
|
begin
|
nl00ii = 0;
|
nl00ii = 0;
|
end
|
end
|
always @ ( posedge clk or posedge reset)
|
always @ ( posedge clk or posedge reset)
|
begin
|
begin
|
if (reset == 1'b1)
|
if (reset == 1'b1)
|
begin
|
begin
|
nl00ii <= 0;
|
nl00ii <= 0;
|
end
|
end
|
else if (wire_nl000O_ENA == 1'b1)
|
else if (wire_nl000O_ENA == 1'b1)
|
begin
|
begin
|
nl00ii <= nlO1iO;
|
nl00ii <= nlO01i;
|
end
|
end
|
end
|
end
|
assign
|
assign
|
wire_nl000O_ENA = (nli1O0l & nlO1il);
|
wire_nl000O_ENA = (nli1lil & nlO1OO);
|
|
initial
|
|
begin
|
|
n0lil = 0;
|
|
niO1i = 0;
|
|
niOii = 0;
|
|
niOli = 0;
|
|
niOll = 0;
|
|
niOlO = 0;
|
|
niOOi = 0;
|
|
niOOl = 0;
|
|
niOOO = 0;
|
|
nl01l = 0;
|
|
nl10i = 0;
|
|
nl10l = 0;
|
|
nl10O = 0;
|
|
nl11i = 0;
|
|
nl11l = 0;
|
|
nl11O = 0;
|
|
nl1ii = 0;
|
|
nl1il = 0;
|
|
nl1iO = 0;
|
|
nl1li = 0;
|
|
nl1ll = 0;
|
|
nl1lO = 0;
|
|
nl1Oi = 0;
|
|
nl1Ol = 0;
|
|
nl1OO = 0;
|
|
end
|
|
always @ ( posedge wire_nl0ii_clkout or negedge wire_nl01i_CLRN)
|
|
begin
|
|
if (wire_nl01i_CLRN == 1'b0)
|
|
begin
|
|
n0lil <= 0;
|
|
niO1i <= 0;
|
|
niOii <= 0;
|
|
niOli <= 0;
|
|
niOll <= 0;
|
|
niOlO <= 0;
|
|
niOOi <= 0;
|
|
niOOl <= 0;
|
|
niOOO <= 0;
|
|
nl01l <= 0;
|
|
nl10i <= 0;
|
|
nl10l <= 0;
|
|
nl10O <= 0;
|
|
nl11i <= 0;
|
|
nl11l <= 0;
|
|
nl11O <= 0;
|
|
nl1ii <= 0;
|
|
nl1il <= 0;
|
|
nl1iO <= 0;
|
|
nl1li <= 0;
|
|
nl1ll <= 0;
|
|
nl1lO <= 0;
|
|
nl1Oi <= 0;
|
|
nl1Ol <= 0;
|
|
nl1OO <= 0;
|
|
end
|
|
else
|
|
begin
|
|
n0lil <= wire_niO1l_dataout;
|
|
niO1i <= nl1il;
|
|
niOii <= nl10O;
|
|
niOli <= nl1iO;
|
|
niOll <= nl1li;
|
|
niOlO <= nl1ll;
|
|
niOOi <= nl1lO;
|
|
niOOl <= nl1Oi;
|
|
niOOO <= nl1Ol;
|
|
nl01l <= wire_nl0ii_dataout[7];
|
|
nl10i <= wire_nl0ii_patterndetect[0];
|
|
nl10l <= wire_nl0ii_errdetect[0];
|
|
nl10O <= wire_nl0ii_ctrldetect[0];
|
|
nl11i <= nl1OO;
|
|
nl11l <= nl01l;
|
|
nl11O <= wire_nl0ii_runningdisp[0];
|
|
nl1ii <= wire_nl0ii_disperr[0];
|
|
nl1il <= wire_nl0ii_syncstatus[0];
|
|
nl1iO <= wire_nl0ii_dataout[0];
|
|
nl1li <= wire_nl0ii_dataout[1];
|
|
nl1ll <= wire_nl0ii_dataout[2];
|
|
nl1lO <= wire_nl0ii_dataout[3];
|
|
nl1Oi <= wire_nl0ii_dataout[4];
|
|
nl1Ol <= wire_nl0ii_dataout[5];
|
|
nl1OO <= wire_nl0ii_dataout[6];
|
|
end
|
|
end
|
|
assign
|
|
wire_nl01i_CLRN = ((nlii01l18 ^ nlii01l17) & (~ n0i0l));
|
initial
|
initial
|
begin
|
begin
|
nl00ll = 0;
|
nl00ll = 0;
|
nl00Oi = 0;
|
nl00Oi = 0;
|
nl00Ol = 0;
|
nl00Ol = 0;
|
| Line 5874... |
Line 6078... |
nl00Ol <= 0;
|
nl00Ol <= 0;
|
nl00OO <= 0;
|
nl00OO <= 0;
|
nl0i1i <= 0;
|
nl0i1i <= 0;
|
nl0i1O <= 0;
|
nl0i1O <= 0;
|
end
|
end
|
else if (nli1Oii == 1'b1)
|
else if (nli1lli == 1'b1)
|
begin
|
begin
|
nl00ll <= nlO1iO;
|
nl00ll <= nlO01i;
|
nl00Oi <= nlO1li;
|
nl00Oi <= nlO01l;
|
nl00Ol <= nlO1ll;
|
nl00Ol <= nlO01O;
|
nl00OO <= nlO1lO;
|
nl00OO <= nlO00i;
|
nl0i1i <= nlO1Oi;
|
nl0i1i <= nlO00l;
|
nl0i1O <= nlO1Ol;
|
nl0i1O <= nlO00O;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
n000i = 0;
|
|
n110i = 0;
|
|
n111i = 0;
|
|
n111l = 0;
|
|
n111O = 0;
|
|
nl00O = 0;
|
|
nl01l = 0;
|
|
nl0il = 0;
|
|
nlOOOl = 0;
|
|
nlOOOO = 0;
|
|
end
|
|
always @ (clk or wire_nl0ii_PRN or wire_nl0ii_CLRN)
|
|
begin
|
|
if (wire_nl0ii_PRN == 1'b0)
|
|
begin
|
|
n000i <= 1;
|
|
n110i <= 1;
|
|
n111i <= 1;
|
|
n111l <= 1;
|
|
n111O <= 1;
|
|
nl00O <= 1;
|
|
nl01l <= 1;
|
|
nl0il <= 1;
|
|
nlOOOl <= 1;
|
|
nlOOOO <= 1;
|
|
end
|
|
else if (wire_nl0ii_CLRN == 1'b0)
|
|
begin
|
|
n000i <= 0;
|
|
n110i <= 0;
|
|
n111i <= 0;
|
|
n111l <= 0;
|
|
n111O <= 0;
|
|
nl00O <= 0;
|
|
nl01l <= 0;
|
|
nl0il <= 0;
|
|
nlOOOl <= 0;
|
|
nlOOOO <= 0;
|
|
end
|
|
else
|
|
if (clk != nl0ii_clk_prev && clk == 1'b1)
|
|
begin
|
|
n000i <= nlii0lO;
|
|
n110i <= nlOOOO;
|
|
n111i <= wire_nl01O_dataout;
|
|
n111l <= n111i;
|
|
n111O <= nlOOOl;
|
|
nl00O <= nl01l;
|
|
nl01l <= reset;
|
|
nl0il <= (((~ nl00O) & nl01l) & (nliii1i10 ^ nliii1i9));
|
|
nlOOOl <= reconfig_busy;
|
|
nlOOOO <= ((~ n1i0O) & wire_nl10O_freqlocked);
|
|
end
|
|
nl0ii_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nl0ii_CLRN = (nlii0OO12 ^ nlii0OO11),
|
|
wire_nl0ii_PRN = (nlii0Ol14 ^ nlii0Ol13);
|
|
initial
|
|
begin
|
|
nl0i0i = 0;
|
nl0i0i = 0;
|
nl0i0O = 0;
|
nl0i0O = 0;
|
nl0iii = 0;
|
nl0iii = 0;
|
nl0iiO = 0;
|
nl0iiO = 0;
|
nl0ilO = 0;
|
nl0ilO = 0;
|
| Line 5972... |
Line 6116... |
nl0iOO <= 0;
|
nl0iOO <= 0;
|
nl0l0i <= 0;
|
nl0l0i <= 0;
|
nl0l0O <= 0;
|
nl0l0O <= 0;
|
nl0l1O <= 0;
|
nl0l1O <= 0;
|
end
|
end
|
else if (nli1OOi == 1'b1)
|
else if (nli1O1i == 1'b1)
|
begin
|
begin
|
nl0i0i <= nlO1li;
|
nl0i0i <= nlO01l;
|
nl0i0O <= nlO1ll;
|
nl0i0O <= nlO01O;
|
nl0iii <= nlO1lO;
|
nl0iii <= nlO00i;
|
nl0iiO <= nlO1Ol;
|
nl0iiO <= nlO00O;
|
nl0ilO <= nlO01l;
|
nl0ilO <= nlO0iO;
|
nl0iOl <= nlO00i;
|
nl0iOl <= nlO0ll;
|
nl0iOO <= nlO00l;
|
nl0iOO <= nlO0lO;
|
nl0l0i <= nlO0il;
|
nl0l0i <= nlO0OO;
|
nl0l0O <= nlO0iO;
|
nl0l0O <= nlOi1i;
|
nl0l1O <= nlO0ii;
|
nl0l1O <= nlO0Ol;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
nl0iil = 0;
|
nl0iil = 0;
|
| Line 6004... |
Line 6148... |
nl0ili <= 1;
|
nl0ili <= 1;
|
nl0ill <= 1;
|
nl0ill <= 1;
|
nl0iOi <= 1;
|
nl0iOi <= 1;
|
nl0l1l <= 1;
|
nl0l1l <= 1;
|
end
|
end
|
else if (nli1OOi == 1'b1)
|
else if (nli1O1i == 1'b1)
|
begin
|
begin
|
nl0iil <= nlO1Oi;
|
nl0iil <= nlO00l;
|
nl0ili <= nlO1OO;
|
nl0ili <= nlO0ii;
|
nl0ill <= nlO01i;
|
nl0ill <= nlO0il;
|
nl0iOi <= nlO01O;
|
nl0iOi <= nlO0li;
|
nl0l1l <= nlO00O;
|
nl0l1l <= nlO0Oi;
|
end
|
end
|
end
|
end
|
event nl0iil_event;
|
event nl0iil_event;
|
event nl0ili_event;
|
event nl0ili_event;
|
event nl0ill_event;
|
event nl0ill_event;
|
| Line 6040... |
Line 6184... |
nl0iOi <= 1;
|
nl0iOi <= 1;
|
always @(nl0l1l_event)
|
always @(nl0l1l_event)
|
nl0l1l <= 1;
|
nl0l1l <= 1;
|
initial
|
initial
|
begin
|
begin
|
nl0liO = 0;
|
nl0li = 0;
|
nl0lll = 0;
|
nl0lO = 0;
|
end
|
end
|
always @ (clk or wire_nl0lli_PRN or reset)
|
always @ ( negedge reconfig_clk or negedge wire_nl0ll_PRN)
|
begin
|
begin
|
if (wire_nl0lli_PRN == 1'b0)
|
if (wire_nl0ll_PRN == 1'b0)
|
begin
|
begin
|
nl0liO <= 1;
|
nl0li <= 1;
|
nl0lll <= 1;
|
nl0lO <= 1;
|
end
|
end
|
else if (reset == 1'b1)
|
else
|
|
begin
|
|
nl0li <= reconfig_togxb[3];
|
|
nl0lO <= nl0li;
|
|
end
|
|
end
|
|
assign
|
|
wire_nl0ll_PRN = (nlii01O16 ^ nlii01O15);
|
|
initial
|
|
begin
|
|
nl0liO = 0;
|
|
nl0lll = 0;
|
|
end
|
|
always @ ( posedge clk or posedge reset)
|
|
begin
|
|
if (reset == 1'b1)
|
begin
|
begin
|
nl0liO <= 0;
|
nl0liO <= 0;
|
nl0lll <= 0;
|
nl0lll <= 0;
|
end
|
end
|
else if (nli1Oll == 1'b1)
|
else if (nli1lOl == 1'b1)
|
if (clk != nl0lli_clk_prev && clk == 1'b1)
|
|
begin
|
begin
|
nl0liO <= nlO1ll;
|
nl0liO <= nlO01O;
|
nl0lll <= nlO1lO;
|
nl0lll <= nlO00i;
|
end
|
end
|
nl0lli_clk_prev <= clk;
|
|
end
|
end
|
assign
|
|
wire_nl0lli_PRN = (nli1OiO80 ^ nli1OiO79);
|
|
initial
|
initial
|
begin
|
begin
|
nl0lii = 0;
|
nl0lii = 0;
|
nl0lil = 0;
|
nl0lil = 0;
|
nl0lOi = 0;
|
nl0lOi = 0;
|
end
|
end
|
always @ (clk or reset or wire_nl0llO_CLRN)
|
always @ (clk or wire_nl0llO_PRN or wire_nl0llO_CLRN)
|
begin
|
begin
|
if (reset == 1'b1)
|
if (wire_nl0llO_PRN == 1'b0)
|
begin
|
begin
|
nl0lii <= 1;
|
nl0lii <= 1;
|
nl0lil <= 1;
|
nl0lil <= 1;
|
nl0lOi <= 1;
|
nl0lOi <= 1;
|
end
|
end
|
| Line 6085... |
Line 6240... |
begin
|
begin
|
nl0lii <= 0;
|
nl0lii <= 0;
|
nl0lil <= 0;
|
nl0lil <= 0;
|
nl0lOi <= 0;
|
nl0lOi <= 0;
|
end
|
end
|
else if (nli1Oll == 1'b1)
|
else if (nli1lOl == 1'b1)
|
if (clk != nl0llO_clk_prev && clk == 1'b1)
|
if (clk != nl0llO_clk_prev && clk == 1'b1)
|
begin
|
begin
|
nl0lii <= nlO1iO;
|
nl0lii <= nlO01i;
|
nl0lil <= nlO1li;
|
nl0lil <= nlO01l;
|
nl0lOi <= nlO1Oi;
|
nl0lOi <= nlO00l;
|
end
|
end
|
nl0llO_clk_prev <= clk;
|
nl0llO_clk_prev <= clk;
|
end
|
end
|
assign
|
assign
|
wire_nl0llO_CLRN = (nli1Oli78 ^ nli1Oli77);
|
wire_nl0llO_CLRN = (nli1lOi78 ^ nli1lOi77),
|
|
wire_nl0llO_PRN = ((nli1llO80 ^ nli1llO79) & (~ reset));
|
event nl0lii_event;
|
event nl0lii_event;
|
event nl0lil_event;
|
event nl0lil_event;
|
event nl0lOi_event;
|
event nl0lOi_event;
|
initial
|
initial
|
#1 ->nl0lii_event;
|
#1 ->nl0lii_event;
|
| Line 6113... |
Line 6269... |
nl0lil <= 1;
|
nl0lil <= 1;
|
always @(nl0lOi_event)
|
always @(nl0lOi_event)
|
nl0lOi <= 1;
|
nl0lOi <= 1;
|
initial
|
initial
|
begin
|
begin
|
nl00l = 0;
|
|
nl0Oi = 0;
|
|
end
|
|
always @ (clk or wire_nl0lO_PRN or wire_nl0lO_CLRN)
|
|
begin
|
|
if (wire_nl0lO_PRN == 1'b0)
|
|
begin
|
|
nl00l <= 1;
|
|
nl0Oi <= 1;
|
|
end
|
|
else if (wire_nl0lO_CLRN == 1'b0)
|
|
begin
|
|
nl00l <= 0;
|
|
nl0Oi <= 0;
|
|
end
|
|
else
|
|
if (clk != nl0lO_clk_prev && clk == 1'b1)
|
|
begin
|
|
nl00l <= nlii0Oi;
|
|
nl0Oi <= nl00l;
|
|
end
|
|
nl0lO_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nl0lO_CLRN = (nliiiii6 ^ nliiiii5),
|
|
wire_nl0lO_PRN = ((nliii0O8 ^ nliii0O7) & (~ gxb_pwrdn_in));
|
|
event nl00l_event;
|
|
event nl0Oi_event;
|
|
initial
|
|
#1 ->nl00l_event;
|
|
initial
|
|
#1 ->nl0Oi_event;
|
|
always @(nl00l_event)
|
|
nl00l <= 1;
|
|
always @(nl0Oi_event)
|
|
nl0Oi <= 1;
|
|
initial
|
|
begin
|
|
n0iil = 0;
|
|
nil1i = 0;
|
|
nilii = 0;
|
|
nilli = 0;
|
|
nilll = 0;
|
|
nillO = 0;
|
|
nilOi = 0;
|
|
nilOl = 0;
|
|
nilOO = 0;
|
|
niO0i = 0;
|
|
niO0l = 0;
|
|
niO0O = 0;
|
|
niO1i = 0;
|
|
niO1l = 0;
|
|
niO1O = 0;
|
|
niOii = 0;
|
|
niOil = 0;
|
|
niOiO = 0;
|
|
niOli = 0;
|
|
niOll = 0;
|
|
niOlO = 0;
|
|
niOOi = 0;
|
|
niOOl = 0;
|
|
niOOO = 0;
|
|
nl11l = 0;
|
|
end
|
|
always @ ( posedge wire_nl1ii_clkout or posedge n000l)
|
|
begin
|
|
if (n000l == 1'b1)
|
|
begin
|
|
n0iil <= 0;
|
|
nil1i <= 0;
|
|
nilii <= 0;
|
|
nilli <= 0;
|
|
nilll <= 0;
|
|
nillO <= 0;
|
|
nilOi <= 0;
|
|
nilOl <= 0;
|
|
nilOO <= 0;
|
|
niO0i <= 0;
|
|
niO0l <= 0;
|
|
niO0O <= 0;
|
|
niO1i <= 0;
|
|
niO1l <= 0;
|
|
niO1O <= 0;
|
|
niOii <= 0;
|
|
niOil <= 0;
|
|
niOiO <= 0;
|
|
niOli <= 0;
|
|
niOll <= 0;
|
|
niOlO <= 0;
|
|
niOOi <= 0;
|
|
niOOl <= 0;
|
|
niOOO <= 0;
|
|
nl11l <= 0;
|
|
end
|
|
else
|
|
begin
|
|
n0iil <= wire_nil1l_dataout;
|
|
nil1i <= niOil;
|
|
nilii <= niO0O;
|
|
nilli <= niOiO;
|
|
nilll <= niOli;
|
|
nillO <= niOll;
|
|
nilOi <= niOlO;
|
|
nilOl <= niOOi;
|
|
nilOO <= niOOl;
|
|
niO0i <= wire_nl1ii_patterndetect[0];
|
|
niO0l <= wire_nl1ii_errdetect[0];
|
|
niO0O <= wire_nl1ii_ctrldetect[0];
|
|
niO1i <= niOOO;
|
|
niO1l <= nl11l;
|
|
niO1O <= wire_nl1ii_runningdisp[0];
|
|
niOii <= wire_nl1ii_disperr[0];
|
|
niOil <= wire_nl1ii_syncstatus[0];
|
|
niOiO <= wire_nl1ii_dataout[0];
|
|
niOli <= wire_nl1ii_dataout[1];
|
|
niOll <= wire_nl1ii_dataout[2];
|
|
niOlO <= wire_nl1ii_dataout[3];
|
|
niOOi <= wire_nl1ii_dataout[4];
|
|
niOOl <= wire_nl1ii_dataout[5];
|
|
niOOO <= wire_nl1ii_dataout[6];
|
|
nl11l <= wire_nl1ii_dataout[7];
|
|
end
|
|
end
|
|
initial
|
|
begin
|
|
nl111i = 0;
|
nl111i = 0;
|
nl1i0l = 0;
|
nl1i0l = 0;
|
nl1i0O = 0;
|
nl1i0O = 0;
|
nl1iii = 0;
|
nl1iii = 0;
|
nl1iil = 0;
|
nl1iil = 0;
|
| Line 6255... |
Line 6286... |
nl1l0l = 0;
|
nl1l0l = 0;
|
nl1l1i = 0;
|
nl1l1i = 0;
|
nl1l1l = 0;
|
nl1l1l = 0;
|
nl1l1O = 0;
|
nl1l1O = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge nlilill)
|
always @ ( posedge wire_nl0ii_clkout or posedge nlili1O)
|
begin
|
begin
|
if (nlilill == 1'b1)
|
if (nlili1O == 1'b1)
|
begin
|
begin
|
nl111i <= 0;
|
nl111i <= 0;
|
nl1i0l <= 0;
|
nl1i0l <= 0;
|
nl1i0O <= 0;
|
nl1i0O <= 0;
|
nl1iii <= 0;
|
nl1iii <= 0;
|
| Line 6276... |
Line 6307... |
nl1l0l <= 0;
|
nl1l0l <= 0;
|
nl1l1i <= 0;
|
nl1l1i <= 0;
|
nl1l1l <= 0;
|
nl1l1l <= 0;
|
nl1l1O <= 0;
|
nl1l1O <= 0;
|
end
|
end
|
else if (nll0ll == 1'b1)
|
else if (nlli1O == 1'b1)
|
begin
|
begin
|
nl111i <= wire_nl1lii_dataout;
|
nl111i <= wire_nl1lii_dataout;
|
nl1i0l <= wire_nl1lil_dataout;
|
nl1i0l <= wire_nl1lil_dataout;
|
nl1i0O <= wire_nl1liO_dataout;
|
nl1i0O <= wire_nl1liO_dataout;
|
nl1iii <= wire_nl1lli_dataout;
|
nl1iii <= wire_nl1lli_dataout;
|
| Line 6298... |
Line 6329... |
nl1l1O <= wire_nl1O0O_dataout;
|
nl1l1O <= wire_nl1O0O_dataout;
|
end
|
end
|
end
|
end
|
initial
|
initial
|
begin
|
begin
|
nl1li = 0;
|
nli0O = 0;
|
nl1lO = 0;
|
|
end
|
end
|
always @ ( negedge reconfig_clk or negedge wire_nl1ll_CLRN)
|
always @ (clk or wire_nli0l_PRN or wire_nli0l_CLRN)
|
begin
|
begin
|
if (wire_nl1ll_CLRN == 1'b0)
|
if (wire_nli0l_PRN == 1'b0)
|
begin
|
begin
|
nl1li <= 0;
|
nli0O <= 1;
|
nl1lO <= 0;
|
end
|
|
else if (wire_nli0l_CLRN == 1'b0)
|
|
begin
|
|
nli0O <= 0;
|
end
|
end
|
else
|
else
|
|
if (clk != nli0l_clk_prev && clk == 1'b1)
|
begin
|
begin
|
nl1li <= reconfig_togxb[3];
|
nli0O <= nlii0iO;
|
nl1lO <= nl1li;
|
|
end
|
end
|
|
nli0l_clk_prev <= clk;
|
end
|
end
|
assign
|
assign
|
wire_nl1ll_CLRN = (nlii0ll16 ^ nlii0ll15);
|
wire_nli0l_CLRN = (nlii0il10 ^ nlii0il9),
|
|
wire_nli0l_PRN = ((nlii0ii12 ^ nlii0ii11) & (~ n110l));
|
|
event nli0O_event;
|
|
initial
|
|
#1 ->nli0O_event;
|
|
always @(nli0O_event)
|
|
nli0O <= 1;
|
initial
|
initial
|
begin
|
begin
|
nl0lOl = 0;
|
nl0lOl = 0;
|
nl0O0i = 0;
|
nl0O0i = 0;
|
nl0O0l = 0;
|
nl0O0l = 0;
|
| Line 6335... |
Line 6375... |
nl0OOi = 0;
|
nl0OOi = 0;
|
nl0OOl = 0;
|
nl0OOl = 0;
|
nl0OOO = 0;
|
nl0OOO = 0;
|
nli11l = 0;
|
nli11l = 0;
|
end
|
end
|
always @ (clk or wire_nli11i_PRN or wire_nli11i_CLRN)
|
always @ ( posedge clk or posedge reset)
|
begin
|
|
if (wire_nli11i_PRN == 1'b0)
|
|
begin
|
begin
|
nl0lOl <= 1;
|
if (reset == 1'b1)
|
nl0O0i <= 1;
|
|
nl0O0l <= 1;
|
|
nl0O0O <= 1;
|
|
nl0O1l <= 1;
|
|
nl0O1O <= 1;
|
|
nl0Oii <= 1;
|
|
nl0Oil <= 1;
|
|
nl0OiO <= 1;
|
|
nl0Oli <= 1;
|
|
nl0Oll <= 1;
|
|
nl0OlO <= 1;
|
|
nl0OOi <= 1;
|
|
nl0OOl <= 1;
|
|
nl0OOO <= 1;
|
|
nli11l <= 1;
|
|
end
|
|
else if (wire_nli11i_CLRN == 1'b0)
|
|
begin
|
begin
|
nl0lOl <= 0;
|
nl0lOl <= 0;
|
nl0O0i <= 0;
|
nl0O0i <= 0;
|
nl0O0l <= 0;
|
nl0O0l <= 0;
|
nl0O0O <= 0;
|
nl0O0O <= 0;
|
| Line 6375... |
Line 6396... |
nl0OOi <= 0;
|
nl0OOi <= 0;
|
nl0OOl <= 0;
|
nl0OOl <= 0;
|
nl0OOO <= 0;
|
nl0OOO <= 0;
|
nli11l <= 0;
|
nli11l <= 0;
|
end
|
end
|
else if (nli011l == 1'b1)
|
else if (nli1O1O == 1'b1)
|
if (clk != nli11i_clk_prev && clk == 1'b1)
|
|
begin
|
begin
|
nl0lOl <= nlO1iO;
|
nl0lOl <= nlO01i;
|
nl0O0i <= nlO1lO;
|
nl0O0i <= nlO00i;
|
nl0O0l <= nlO1Oi;
|
nl0O0l <= nlO00l;
|
nl0O0O <= nlO1Ol;
|
nl0O0O <= nlO00O;
|
nl0O1l <= nlO1li;
|
nl0O1l <= nlO01l;
|
nl0O1O <= nlO1ll;
|
nl0O1O <= nlO01O;
|
nl0Oii <= nlO1OO;
|
nl0Oii <= nlO0ii;
|
nl0Oil <= nlO01i;
|
nl0Oil <= nlO0il;
|
nl0OiO <= nlO01l;
|
nl0OiO <= nlO0iO;
|
nl0Oli <= nlO01O;
|
nl0Oli <= nlO0li;
|
nl0Oll <= nlO00i;
|
nl0Oll <= nlO0ll;
|
nl0OlO <= nlO00l;
|
nl0OlO <= nlO0lO;
|
nl0OOi <= nlO00O;
|
nl0OOi <= nlO0Oi;
|
nl0OOl <= nlO0ii;
|
nl0OOl <= nlO0Ol;
|
nl0OOO <= nlO0il;
|
nl0OOO <= nlO0OO;
|
nli11l <= nlO0iO;
|
nli11l <= nlOi1i;
|
end
|
end
|
nli11i_clk_prev <= clk;
|
|
end
|
end
|
assign
|
|
wire_nli11i_CLRN = ((nli011i74 ^ nli011i73) & (~ reset)),
|
|
wire_nli11i_PRN = (nli1OOO76 ^ nli1OOO75);
|
|
initial
|
initial
|
begin
|
begin
|
nli00i = 0;
|
nli00i = 0;
|
nli00l = 0;
|
nli00l = 0;
|
nli00O = 0;
|
nli00O = 0;
|
| Line 6419... |
Line 6435... |
nli0OO = 0;
|
nli0OO = 0;
|
nli1OO = 0;
|
nli1OO = 0;
|
nlii1i = 0;
|
nlii1i = 0;
|
nlii1O = 0;
|
nlii1O = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge nlilill)
|
always @ ( posedge wire_nl0ii_clkout or negedge wire_nlii1l_CLRN)
|
begin
|
begin
|
if (nlilill == 1'b1)
|
if (wire_nlii1l_CLRN == 1'b0)
|
begin
|
begin
|
nli00i <= 0;
|
nli00i <= 0;
|
nli00l <= 0;
|
nli00l <= 0;
|
nli00O <= 0;
|
nli00O <= 0;
|
nli01O <= 0;
|
nli01O <= 0;
|
| Line 6440... |
Line 6456... |
nli0OO <= 0;
|
nli0OO <= 0;
|
nli1OO <= 0;
|
nli1OO <= 0;
|
nlii1i <= 0;
|
nlii1i <= 0;
|
nlii1O <= 0;
|
nlii1O <= 0;
|
end
|
end
|
else if (nlOO11i == 1'b1)
|
else if (nlOlOlO == 1'b1)
|
begin
|
begin
|
nli00i <= nlOO1iO;
|
nli00i <= nlOO10l;
|
nli00l <= nlOO1li;
|
nli00l <= nlOO10O;
|
nli00O <= nlOO1ll;
|
nli00O <= nlOO1ii;
|
nli01O <= nlOO1il;
|
nli01O <= nlOO10i;
|
nli0ii <= nlOO1lO;
|
nli0ii <= nlOO1il;
|
nli0il <= nlOO1Oi;
|
nli0il <= nlOO1iO;
|
nli0iO <= nlOO1Ol;
|
nli0iO <= nlOO1li;
|
nli0li <= nlOO1OO;
|
nli0li <= nlOO1ll;
|
nli0ll <= nlOO01i;
|
nli0ll <= nlOO1lO;
|
nli0lO <= nlOO01l;
|
nli0lO <= nlOO1Oi;
|
nli0Oi <= nlOO01O;
|
nli0Oi <= nlOO1Ol;
|
nli0Ol <= nlOO00i;
|
nli0Ol <= nlOO1OO;
|
nli0OO <= nlOO00l;
|
nli0OO <= nlOO01i;
|
nli1OO <= nlOO10O;
|
nli1OO <= nlOO11l;
|
nlii1i <= nlOO00O;
|
nlii1i <= nlOO01l;
|
nlii1O <= nlOO0ii;
|
nlii1O <= nlOO01O;
|
end
|
end
|
end
|
end
|
|
assign
|
|
wire_nlii1l_CLRN = ((nli1O0O76 ^ nli1O0O75) & (~ nlili1O));
|
initial
|
initial
|
begin
|
begin
|
nliiiOl = 0;
|
nliii0O = 0;
|
nliil1i = 0;
|
nliiiil = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nli0l1i)
|
always @ ( posedge wire_nl00l_clkout or posedge nli0iil)
|
begin
|
begin
|
if (nli0l1i == 1'b1)
|
if (nli0iil == 1'b1)
|
begin
|
begin
|
nliiiOl <= 1;
|
nliii0O <= 1;
|
nliil1i <= 1;
|
nliiiil <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
nliiiOl <= nliil1i;
|
nliii0O <= nliiiil;
|
nliil1i <= nlii0Oi;
|
nliiiil <= nlii0iO;
|
end
|
end
|
end
|
end
|
event nliiiOl_event;
|
event nliii0O_event;
|
event nliil1i_event;
|
event nliiiil_event;
|
initial
|
initial
|
#1 ->nliiiOl_event;
|
#1 ->nliii0O_event;
|
initial
|
initial
|
#1 ->nliil1i_event;
|
#1 ->nliiiil_event;
|
always @(nliiiOl_event)
|
always @(nliii0O_event)
|
nliiiOl <= 1;
|
nliii0O <= 1;
|
always @(nliil1i_event)
|
always @(nliiiil_event)
|
nliil1i <= 1;
|
nliiiil <= 1;
|
initial
|
initial
|
begin
|
begin
|
nliil0i = 0;
|
nliiiiO = 0;
|
nliil1l = 0;
|
nliiill = 0;
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nli0ill)
|
always @ ( posedge wire_nl00l_clkout or posedge nli0i1l)
|
begin
|
begin
|
if (nli0ill == 1'b1)
|
if (nli0i1l == 1'b1)
|
begin
|
begin
|
nliil0i <= 1;
|
nliiiiO <= 1;
|
nliil1l <= 1;
|
nliiill <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
nliil0i <= nlii0Oi;
|
nliiiiO <= nliiill;
|
nliil1l <= nliil0i;
|
nliiill <= nlii0iO;
|
end
|
end
|
end
|
end
|
event nliil0i_event;
|
event nliiiiO_event;
|
event nliil1l_event;
|
event nliiill_event;
|
initial
|
initial
|
#1 ->nliil0i_event;
|
#1 ->nliiiiO_event;
|
initial
|
initial
|
#1 ->nliil1l_event;
|
#1 ->nliiill_event;
|
always @(nliil0i_event)
|
always @(nliiiiO_event)
|
nliil0i <= 1;
|
nliiiiO <= 1;
|
always @(nliil1l_event)
|
always @(nliiill_event)
|
nliil1l <= 1;
|
nliiill <= 1;
|
|
initial
|
|
begin
|
|
nli0i = 0;
|
|
nlili = 0;
|
|
end
|
|
always @ (clk or wire_nliiO_PRN or wire_nliiO_CLRN)
|
|
begin
|
|
if (wire_nliiO_PRN == 1'b0)
|
|
begin
|
|
nli0i <= 1;
|
|
nlili <= 1;
|
|
end
|
|
else if (wire_nliiO_CLRN == 1'b0)
|
|
begin
|
|
nli0i <= 0;
|
|
nlili <= 0;
|
|
end
|
|
else
|
|
if (clk != nliiO_clk_prev && clk == 1'b1)
|
|
begin
|
|
nli0i <= nlii0iO;
|
|
nlili <= nli0i;
|
|
end
|
|
nliiO_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nliiO_CLRN = (nlii0Ol6 ^ nlii0Ol5),
|
|
wire_nliiO_PRN = ((nlii0Oi8 ^ nlii0Oi7) & (~ gxb_pwrdn_in));
|
|
event nli0i_event;
|
|
event nlili_event;
|
|
initial
|
|
#1 ->nli0i_event;
|
|
initial
|
|
#1 ->nlili_event;
|
|
always @(nli0i_event)
|
|
nli0i <= 1;
|
|
always @(nlili_event)
|
|
nlili <= 1;
|
initial
|
initial
|
begin
|
begin
|
nlii0i = 0;
|
nlii0i = 0;
|
nliilO = 0;
|
nliilO = 0;
|
nliiOl = 0;
|
nliiOl = 0;
|
end
|
end
|
always @ (clk or reset or wire_nliiOi_CLRN)
|
always @ ( posedge clk or posedge reset)
|
begin
|
begin
|
if (reset == 1'b1)
|
if (reset == 1'b1)
|
begin
|
begin
|
nlii0i <= 1;
|
nlii0i <= 1;
|
nliilO <= 1;
|
nliilO <= 1;
|
nliiOl <= 1;
|
nliiOl <= 1;
|
end
|
end
|
else if (wire_nliiOi_CLRN == 1'b0)
|
else if (nli1OiO == 1'b1)
|
begin
|
begin
|
nlii0i <= 0;
|
nlii0i <= nlO00O;
|
nliilO <= 0;
|
nliilO <= nlO0il;
|
nliiOl <= 0;
|
nliiOl <= nlO0iO;
|
end
|
end
|
else if (nli01ii == 1'b1)
|
|
if (clk != nliiOi_clk_prev && clk == 1'b1)
|
|
begin
|
|
nlii0i <= nlO1Ol;
|
|
nliilO <= nlO01i;
|
|
nliiOl <= nlO01l;
|
|
end
|
end
|
nliiOi_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nliiOi_CLRN = (nli010l72 ^ nli010l71);
|
|
event nlii0i_event;
|
event nlii0i_event;
|
event nliilO_event;
|
event nliilO_event;
|
event nliiOl_event;
|
event nliiOl_event;
|
initial
|
initial
|
#1 ->nlii0i_event;
|
#1 ->nlii0i_event;
|
| Line 6568... |
Line 6614... |
begin
|
begin
|
nliill = 0;
|
nliill = 0;
|
nliiOO = 0;
|
nliiOO = 0;
|
nlil1l = 0;
|
nlil1l = 0;
|
end
|
end
|
always @ ( posedge clk or negedge wire_nlil1i_CLRN)
|
always @ (clk or wire_nlil1i_PRN or wire_nlil1i_CLRN)
|
begin
|
begin
|
if (wire_nlil1i_CLRN == 1'b0)
|
if (wire_nlil1i_PRN == 1'b0)
|
|
begin
|
|
nliill <= 1;
|
|
nliiOO <= 1;
|
|
nlil1l <= 1;
|
|
end
|
|
else if (wire_nlil1i_CLRN == 1'b0)
|
begin
|
begin
|
nliill <= 0;
|
nliill <= 0;
|
nliiOO <= 0;
|
nliiOO <= 0;
|
nlil1l <= 0;
|
nlil1l <= 0;
|
end
|
end
|
else if (nli01ii == 1'b1)
|
else if (nli1OiO == 1'b1)
|
|
if (clk != nlil1i_clk_prev && clk == 1'b1)
|
begin
|
begin
|
nliill <= nlO1OO;
|
nliill <= nlO0ii;
|
nliiOO <= nlO00O;
|
nliiOO <= nlO0Oi;
|
nlil1l <= nlO0ii;
|
nlil1l <= nlO0Ol;
|
end
|
end
|
|
nlil1i_clk_prev <= clk;
|
end
|
end
|
assign
|
assign
|
wire_nlil1i_CLRN = ((nli010O70 ^ nli010O69) & (~ reset));
|
wire_nlil1i_CLRN = ((nli1Oil72 ^ nli1Oil71) & (~ reset)),
|
|
wire_nlil1i_PRN = (nli1Oii74 ^ nli1Oii73);
|
initial
|
initial
|
begin
|
begin
|
nlilill = 0;
|
nlili0l = 0;
|
nliliOi = 0;
|
nlili1O = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or posedge nliii0i)
|
always @ ( posedge wire_nl0ii_clkout or posedge nlii0ll)
|
begin
|
begin
|
if (nliii0i == 1'b1)
|
if (nlii0ll == 1'b1)
|
begin
|
begin
|
nlilill <= 1;
|
nlili0l <= 1;
|
nliliOi <= 1;
|
nlili1O <= 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
nlilill <= nliliOi;
|
nlili0l <= nlii0iO;
|
nliliOi <= nlii0Oi;
|
nlili1O <= nlili0l;
|
end
|
end
|
end
|
end
|
event nlilill_event;
|
event nlili0l_event;
|
event nliliOi_event;
|
event nlili1O_event;
|
initial
|
|
#1 ->nlilill_event;
|
|
initial
|
initial
|
#1 ->nliliOi_event;
|
#1 ->nlili0l_event;
|
always @(nlilill_event)
|
|
nlilill <= 1;
|
|
always @(nliliOi_event)
|
|
nliliOi <= 1;
|
|
initial
|
initial
|
begin
|
#1 ->nlili1O_event;
|
nliOOi = 0;
|
always @(nlili0l_event)
|
end
|
nlili0l <= 1;
|
always @ (clk or reset or wire_nliOlO_CLRN)
|
always @(nlili1O_event)
|
begin
|
nlili1O <= 1;
|
if (reset == 1'b1)
|
|
begin
|
|
nliOOi <= 1;
|
|
end
|
|
else if (wire_nliOlO_CLRN == 1'b0)
|
|
begin
|
|
nliOOi <= 0;
|
|
end
|
|
else if (nli01lO == 1'b1)
|
|
if (clk != nliOlO_clk_prev && clk == 1'b1)
|
|
begin
|
|
nliOOi <= nlO00O;
|
|
end
|
|
nliOlO_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nliOlO_CLRN = (nli01li68 ^ nli01li67);
|
|
event nliOOi_event;
|
|
initial
|
|
#1 ->nliOOi_event;
|
|
always @(nliOOi_event)
|
|
nliOOi <= 1;
|
|
initial
|
|
begin
|
|
nliOli = 0;
|
|
nliOll = 0;
|
|
nliOOO = 0;
|
|
end
|
|
always @ ( posedge clk or negedge wire_nliOOl_CLRN)
|
|
begin
|
|
if (wire_nliOOl_CLRN == 1'b0)
|
|
begin
|
|
nliOli <= 0;
|
|
nliOll <= 0;
|
|
nliOOO <= 0;
|
|
end
|
|
else if (nli01lO == 1'b1)
|
|
begin
|
|
nliOli <= nlO00i;
|
|
nliOll <= nlO00l;
|
|
nliOOO <= nlO0il;
|
|
end
|
|
end
|
|
assign
|
|
wire_nliOOl_CLRN = ((nli01ll66 ^ nli01ll65) & (~ reset));
|
|
initial
|
initial
|
begin
|
begin
|
n0101i = 0;
|
n010li = 0;
|
n0101l = 0;
|
n010ll = 0;
|
n0110i = 0;
|
n0110i = 0;
|
n0110l = 0;
|
n0110l = 0;
|
n0110O = 0;
|
n0110O = 0;
|
|
n0111i = 0;
|
|
n0111l = 0;
|
|
n0111O = 0;
|
n011ii = 0;
|
n011ii = 0;
|
n011il = 0;
|
n01i0i = 0;
|
n011iO = 0;
|
|
n011li = 0;
|
|
n011ll = 0;
|
|
n011lO = 0;
|
|
n011Oi = 0;
|
|
n011Ol = 0;
|
|
n011OO = 0;
|
|
n01i0l = 0;
|
n01i0l = 0;
|
n01i0O = 0;
|
n01i1i = 0;
|
n01ill = 0;
|
n01i1O = 0;
|
n01iOi = 0;
|
n1i01i = 0;
|
n01iOl = 0;
|
n1i01l = 0;
|
n01iOO = 0;
|
n1i01O = 0;
|
n1i00l = 0;
|
n1i0il = 0;
|
n1i00O = 0;
|
n1i0li = 0;
|
n1i0ii = 0;
|
n1OOiO = 0;
|
n1i0lO = 0;
|
n1OOli = 0;
|
n1i0Ol = 0;
|
n1OOll = 0;
|
|
n1OOlO = 0;
|
|
n1OOOi = 0;
|
|
n1OOOl = 0;
|
|
n1OOOO = 0;
|
nili1l = 0;
|
nili1l = 0;
|
nili1O = 0;
|
nili1O = 0;
|
niliil = 0;
|
niliil = 0;
|
nilill = 0;
|
nilill = 0;
|
nililO = 0;
|
nililO = 0;
|
| Line 6721... |
Line 6725... |
niOiOi = 0;
|
niOiOi = 0;
|
niOiOl = 0;
|
niOiOl = 0;
|
niOiOO = 0;
|
niOiOO = 0;
|
niOl1i = 0;
|
niOl1i = 0;
|
niOl1l = 0;
|
niOl1l = 0;
|
|
nliil1i = 0;
|
|
nliilii = 0;
|
|
nliilil = 0;
|
nliiliO = 0;
|
nliiliO = 0;
|
|
nliilli = 0;
|
|
nliilll = 0;
|
|
nliillO = 0;
|
|
nliilOi = 0;
|
|
nliilOl = 0;
|
nliilOO = 0;
|
nliilOO = 0;
|
nliiO0i = 0;
|
nliiOOi = 0;
|
nliiO0l = 0;
|
nll0iO = 0;
|
nliiO0O = 0;
|
nll0li = 0;
|
nliiO1i = 0;
|
nll0ll = 0;
|
nliiO1l = 0;
|
nll0Oi = 0;
|
nliiO1O = 0;
|
|
nliiOii = 0;
|
|
nliiOil = 0;
|
|
nlil10O = 0;
|
|
nll00i = 0;
|
|
nll00O = 0;
|
|
nll01l = 0;
|
|
nll01O = 0;
|
|
end
|
end
|
always @ ( posedge wire_nl10l_clkout or posedge nliii1O)
|
always @ ( posedge wire_nl00l_clkout or negedge wire_nll0lO_CLRN)
|
begin
|
begin
|
if (nliii1O == 1'b1)
|
if (wire_nll0lO_CLRN == 1'b0)
|
begin
|
begin
|
n0101i <= 0;
|
n010li <= 0;
|
n0101l <= 0;
|
n010ll <= 0;
|
n0110i <= 0;
|
n0110i <= 0;
|
n0110l <= 0;
|
n0110l <= 0;
|
n0110O <= 0;
|
n0110O <= 0;
|
|
n0111i <= 0;
|
|
n0111l <= 0;
|
|
n0111O <= 0;
|
n011ii <= 0;
|
n011ii <= 0;
|
n011il <= 0;
|
n01i0i <= 0;
|
n011iO <= 0;
|
|
n011li <= 0;
|
|
n011ll <= 0;
|
|
n011lO <= 0;
|
|
n011Oi <= 0;
|
|
n011Ol <= 0;
|
|
n011OO <= 0;
|
|
n01i0l <= 0;
|
n01i0l <= 0;
|
n01i0O <= 0;
|
n01i1i <= 0;
|
n01ill <= 0;
|
n01i1O <= 0;
|
n01iOi <= 0;
|
n1i01i <= 0;
|
n01iOl <= 0;
|
n1i01l <= 0;
|
n01iOO <= 0;
|
n1i01O <= 0;
|
n1i00l <= 0;
|
n1i0il <= 0;
|
n1i00O <= 0;
|
n1i0li <= 0;
|
n1i0ii <= 0;
|
n1OOiO <= 0;
|
n1i0lO <= 0;
|
n1OOli <= 0;
|
n1i0Ol <= 0;
|
n1OOll <= 0;
|
|
n1OOlO <= 0;
|
|
n1OOOi <= 0;
|
|
n1OOOl <= 0;
|
|
n1OOOO <= 0;
|
nili1l <= 0;
|
nili1l <= 0;
|
nili1O <= 0;
|
nili1O <= 0;
|
niliil <= 0;
|
niliil <= 0;
|
nilill <= 0;
|
nilill <= 0;
|
nililO <= 0;
|
nililO <= 0;
|
| Line 6796... |
Line 6800... |
niOiOi <= 0;
|
niOiOi <= 0;
|
niOiOl <= 0;
|
niOiOl <= 0;
|
niOiOO <= 0;
|
niOiOO <= 0;
|
niOl1i <= 0;
|
niOl1i <= 0;
|
niOl1l <= 0;
|
niOl1l <= 0;
|
|
nliil1i <= 0;
|
|
nliilii <= 0;
|
|
nliilil <= 0;
|
nliiliO <= 0;
|
nliiliO <= 0;
|
|
nliilli <= 0;
|
|
nliilll <= 0;
|
|
nliillO <= 0;
|
|
nliilOi <= 0;
|
|
nliilOl <= 0;
|
nliilOO <= 0;
|
nliilOO <= 0;
|
nliiO0i <= 0;
|
nliiOOi <= 0;
|
nliiO0l <= 0;
|
nll0iO <= 0;
|
nliiO0O <= 0;
|
nll0li <= 0;
|
nliiO1i <= 0;
|
nll0ll <= 0;
|
nliiO1l <= 0;
|
nll0Oi <= 0;
|
nliiO1O <= 0;
|
|
nliiOii <= 0;
|
|
nliiOil <= 0;
|
|
nlil10O <= 0;
|
|
nll00i <= 0;
|
|
nll00O <= 0;
|
|
nll01l <= 0;
|
|
nll01O <= 0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
n0101i <= wire_n01i1l_dataout;
|
n010li <= wire_n01i1l_dataout;
|
n0101l <= wire_n01i1O_dataout;
|
n010ll <= n010li;
|
n0110i <= wire_n0100l_dataout;
|
n0110i <= wire_n0100l_dataout;
|
n0110l <= wire_n0100O_dataout;
|
n0110l <= wire_n0100O_dataout;
|
n0110O <= wire_n010ii_dataout;
|
n0110O <= wire_n010ii_dataout;
|
|
n0111i <= wire_n0101l_dataout;
|
|
n0111l <= wire_n0101O_dataout;
|
|
n0111O <= wire_n0100i_dataout;
|
n011ii <= wire_n010il_dataout;
|
n011ii <= wire_n010il_dataout;
|
n011il <= wire_n010iO_dataout;
|
n01i0i <= n01i0l;
|
n011iO <= wire_n010li_dataout;
|
n01i0l <= nlOiilO;
|
n011li <= wire_n010ll_dataout;
|
n01i1i <= n01i1O;
|
n011ll <= wire_n010lO_dataout;
|
n01i1O <= nlilOl;
|
n011lO <= wire_n010Oi_dataout;
|
n1i01i <= wire_n1i1iO_dataout;
|
n011Oi <= wire_n010Ol_dataout;
|
n1i01l <= wire_n1i0lO_dataout;
|
n011Ol <= wire_n010OO_dataout;
|
n1i01O <= wire_n1i0Oi_dataout;
|
n011OO <= wire_n01i1i_dataout;
|
n1i0il <= wire_n1ii1O_dataout;
|
n01i0l <= wire_n01ilO_dataout;
|
n1i0li <= wire_n011iO_dataout;
|
n01i0O <= n01i0l;
|
n1OOiO <= wire_n011li_dataout;
|
n01ill <= n01iOi;
|
n1OOli <= wire_n011ll_dataout;
|
n01iOi <= nlilOl;
|
n1OOll <= wire_n011lO_dataout;
|
n01iOl <= n01iOO;
|
n1OOlO <= wire_n011Oi_dataout;
|
n01iOO <= nlOil1i;
|
n1OOOi <= wire_n011Ol_dataout;
|
n1i00l <= wire_n1i1Oi_dataout;
|
n1OOOl <= wire_n011OO_dataout;
|
n1i00O <= wire_n1ii1i_dataout;
|
n1OOOO <= wire_n0101i_dataout;
|
n1i0ii <= wire_n1ii1l_dataout;
|
|
n1i0lO <= wire_n1iiii_dataout;
|
|
n1i0Ol <= wire_n0100i_dataout;
|
|
nili1l <= (~ ((~ (niO01O ^ niO01i)) & (~ (niO00i ^ niO01l))));
|
nili1l <= (~ ((~ (niO01O ^ niO01i)) & (~ (niO00i ^ niO01l))));
|
nili1O <= (~ ((~ (niO1lO ^ niO1il)) & (~ (niO1Oi ^ niO1ll))));
|
nili1O <= (~ ((~ (niO1lO ^ niO1il)) & (~ (niO1Oi ^ niO1ll))));
|
niliil <= wire_nill0O_dataout;
|
niliil <= wire_nill0O_dataout;
|
nilill <= wire_nillii_dataout;
|
nilill <= wire_nillii_dataout;
|
nililO <= wire_nillil_dataout;
|
nililO <= wire_nillil_dataout;
|
| Line 6868... |
Line 6872... |
niOill <= niOiOi;
|
niOill <= niOiOi;
|
niOiOi <= nl011l;
|
niOiOi <= nl011l;
|
niOiOl <= niOiOO;
|
niOiOl <= niOiOO;
|
niOiOO <= nlilOl;
|
niOiOO <= nlilOl;
|
niOl1i <= niOl1l;
|
niOl1i <= niOl1l;
|
niOl1l <= nlOl10l;
|
niOl1l <= nlOl11i;
|
nliiliO <= wire_nliiOiO_dataout;
|
nliil1i <= wire_nliiO1i_dataout;
|
nliilOO <= wire_nliiOli_dataout;
|
nliilii <= wire_nliiO1l_dataout;
|
nliiO0i <= wire_nliiOOl_dataout;
|
nliilil <= wire_nliiO1O_dataout;
|
nliiO0l <= wire_nlil11i_dataout;
|
nliiliO <= wire_nliiO0i_dataout;
|
nliiO0O <= wire_nlil11l_dataout;
|
nliilli <= wire_nliiO0l_dataout;
|
nliiO1i <= wire_nliiOll_dataout;
|
nliilll <= wire_nliiO0O_dataout;
|
nliiO1l <= wire_nliiOlO_dataout;
|
nliillO <= wire_nliiOil_dataout;
|
nliiO1O <= wire_nliiOOi_dataout;
|
nliilOi <= wire_nliiOiO_dataout;
|
nliiOii <= wire_nlil11O_dataout;
|
nliilOl <= wire_nliiOli_dataout;
|
nliiOil <= nlil10O;
|
nliilOO <= nliiOOi;
|
nlil10O <= nl011O;
|
nliiOOi <= nl011O;
|
nll00i <= (nll0li & nll00O);
|
nll0iO <= nll0li;
|
nll00O <= nll0li;
|
nll0li <= nll0ll;
|
nll01l <= nll01O;
|
nll0ll <= (nlli1l & nll0Oi);
|
nll01O <= nll00i;
|
nll0Oi <= nlli1l;
|
end
|
end
|
end
|
end
|
|
assign
|
|
wire_nll0lO_CLRN = ((nli011l64 ^ nli011l63) & (~ nlii0li));
|
|
initial
|
|
begin
|
|
nll10l = 0;
|
|
end
|
|
always @ (clk or wire_nll10i_PRN or wire_nll10i_CLRN)
|
|
begin
|
|
if (wire_nll10i_PRN == 1'b0)
|
|
begin
|
|
nll10l <= 1;
|
|
end
|
|
else if (wire_nll10i_CLRN == 1'b0)
|
|
begin
|
|
nll10l <= 0;
|
|
end
|
|
else if (nli1OOO == 1'b1)
|
|
if (clk != nll10i_clk_prev && clk == 1'b1)
|
|
begin
|
|
nll10l <= nlO0Oi;
|
|
end
|
|
nll10i_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nll10i_CLRN = (nli1OOi68 ^ nli1OOi67),
|
|
wire_nll10i_PRN = ((nli1OlO70 ^ nli1OlO69) & (~ reset));
|
|
event nll10l_event;
|
|
initial
|
|
#1 ->nll10l_event;
|
|
always @(nll10l_event)
|
|
nll10l <= 1;
|
|
initial
|
|
begin
|
|
nliOiO = 0;
|
|
nll11l = 0;
|
|
nll11O = 0;
|
|
nll1ii = 0;
|
|
end
|
|
always @ (clk or wire_nll10O_PRN or reset)
|
|
begin
|
|
if (wire_nll10O_PRN == 1'b0)
|
|
begin
|
|
nliOiO <= 1;
|
|
nll11l <= 1;
|
|
nll11O <= 1;
|
|
nll1ii <= 1;
|
|
end
|
|
else if (reset == 1'b1)
|
|
begin
|
|
nliOiO <= 0;
|
|
nll11l <= 0;
|
|
nll11O <= 0;
|
|
nll1ii <= 0;
|
|
end
|
|
else if (nli1OOO == 1'b1)
|
|
if (clk != nll10O_clk_prev && clk == 1'b1)
|
|
begin
|
|
nliOiO <= nlO00O;
|
|
nll11l <= nlO0ll;
|
|
nll11O <= nlO0lO;
|
|
nll1ii <= nlO0OO;
|
|
end
|
|
nll10O_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nll10O_PRN = (nli1OOl66 ^ nli1OOl65);
|
initial
|
initial
|
begin
|
begin
|
n0O11l = 0;
|
n0O11l = 0;
|
n0Oi0i = 0;
|
n0Oi0i = 0;
|
n1010i = 0;
|
n1010i = 0;
|
| Line 6900... |
Line 6970... |
n1011O = 0;
|
n1011O = 0;
|
n101ii = 0;
|
n101ii = 0;
|
n101il = 0;
|
n101il = 0;
|
n101iO = 0;
|
n101iO = 0;
|
n101li = 0;
|
n101li = 0;
|
n101ll = 0;
|
n10l0i = 0;
|
n101lO = 0;
|
n10l0l = 0;
|
n101Oi = 0;
|
n10l0O = 0;
|
n101Ol = 0;
|
n10lii = 0;
|
n10lil = 0;
|
n10lil = 0;
|
n10liO = 0;
|
n10liO = 0;
|
n10lli = 0;
|
n10lli = 0;
|
n10lll = 0;
|
n10lll = 0;
|
n10llO = 0;
|
n10llO = 0;
|
n10lOi = 0;
|
n10lOi = 0;
|
n10lOl = 0;
|
n10lOl = 0;
|
n10lOO = 0;
|
n10lOO = 0;
|
n10O0i = 0;
|
n10OlO = 0;
|
n10O1i = 0;
|
n10OOi = 0;
|
n10O1l = 0;
|
n11OiO = 0;
|
n10O1O = 0;
|
n11Oli = 0;
|
|
n11Oll = 0;
|
|
n11OlO = 0;
|
n11OOi = 0;
|
n11OOi = 0;
|
n11OOl = 0;
|
n11OOl = 0;
|
n11OOO = 0;
|
n11OOO = 0;
|
n1i10O = 0;
|
|
n1i11i = 0;
|
|
n1i11l = 0;
|
n1i11l = 0;
|
nl011i = 0;
|
nl011i = 0;
|
nl1l0O = 0;
|
nl1l0O = 0;
|
nl1Oil = 0;
|
nl1Oil = 0;
|
nl1OiO = 0;
|
nl1OiO = 0;
|
| Line 6935... |
Line 7005... |
nl1OOl = 0;
|
nl1OOl = 0;
|
nl1OOO = 0;
|
nl1OOO = 0;
|
nli1lO = 0;
|
nli1lO = 0;
|
nli1Oi = 0;
|
nli1Oi = 0;
|
nli1Ol = 0;
|
nli1Ol = 0;
|
|
nliOlOi = 0;
|
nliOO0l = 0;
|
nliOO0l = 0;
|
|
nliOOiO = 0;
|
|
nliOOli = 0;
|
|
nliOOll = 0;
|
nliOOlO = 0;
|
nliOOlO = 0;
|
nll000i = 0;
|
nliOOOi = 0;
|
nll00ii = 0;
|
nliOOOl = 0;
|
nll00il = 0;
|
nliOOOO = 0;
|
nll00iO = 0;
|
nll001i = 0;
|
|
nll001l = 0;
|
|
nll010l = 0;
|
|
nll010O = 0;
|
|
nll01il = 0;
|
nll01lO = 0;
|
nll01lO = 0;
|
nll01Oi = 0;
|
|
nll01OO = 0;
|
nll01OO = 0;
|
nll0iiO = 0;
|
nll0i0l = 0;
|
nll0ili = 0;
|
nll0i0O = 0;
|
|
nll0i1l = 0;
|
|
nll0ill = 0;
|
|
nll0ilO = 0;
|
|
nll0iOi = 0;
|
|
nll0iOl = 0;
|
nll0iOO = 0;
|
nll0iOO = 0;
|
nll0l0i = 0;
|
nll0l0i = 0;
|
nll0l0l = 0;
|
nll0l0l = 0;
|
nll0l0O = 0;
|
nll0l0O = 0;
|
nll0l1i = 0;
|
nll0l1i = 0;
|
nll0l1l = 0;
|
nll0l1l = 0;
|
nll0l1O = 0;
|
nll0l1O = 0;
|
nll0lii = 0;
|
nll0lii = 0;
|
nll0lil = 0;
|
nll0lil = 0;
|
nll0liO = 0;
|
nll0liO = 0;
|
nll0ll = 0;
|
|
nll0lli = 0;
|
nll0lli = 0;
|
nll0lll = 0;
|
nll0lll = 0;
|
nll0llO = 0;
|
|
nll0lOi = 0;
|
|
nll0lOl = 0;
|
|
nll0lOO = 0;
|
|
nll0Oi = 0;
|
|
nll0OO = 0;
|
|
nll100i = 0;
|
|
nll100l = 0;
|
|
nll100O = 0;
|
|
nll101i = 0;
|
|
nll101l = 0;
|
|
nll101O = 0;
|
|
nll10ii = 0;
|
|
nll110i = 0;
|
nll110i = 0;
|
nll110l = 0;
|
nll110l = 0;
|
nll110O = 0;
|
nll110O = 0;
|
nll111i = 0;
|
nll111i = 0;
|
nll111l = 0;
|
nll111l = 0;
|
| Line 6987... |
Line 7055... |
nll11ll = 0;
|
nll11ll = 0;
|
nll11lO = 0;
|
nll11lO = 0;
|
nll11Oi = 0;
|
nll11Oi = 0;
|
nll11Ol = 0;
|
nll11Ol = 0;
|
nll11OO = 0;
|
nll11OO = 0;
|
nlli1i = 0;
|
nlli0l = 0;
|
nlli1O = 0;
|
nlli1O = 0;
|
|
nlliii = 0;
|
|
nlliil = 0;
|
nllil0l = 0;
|
nllil0l = 0;
|
|
nllil0O = 0;
|
|
nllil1i = 0;
|
|
nllili = 0;
|
|
nllilii = 0;
|
|
nllilil = 0;
|
nlliliO = 0;
|
nlliliO = 0;
|
nllilli = 0;
|
nllilli = 0;
|
nllilll = 0;
|
nllilll = 0;
|
nllillO = 0;
|
nllillO = 0;
|
nllilOi = 0;
|
nllilOi = 0;
|
| Line 7007... |
Line 7082... |
nlliO1O = 0;
|
nlliO1O = 0;
|
nlliOii = 0;
|
nlliOii = 0;
|
nlliOil = 0;
|
nlliOil = 0;
|
nlliOiO = 0;
|
nlliOiO = 0;
|
nlliOli = 0;
|
nlliOli = 0;
|
nlliOll = 0;
|
nllO1lO = 0;
|
nlliOlO = 0;
|
nllO1Oi = 0;
|
nlliOOi = 0;
|
nllO1Ol = 0;
|
nlliOOl = 0;
|
nllOi0i = 0;
|
nllO01i = 0;
|
nllOi0l = 0;
|
nllO01l = 0;
|
nllOi1l = 0;
|
nllO01O = 0;
|
nllOi1O = 0;
|
nllOi0O = 0;
|
nllOO0i = 0;
|
nllOiii = 0;
|
|
nllOiil = 0;
|
|
nllOiiO = 0;
|
|
nllOO0l = 0;
|
nllOO0l = 0;
|
nllOO0O = 0;
|
nllOO0O = 0;
|
|
nllOO1i = 0;
|
|
nllOO1l = 0;
|
|
nllOO1O = 0;
|
nllOOii = 0;
|
nllOOii = 0;
|
nllOOil = 0;
|
nllOOil = 0;
|
nllOOiO = 0;
|
nllOOiO = 0;
|
nllOOli = 0;
|
nllOOli = 0;
|
nllOOll = 0;
|
nllOOll = 0;
|
nllOOlO = 0;
|
nllOOlO = 0;
|
nllOOOi = 0;
|
nllOOOi = 0;
|
nllOOOl = 0;
|
nllOOOl = 0;
|
nllOOOO = 0;
|
nllOOOO = 0;
|
nlO100i = 0;
|
|
nlO100l = 0;
|
|
nlO100O = 0;
|
|
nlO101i = 0;
|
nlO101i = 0;
|
nlO101l = 0;
|
nlO101l = 0;
|
nlO101O = 0;
|
|
nlO110i = 0;
|
nlO110i = 0;
|
nlO110l = 0;
|
nlO110l = 0;
|
nlO110O = 0;
|
nlO110O = 0;
|
nlO111i = 0;
|
nlO111i = 0;
|
nlO111l = 0;
|
nlO111l = 0;
|
| Line 7050... |
Line 7121... |
nlO11ll = 0;
|
nlO11ll = 0;
|
nlO11lO = 0;
|
nlO11lO = 0;
|
nlO11Oi = 0;
|
nlO11Oi = 0;
|
nlO11Ol = 0;
|
nlO11Ol = 0;
|
nlO11OO = 0;
|
nlO11OO = 0;
|
nlOi00i = 0;
|
|
nlOi00l = 0;
|
|
nlOi01i = 0;
|
nlOi01i = 0;
|
nlOi01l = 0;
|
|
nlOi01O = 0;
|
nlOi01O = 0;
|
nlOi0ii = 0;
|
nlOi1ll = 0;
|
|
nlOi1lO = 0;
|
|
nlOi1Oi = 0;
|
|
nlOi1Ol = 0;
|
nlOi1OO = 0;
|
nlOi1OO = 0;
|
nlOil1i = 0;
|
nlOiilO = 0;
|
nlOil1l = 0;
|
nlOiiOi = 0;
|
|
nlOil0l = 0;
|
|
nlOil0O = 0;
|
|
nlOilii = 0;
|
|
nlOilil = 0;
|
nlOiliO = 0;
|
nlOiliO = 0;
|
nlOilli = 0;
|
nlOilli = 0;
|
nlOilll = 0;
|
nlOilll = 0;
|
nlOillO = 0;
|
nlOillO = 0;
|
nlOilOi = 0;
|
nlOilOi = 0;
|
| Line 7082... |
Line 7157... |
nlOiOlO = 0;
|
nlOiOlO = 0;
|
nlOiOOi = 0;
|
nlOiOOi = 0;
|
nlOiOOl = 0;
|
nlOiOOl = 0;
|
nlOiOOO = 0;
|
nlOiOOO = 0;
|
nlOl10i = 0;
|
nlOl10i = 0;
|
nlOl10l = 0;
|
|
nlOl10O = 0;
|
|
nlOl11i = 0;
|
nlOl11i = 0;
|
nlOl11l = 0;
|
nlOl11l = 0;
|
nlOl11O = 0;
|
nlOl11O = 0;
|
nlOl1ii = 0;
|
nlOlOlO = 0;
|
nlOl1il = 0;
|
|
nlOO00i = 0;
|
nlOO00i = 0;
|
nlOO00l = 0;
|
|
nlOO00O = 0;
|
|
nlOO01i = 0;
|
nlOO01i = 0;
|
nlOO01l = 0;
|
nlOO01l = 0;
|
nlOO01O = 0;
|
nlOO01O = 0;
|
nlOO0ii = 0;
|
nlOO10i = 0;
|
nlOO0il = 0;
|
nlOO10l = 0;
|
nlOO10O = 0;
|
nlOO10O = 0;
|
nlOO11i = 0;
|
nlOO11l = 0;
|
|
nlOO1ii = 0;
|
nlOO1il = 0;
|
nlOO1il = 0;
|
nlOO1iO = 0;
|
nlOO1iO = 0;
|
nlOO1li = 0;
|
nlOO1li = 0;
|
nlOO1ll = 0;
|
nlOO1ll = 0;
|
nlOO1lO = 0;
|
nlOO1lO = 0;
|
nlOO1Oi = 0;
|
nlOO1Oi = 0;
|
nlOO1Ol = 0;
|
nlOO1Ol = 0;
|
nlOO1OO = 0;
|
nlOO1OO = 0;
|
nlOOO0i = 0;
|
nlOOlOO = 0;
|
end
|
end
|
always @ ( posedge wire_nl1ii_clkout or negedge wire_nlli1l_CLRN)
|
always @ (wire_nl0ii_clkout or wire_nlliiO_PRN or wire_nlliiO_CLRN)
|
begin
|
begin
|
if (wire_nlli1l_CLRN == 1'b0)
|
if (wire_nlliiO_PRN == 1'b0)
|
|
begin
|
|
n0O11l <= 1;
|
|
n0Oi0i <= 1;
|
|
n1010i <= 1;
|
|
n1010l <= 1;
|
|
n1010O <= 1;
|
|
n1011i <= 1;
|
|
n1011l <= 1;
|
|
n1011O <= 1;
|
|
n101ii <= 1;
|
|
n101il <= 1;
|
|
n101iO <= 1;
|
|
n101li <= 1;
|
|
n10l0i <= 1;
|
|
n10l0l <= 1;
|
|
n10l0O <= 1;
|
|
n10lii <= 1;
|
|
n10lil <= 1;
|
|
n10liO <= 1;
|
|
n10lli <= 1;
|
|
n10lll <= 1;
|
|
n10llO <= 1;
|
|
n10lOi <= 1;
|
|
n10lOl <= 1;
|
|
n10lOO <= 1;
|
|
n10OlO <= 1;
|
|
n10OOi <= 1;
|
|
n11OiO <= 1;
|
|
n11Oli <= 1;
|
|
n11Oll <= 1;
|
|
n11OlO <= 1;
|
|
n11OOi <= 1;
|
|
n11OOl <= 1;
|
|
n11OOO <= 1;
|
|
n1i11l <= 1;
|
|
nl011i <= 1;
|
|
nl1l0O <= 1;
|
|
nl1Oil <= 1;
|
|
nl1OiO <= 1;
|
|
nl1Oli <= 1;
|
|
nl1Oll <= 1;
|
|
nl1OlO <= 1;
|
|
nl1OOi <= 1;
|
|
nl1OOl <= 1;
|
|
nl1OOO <= 1;
|
|
nli1lO <= 1;
|
|
nli1Oi <= 1;
|
|
nli1Ol <= 1;
|
|
nliOlOi <= 1;
|
|
nliOO0l <= 1;
|
|
nliOOiO <= 1;
|
|
nliOOli <= 1;
|
|
nliOOll <= 1;
|
|
nliOOlO <= 1;
|
|
nliOOOi <= 1;
|
|
nliOOOl <= 1;
|
|
nliOOOO <= 1;
|
|
nll001i <= 1;
|
|
nll001l <= 1;
|
|
nll010l <= 1;
|
|
nll010O <= 1;
|
|
nll01il <= 1;
|
|
nll01lO <= 1;
|
|
nll01OO <= 1;
|
|
nll0i0l <= 1;
|
|
nll0i0O <= 1;
|
|
nll0i1l <= 1;
|
|
nll0ill <= 1;
|
|
nll0ilO <= 1;
|
|
nll0iOi <= 1;
|
|
nll0iOl <= 1;
|
|
nll0iOO <= 1;
|
|
nll0l0i <= 1;
|
|
nll0l0l <= 1;
|
|
nll0l0O <= 1;
|
|
nll0l1i <= 1;
|
|
nll0l1l <= 1;
|
|
nll0l1O <= 1;
|
|
nll0lii <= 1;
|
|
nll0lil <= 1;
|
|
nll0liO <= 1;
|
|
nll0lli <= 1;
|
|
nll0lll <= 1;
|
|
nll110i <= 1;
|
|
nll110l <= 1;
|
|
nll110O <= 1;
|
|
nll111i <= 1;
|
|
nll111l <= 1;
|
|
nll111O <= 1;
|
|
nll11ii <= 1;
|
|
nll11il <= 1;
|
|
nll11iO <= 1;
|
|
nll11li <= 1;
|
|
nll11ll <= 1;
|
|
nll11lO <= 1;
|
|
nll11Oi <= 1;
|
|
nll11Ol <= 1;
|
|
nll11OO <= 1;
|
|
nlli0l <= 1;
|
|
nlli1O <= 1;
|
|
nlliii <= 1;
|
|
nlliil <= 1;
|
|
nllil0l <= 1;
|
|
nllil0O <= 1;
|
|
nllil1i <= 1;
|
|
nllili <= 1;
|
|
nllilii <= 1;
|
|
nllilil <= 1;
|
|
nlliliO <= 1;
|
|
nllilli <= 1;
|
|
nllilll <= 1;
|
|
nllillO <= 1;
|
|
nllilOi <= 1;
|
|
nllilOl <= 1;
|
|
nllilOO <= 1;
|
|
nlliO0i <= 1;
|
|
nlliO0l <= 1;
|
|
nlliO0O <= 1;
|
|
nlliO1i <= 1;
|
|
nlliO1l <= 1;
|
|
nlliO1O <= 1;
|
|
nlliOii <= 1;
|
|
nlliOil <= 1;
|
|
nlliOiO <= 1;
|
|
nlliOli <= 1;
|
|
nllO1lO <= 1;
|
|
nllO1Oi <= 1;
|
|
nllO1Ol <= 1;
|
|
nllOi0i <= 1;
|
|
nllOi0l <= 1;
|
|
nllOi1l <= 1;
|
|
nllOi1O <= 1;
|
|
nllOO0i <= 1;
|
|
nllOO0l <= 1;
|
|
nllOO0O <= 1;
|
|
nllOO1i <= 1;
|
|
nllOO1l <= 1;
|
|
nllOO1O <= 1;
|
|
nllOOii <= 1;
|
|
nllOOil <= 1;
|
|
nllOOiO <= 1;
|
|
nllOOli <= 1;
|
|
nllOOll <= 1;
|
|
nllOOlO <= 1;
|
|
nllOOOi <= 1;
|
|
nllOOOl <= 1;
|
|
nllOOOO <= 1;
|
|
nlO101i <= 1;
|
|
nlO101l <= 1;
|
|
nlO110i <= 1;
|
|
nlO110l <= 1;
|
|
nlO110O <= 1;
|
|
nlO111i <= 1;
|
|
nlO111l <= 1;
|
|
nlO111O <= 1;
|
|
nlO11ii <= 1;
|
|
nlO11il <= 1;
|
|
nlO11iO <= 1;
|
|
nlO11li <= 1;
|
|
nlO11ll <= 1;
|
|
nlO11lO <= 1;
|
|
nlO11Oi <= 1;
|
|
nlO11Ol <= 1;
|
|
nlO11OO <= 1;
|
|
nlOi01i <= 1;
|
|
nlOi01O <= 1;
|
|
nlOi1ll <= 1;
|
|
nlOi1lO <= 1;
|
|
nlOi1Oi <= 1;
|
|
nlOi1Ol <= 1;
|
|
nlOi1OO <= 1;
|
|
nlOiilO <= 1;
|
|
nlOiiOi <= 1;
|
|
nlOil0l <= 1;
|
|
nlOil0O <= 1;
|
|
nlOilii <= 1;
|
|
nlOilil <= 1;
|
|
nlOiliO <= 1;
|
|
nlOilli <= 1;
|
|
nlOilll <= 1;
|
|
nlOillO <= 1;
|
|
nlOilOi <= 1;
|
|
nlOilOl <= 1;
|
|
nlOilOO <= 1;
|
|
nlOiO0i <= 1;
|
|
nlOiO0l <= 1;
|
|
nlOiO0O <= 1;
|
|
nlOiO1i <= 1;
|
|
nlOiO1l <= 1;
|
|
nlOiO1O <= 1;
|
|
nlOiOii <= 1;
|
|
nlOiOil <= 1;
|
|
nlOiOiO <= 1;
|
|
nlOiOli <= 1;
|
|
nlOiOll <= 1;
|
|
nlOiOlO <= 1;
|
|
nlOiOOi <= 1;
|
|
nlOiOOl <= 1;
|
|
nlOiOOO <= 1;
|
|
nlOl10i <= 1;
|
|
nlOl11i <= 1;
|
|
nlOl11l <= 1;
|
|
nlOl11O <= 1;
|
|
nlOlOlO <= 1;
|
|
nlOO00i <= 1;
|
|
nlOO01i <= 1;
|
|
nlOO01l <= 1;
|
|
nlOO01O <= 1;
|
|
nlOO10i <= 1;
|
|
nlOO10l <= 1;
|
|
nlOO10O <= 1;
|
|
nlOO11l <= 1;
|
|
nlOO1ii <= 1;
|
|
nlOO1il <= 1;
|
|
nlOO1iO <= 1;
|
|
nlOO1li <= 1;
|
|
nlOO1ll <= 1;
|
|
nlOO1lO <= 1;
|
|
nlOO1Oi <= 1;
|
|
nlOO1Ol <= 1;
|
|
nlOO1OO <= 1;
|
|
nlOOlOO <= 1;
|
|
end
|
|
else if (wire_nlliiO_CLRN == 1'b0)
|
begin
|
begin
|
n0O11l <= 0;
|
n0O11l <= 0;
|
n0Oi0i <= 0;
|
n0Oi0i <= 0;
|
n1010i <= 0;
|
n1010i <= 0;
|
n1010l <= 0;
|
n1010l <= 0;
|
| Line 7125... |
Line 7420... |
n1011O <= 0;
|
n1011O <= 0;
|
n101ii <= 0;
|
n101ii <= 0;
|
n101il <= 0;
|
n101il <= 0;
|
n101iO <= 0;
|
n101iO <= 0;
|
n101li <= 0;
|
n101li <= 0;
|
n101ll <= 0;
|
n10l0i <= 0;
|
n101lO <= 0;
|
n10l0l <= 0;
|
n101Oi <= 0;
|
n10l0O <= 0;
|
n101Ol <= 0;
|
n10lii <= 0;
|
n10lil <= 0;
|
n10lil <= 0;
|
n10liO <= 0;
|
n10liO <= 0;
|
n10lli <= 0;
|
n10lli <= 0;
|
n10lll <= 0;
|
n10lll <= 0;
|
n10llO <= 0;
|
n10llO <= 0;
|
n10lOi <= 0;
|
n10lOi <= 0;
|
n10lOl <= 0;
|
n10lOl <= 0;
|
n10lOO <= 0;
|
n10lOO <= 0;
|
n10O0i <= 0;
|
n10OlO <= 0;
|
n10O1i <= 0;
|
n10OOi <= 0;
|
n10O1l <= 0;
|
n11OiO <= 0;
|
n10O1O <= 0;
|
n11Oli <= 0;
|
|
n11Oll <= 0;
|
|
n11OlO <= 0;
|
n11OOi <= 0;
|
n11OOi <= 0;
|
n11OOl <= 0;
|
n11OOl <= 0;
|
n11OOO <= 0;
|
n11OOO <= 0;
|
n1i10O <= 0;
|
|
n1i11i <= 0;
|
|
n1i11l <= 0;
|
n1i11l <= 0;
|
nl011i <= 0;
|
nl011i <= 0;
|
nl1l0O <= 0;
|
nl1l0O <= 0;
|
nl1Oil <= 0;
|
nl1Oil <= 0;
|
nl1OiO <= 0;
|
nl1OiO <= 0;
|
| Line 7160... |
Line 7455... |
nl1OOl <= 0;
|
nl1OOl <= 0;
|
nl1OOO <= 0;
|
nl1OOO <= 0;
|
nli1lO <= 0;
|
nli1lO <= 0;
|
nli1Oi <= 0;
|
nli1Oi <= 0;
|
nli1Ol <= 0;
|
nli1Ol <= 0;
|
|
nliOlOi <= 0;
|
nliOO0l <= 0;
|
nliOO0l <= 0;
|
|
nliOOiO <= 0;
|
|
nliOOli <= 0;
|
|
nliOOll <= 0;
|
nliOOlO <= 0;
|
nliOOlO <= 0;
|
nll000i <= 0;
|
nliOOOi <= 0;
|
nll00ii <= 0;
|
nliOOOl <= 0;
|
nll00il <= 0;
|
nliOOOO <= 0;
|
nll00iO <= 0;
|
nll001i <= 0;
|
|
nll001l <= 0;
|
|
nll010l <= 0;
|
|
nll010O <= 0;
|
|
nll01il <= 0;
|
nll01lO <= 0;
|
nll01lO <= 0;
|
nll01Oi <= 0;
|
|
nll01OO <= 0;
|
nll01OO <= 0;
|
nll0iiO <= 0;
|
nll0i0l <= 0;
|
nll0ili <= 0;
|
nll0i0O <= 0;
|
|
nll0i1l <= 0;
|
|
nll0ill <= 0;
|
|
nll0ilO <= 0;
|
|
nll0iOi <= 0;
|
|
nll0iOl <= 0;
|
nll0iOO <= 0;
|
nll0iOO <= 0;
|
nll0l0i <= 0;
|
nll0l0i <= 0;
|
nll0l0l <= 0;
|
nll0l0l <= 0;
|
nll0l0O <= 0;
|
nll0l0O <= 0;
|
nll0l1i <= 0;
|
nll0l1i <= 0;
|
nll0l1l <= 0;
|
nll0l1l <= 0;
|
nll0l1O <= 0;
|
nll0l1O <= 0;
|
nll0lii <= 0;
|
nll0lii <= 0;
|
nll0lil <= 0;
|
nll0lil <= 0;
|
nll0liO <= 0;
|
nll0liO <= 0;
|
nll0ll <= 0;
|
|
nll0lli <= 0;
|
nll0lli <= 0;
|
nll0lll <= 0;
|
nll0lll <= 0;
|
nll0llO <= 0;
|
|
nll0lOi <= 0;
|
|
nll0lOl <= 0;
|
|
nll0lOO <= 0;
|
|
nll0Oi <= 0;
|
|
nll0OO <= 0;
|
|
nll100i <= 0;
|
|
nll100l <= 0;
|
|
nll100O <= 0;
|
|
nll101i <= 0;
|
|
nll101l <= 0;
|
|
nll101O <= 0;
|
|
nll10ii <= 0;
|
|
nll110i <= 0;
|
nll110i <= 0;
|
nll110l <= 0;
|
nll110l <= 0;
|
nll110O <= 0;
|
nll110O <= 0;
|
nll111i <= 0;
|
nll111i <= 0;
|
nll111l <= 0;
|
nll111l <= 0;
|
| Line 7212... |
Line 7505... |
nll11ll <= 0;
|
nll11ll <= 0;
|
nll11lO <= 0;
|
nll11lO <= 0;
|
nll11Oi <= 0;
|
nll11Oi <= 0;
|
nll11Ol <= 0;
|
nll11Ol <= 0;
|
nll11OO <= 0;
|
nll11OO <= 0;
|
nlli1i <= 0;
|
nlli0l <= 0;
|
nlli1O <= 0;
|
nlli1O <= 0;
|
|
nlliii <= 0;
|
|
nlliil <= 0;
|
nllil0l <= 0;
|
nllil0l <= 0;
|
|
nllil0O <= 0;
|
|
nllil1i <= 0;
|
|
nllili <= 0;
|
|
nllilii <= 0;
|
|
nllilil <= 0;
|
nlliliO <= 0;
|
nlliliO <= 0;
|
nllilli <= 0;
|
nllilli <= 0;
|
nllilll <= 0;
|
nllilll <= 0;
|
nllillO <= 0;
|
nllillO <= 0;
|
nllilOi <= 0;
|
nllilOi <= 0;
|
| Line 7232... |
Line 7532... |
nlliO1O <= 0;
|
nlliO1O <= 0;
|
nlliOii <= 0;
|
nlliOii <= 0;
|
nlliOil <= 0;
|
nlliOil <= 0;
|
nlliOiO <= 0;
|
nlliOiO <= 0;
|
nlliOli <= 0;
|
nlliOli <= 0;
|
nlliOll <= 0;
|
nllO1lO <= 0;
|
nlliOlO <= 0;
|
nllO1Oi <= 0;
|
nlliOOi <= 0;
|
nllO1Ol <= 0;
|
nlliOOl <= 0;
|
nllOi0i <= 0;
|
nllO01i <= 0;
|
nllOi0l <= 0;
|
nllO01l <= 0;
|
nllOi1l <= 0;
|
nllO01O <= 0;
|
nllOi1O <= 0;
|
nllOi0O <= 0;
|
nllOO0i <= 0;
|
nllOiii <= 0;
|
|
nllOiil <= 0;
|
|
nllOiiO <= 0;
|
|
nllOO0l <= 0;
|
nllOO0l <= 0;
|
nllOO0O <= 0;
|
nllOO0O <= 0;
|
|
nllOO1i <= 0;
|
|
nllOO1l <= 0;
|
|
nllOO1O <= 0;
|
nllOOii <= 0;
|
nllOOii <= 0;
|
nllOOil <= 0;
|
nllOOil <= 0;
|
nllOOiO <= 0;
|
nllOOiO <= 0;
|
nllOOli <= 0;
|
nllOOli <= 0;
|
nllOOll <= 0;
|
nllOOll <= 0;
|
nllOOlO <= 0;
|
nllOOlO <= 0;
|
nllOOOi <= 0;
|
nllOOOi <= 0;
|
nllOOOl <= 0;
|
nllOOOl <= 0;
|
nllOOOO <= 0;
|
nllOOOO <= 0;
|
nlO100i <= 0;
|
|
nlO100l <= 0;
|
|
nlO100O <= 0;
|
|
nlO101i <= 0;
|
nlO101i <= 0;
|
nlO101l <= 0;
|
nlO101l <= 0;
|
nlO101O <= 0;
|
|
nlO110i <= 0;
|
nlO110i <= 0;
|
nlO110l <= 0;
|
nlO110l <= 0;
|
nlO110O <= 0;
|
nlO110O <= 0;
|
nlO111i <= 0;
|
nlO111i <= 0;
|
nlO111l <= 0;
|
nlO111l <= 0;
|
| Line 7275... |
Line 7571... |
nlO11ll <= 0;
|
nlO11ll <= 0;
|
nlO11lO <= 0;
|
nlO11lO <= 0;
|
nlO11Oi <= 0;
|
nlO11Oi <= 0;
|
nlO11Ol <= 0;
|
nlO11Ol <= 0;
|
nlO11OO <= 0;
|
nlO11OO <= 0;
|
nlOi00i <= 0;
|
|
nlOi00l <= 0;
|
|
nlOi01i <= 0;
|
nlOi01i <= 0;
|
nlOi01l <= 0;
|
|
nlOi01O <= 0;
|
nlOi01O <= 0;
|
nlOi0ii <= 0;
|
nlOi1ll <= 0;
|
|
nlOi1lO <= 0;
|
|
nlOi1Oi <= 0;
|
|
nlOi1Ol <= 0;
|
nlOi1OO <= 0;
|
nlOi1OO <= 0;
|
nlOil1i <= 0;
|
nlOiilO <= 0;
|
nlOil1l <= 0;
|
nlOiiOi <= 0;
|
|
nlOil0l <= 0;
|
|
nlOil0O <= 0;
|
|
nlOilii <= 0;
|
|
nlOilil <= 0;
|
nlOiliO <= 0;
|
nlOiliO <= 0;
|
nlOilli <= 0;
|
nlOilli <= 0;
|
nlOilll <= 0;
|
nlOilll <= 0;
|
nlOillO <= 0;
|
nlOillO <= 0;
|
nlOilOi <= 0;
|
nlOilOi <= 0;
|
| Line 7307... |
Line 7607... |
nlOiOlO <= 0;
|
nlOiOlO <= 0;
|
nlOiOOi <= 0;
|
nlOiOOi <= 0;
|
nlOiOOl <= 0;
|
nlOiOOl <= 0;
|
nlOiOOO <= 0;
|
nlOiOOO <= 0;
|
nlOl10i <= 0;
|
nlOl10i <= 0;
|
nlOl10l <= 0;
|
|
nlOl10O <= 0;
|
|
nlOl11i <= 0;
|
nlOl11i <= 0;
|
nlOl11l <= 0;
|
nlOl11l <= 0;
|
nlOl11O <= 0;
|
nlOl11O <= 0;
|
nlOl1ii <= 0;
|
nlOlOlO <= 0;
|
nlOl1il <= 0;
|
|
nlOO00i <= 0;
|
nlOO00i <= 0;
|
nlOO00l <= 0;
|
|
nlOO00O <= 0;
|
|
nlOO01i <= 0;
|
nlOO01i <= 0;
|
nlOO01l <= 0;
|
nlOO01l <= 0;
|
nlOO01O <= 0;
|
nlOO01O <= 0;
|
nlOO0ii <= 0;
|
nlOO10i <= 0;
|
nlOO0il <= 0;
|
nlOO10l <= 0;
|
nlOO10O <= 0;
|
nlOO10O <= 0;
|
nlOO11i <= 0;
|
nlOO11l <= 0;
|
|
nlOO1ii <= 0;
|
nlOO1il <= 0;
|
nlOO1il <= 0;
|
nlOO1iO <= 0;
|
nlOO1iO <= 0;
|
nlOO1li <= 0;
|
nlOO1li <= 0;
|
nlOO1ll <= 0;
|
nlOO1ll <= 0;
|
nlOO1lO <= 0;
|
nlOO1lO <= 0;
|
nlOO1Oi <= 0;
|
nlOO1Oi <= 0;
|
nlOO1Ol <= 0;
|
nlOO1Ol <= 0;
|
nlOO1OO <= 0;
|
nlOO1OO <= 0;
|
nlOOO0i <= 0;
|
nlOOlOO <= 0;
|
end
|
end
|
else
|
else
|
|
if (wire_nl0ii_clkout != nlliiO_clk_prev && wire_nl0ii_clkout == 1'b1)
|
begin
|
begin
|
n0O11l <= (~ ((~ (n0Oi0i ^ wire_n01lii_dout[0])) & (~ (n0Oiil ^ wire_n01lii_dout[1]))));
|
n0O11l <= (~ ((~ (n0Oi0i ^ wire_n01ilO_dout[0])) & (~ (n0Oiil ^ wire_n01ilO_dout[1]))));
|
n0Oi0i <= wire_n01lii_dout[0];
|
n0Oi0i <= wire_n01ilO_dout[0];
|
n1010i <= wire_n100il_dataout;
|
n1010i <= wire_n100il_dataout;
|
n1010l <= wire_n100iO_dataout;
|
n1010l <= wire_n100iO_dataout;
|
n1010O <= wire_n100li_dataout;
|
n1010O <= wire_n100li_dataout;
|
n1011i <= wire_n1000l_dataout;
|
n1011i <= wire_n1000l_dataout;
|
n1011l <= wire_n1000O_dataout;
|
n1011l <= wire_n1000O_dataout;
|
n1011O <= wire_n100ii_dataout;
|
n1011O <= wire_n100ii_dataout;
|
n101ii <= wire_n100ll_dataout;
|
n101ii <= wire_n100ll_dataout;
|
n101il <= wire_n100lO_dataout;
|
n101il <= wire_n100lO_dataout;
|
n101iO <= wire_n100Oi_dataout;
|
n101iO <= wire_n100Oi_dataout;
|
n101li <= wire_n100Ol_dataout;
|
n101li <= wire_n100Ol_dataout;
|
n101ll <= wire_n100OO_dataout;
|
n10l0i <= wire_n10O1i_dataout;
|
n101lO <= wire_n10i1i_dataout;
|
n10l0l <= wire_n10O1l_dataout;
|
n101Oi <= wire_n10i1l_dataout;
|
n10l0O <= wire_n10O1O_dataout;
|
n101Ol <= wire_n10i1O_dataout;
|
n10lii <= wire_n10O0i_dataout;
|
n10lil <= wire_n10O0l_dataout;
|
n10lil <= wire_n10O0l_dataout;
|
n10liO <= wire_n10O0O_dataout;
|
n10liO <= wire_n10O0O_dataout;
|
n10lli <= wire_n10Oii_dataout;
|
n10lli <= wire_n10Oii_dataout;
|
n10lll <= wire_n10Oil_dataout;
|
n10lll <= wire_n10Oil_dataout;
|
n10llO <= wire_n10OiO_dataout;
|
n10llO <= wire_n10OiO_dataout;
|
n10lOi <= wire_n10Oli_dataout;
|
n10lOi <= wire_n10Oli_dataout;
|
n10lOl <= wire_n10Oll_dataout;
|
n10lOl <= wire_n10Oll_dataout;
|
n10lOO <= wire_n10OlO_dataout;
|
n10lOO <= niO1i;
|
n10O0i <= nil1i;
|
n10OlO <= wire_n10OOl_dataout;
|
n10O1i <= wire_n10OOi_dataout;
|
n10OOi <= n1i11l;
|
n10O1l <= wire_n10OOl_dataout;
|
n11OiO <= wire_n101Oi_dataout;
|
n10O1O <= wire_n10OOO_dataout;
|
n11Oli <= wire_n101Ol_dataout;
|
|
n11Oll <= wire_n101OO_dataout;
|
|
n11OlO <= wire_n1001i_dataout;
|
n11OOi <= wire_n1001l_dataout;
|
n11OOi <= wire_n1001l_dataout;
|
n11OOl <= wire_n1001O_dataout;
|
n11OOl <= wire_n1001O_dataout;
|
n11OOO <= wire_n1000i_dataout;
|
n11OOO <= wire_n1000i_dataout;
|
n1i10O <= nlilOl;
|
n1i11l <= nlilOl;
|
n1i11i <= wire_n1i11O_dataout;
|
nl011i <= nlO1Ol;
|
n1i11l <= n1i10O;
|
|
nl011i <= nlO1ii;
|
|
nl1l0O <= nl1OlO;
|
nl1l0O <= nl1OlO;
|
nl1Oil <= nl1OOi;
|
nl1Oil <= nl1OOi;
|
nl1OiO <= nl1OOl;
|
nl1OiO <= nl1OOl;
|
nl1Oli <= nl1OOO;
|
nl1Oli <= nl1OOO;
|
nl1Oll <= nl011i;
|
nl1Oll <= nl011i;
|
nl1OlO <= nlO11O;
|
nl1OlO <= nlO1li;
|
nl1OOi <= nlO10i;
|
nl1OOi <= nlO1ll;
|
nl1OOl <= nlO10l;
|
nl1OOl <= nlO1lO;
|
nl1OOO <= nlO10O;
|
nl1OOO <= nlO1Oi;
|
nli1lO <= nli1Oi;
|
nli1lO <= nli1Oi;
|
nli1Oi <= nli10O;
|
nli1Oi <= nli10O;
|
nli1Ol <= wire_nli01i_dataout;
|
nli1Ol <= wire_nli01i_dataout;
|
nliOO0l <= wire_nliOOOi_dataout;
|
nliOlOi <= wire_nliOO0O_dataout;
|
nliOOlO <= wire_nll10il_dataout;
|
nliOO0l <= wire_nll101i_dataout;
|
nll000i <= wire_nll00li_dataout;
|
nliOOiO <= wire_nll01ii_dataout;
|
nll00ii <= wire_nll00ll_dataout;
|
nliOOli <= wire_nll101l_dataout;
|
nll00il <= wire_nll00lO_dataout;
|
nliOOll <= wire_nll101O_dataout;
|
nll00iO <= wire_nll0ill_dataout;
|
nliOOlO <= wire_nll100i_dataout;
|
nll01lO <= wire_nliOO0O_dataout;
|
nliOOOi <= wire_nll100l_dataout;
|
nll01Oi <= wire_nll001i_dataout;
|
nliOOOl <= wire_nll100O_dataout;
|
nll01OO <= wire_nll000l_dataout;
|
nliOOOO <= wire_nll10ii_dataout;
|
nll0iiO <= wire_nll0ilO_dataout;
|
nll001i <= wire_nll000l_dataout;
|
nll0ili <= wire_nll0O1i_dataout;
|
nll001l <= wire_nll0i1O_dataout;
|
|
nll010l <= wire_nliOlOl_dataout;
|
|
nll010O <= wire_nll01iO_dataout;
|
|
nll01il <= wire_nll01Oi_dataout;
|
|
nll01lO <= wire_nll001O_dataout;
|
|
nll01OO <= wire_nll000i_dataout;
|
|
nll0i0l <= wire_nll0iil_dataout;
|
|
nll0i0O <= wire_nll0llO_dataout;
|
|
nll0i1l <= wire_nll0iii_dataout;
|
|
nll0ill <= wire_nll0lOi_dataout;
|
|
nll0ilO <= wire_nll0lOl_dataout;
|
|
nll0iOi <= wire_nll0lOO_dataout;
|
|
nll0iOl <= wire_nll0O1i_dataout;
|
nll0iOO <= wire_nll0O1l_dataout;
|
nll0iOO <= wire_nll0O1l_dataout;
|
nll0l0i <= wire_nll0O0O_dataout;
|
nll0l0i <= wire_nll0O0O_dataout;
|
nll0l0l <= wire_nll0Oii_dataout;
|
nll0l0l <= wire_nll0Oii_dataout;
|
nll0l0O <= wire_nll0Oil_dataout;
|
nll0l0O <= wire_nll0Oil_dataout;
|
nll0l1i <= wire_nll0O1O_dataout;
|
nll0l1i <= wire_nll0O1O_dataout;
|
nll0l1l <= wire_nll0O0i_dataout;
|
nll0l1l <= wire_nll0O0i_dataout;
|
nll0l1O <= wire_nll0O0l_dataout;
|
nll0l1O <= wire_nll0O0l_dataout;
|
nll0lii <= wire_nll0OiO_dataout;
|
nll0lii <= wire_nll0OiO_dataout;
|
nll0lil <= wire_nll0Oli_dataout;
|
nll0lil <= wire_nll0Oli_dataout;
|
nll0liO <= wire_nll0Oll_dataout;
|
nll0liO <= wire_nll0Oll_dataout;
|
nll0ll <= (nlli1i & (~ nll0OO));
|
|
nll0lli <= wire_nll0OlO_dataout;
|
nll0lli <= wire_nll0OlO_dataout;
|
nll0lll <= wire_nll0OOi_dataout;
|
nll0lll <= wire_nllil1l_dataout;
|
nll0llO <= wire_nll0OOl_dataout;
|
|
nll0lOi <= wire_nll0OOO_dataout;
|
|
nll0lOl <= wire_nlli11i_dataout;
|
|
nll0lOO <= wire_nllil0O_dataout;
|
|
nll0Oi <= nll0OO;
|
|
nll0OO <= nlli1i;
|
|
nll100i <= wire_nll1ill_dataout;
|
|
nll100l <= wire_nll1ilO_dataout;
|
|
nll100O <= wire_nll1iOi_dataout;
|
|
nll101i <= wire_nll1iil_dataout;
|
|
nll101l <= wire_nll1iiO_dataout;
|
|
nll101O <= wire_nll1ili_dataout;
|
|
nll10ii <= wire_nliOOll_dataout;
|
|
nll110i <= wire_nll10ll_dataout;
|
nll110i <= wire_nll10ll_dataout;
|
nll110l <= wire_nll10lO_dataout;
|
nll110l <= wire_nll10lO_dataout;
|
nll110O <= wire_nll10Oi_dataout;
|
nll110O <= wire_nll10Oi_dataout;
|
nll111i <= wire_nll01Ol_dataout;
|
nll111i <= wire_nll10il_dataout;
|
nll111l <= wire_nll10iO_dataout;
|
nll111l <= wire_nll10iO_dataout;
|
nll111O <= wire_nll10li_dataout;
|
nll111O <= wire_nll10li_dataout;
|
nll11ii <= wire_nll10Ol_dataout;
|
nll11ii <= wire_nll10Ol_dataout;
|
nll11il <= wire_nll10OO_dataout;
|
nll11il <= wire_nll10OO_dataout;
|
nll11iO <= wire_nll1i1i_dataout;
|
nll11iO <= wire_nll1i1i_dataout;
|
nll11li <= wire_nll1i1l_dataout;
|
nll11li <= wire_nll1i1l_dataout;
|
nll11ll <= wire_nll1i1O_dataout;
|
nll11ll <= wire_nll1i1O_dataout;
|
nll11lO <= wire_nll1i0i_dataout;
|
nll11lO <= wire_nll1i0i_dataout;
|
nll11Oi <= wire_nll1i0l_dataout;
|
nll11Oi <= wire_nll1i0l_dataout;
|
nll11Ol <= wire_nll1i0O_dataout;
|
nll11Ol <= wire_nll1i0O_dataout;
|
nll11OO <= wire_nll1iii_dataout;
|
nll11OO <= wire_nliOO0i_dataout;
|
nlli1i <= (nlliii & nlli1O);
|
nlli0l <= nlliii;
|
nlli1O <= nlliii;
|
nlli1O <= (nlliil & (~ nlliii));
|
nllil0l <= wire_nlliOOO_dataout;
|
nlliii <= nlliil;
|
|
nlliil <= (nlliOl & nllili);
|
|
nllil0l <= wire_nlliOlO_dataout;
|
|
nllil0O <= wire_nlliOOi_dataout;
|
|
nllil1i <= wire_nlliOll_dataout;
|
|
nllili <= nlliOl;
|
|
nllilii <= wire_nlliOOl_dataout;
|
|
nllilil <= wire_nlliOOO_dataout;
|
nlliliO <= wire_nlll11i_dataout;
|
nlliliO <= wire_nlll11i_dataout;
|
nllilli <= wire_nlll11l_dataout;
|
nllilli <= wire_nlll11l_dataout;
|
nllilll <= wire_nlll11O_dataout;
|
nllilll <= wire_nlll11O_dataout;
|
nllillO <= wire_nlll10i_dataout;
|
nllillO <= wire_nlll10i_dataout;
|
nllilOi <= wire_nlll10l_dataout;
|
nllilOi <= wire_nlll10l_dataout;
|
| Line 7454... |
Line 7756... |
nlliO1l <= wire_nlll1iO_dataout;
|
nlliO1l <= wire_nlll1iO_dataout;
|
nlliO1O <= wire_nlll1li_dataout;
|
nlliO1O <= wire_nlll1li_dataout;
|
nlliOii <= wire_nlll1Ol_dataout;
|
nlliOii <= wire_nlll1Ol_dataout;
|
nlliOil <= wire_nlll1OO_dataout;
|
nlliOil <= wire_nlll1OO_dataout;
|
nlliOiO <= wire_nlll01i_dataout;
|
nlliOiO <= wire_nlll01i_dataout;
|
nlliOli <= wire_nlll01l_dataout;
|
nlliOli <= wire_nllO1OO_dataout;
|
nlliOll <= wire_nlll01O_dataout;
|
nllO1lO <= wire_nllO01i_dataout;
|
nlliOlO <= wire_nlll00i_dataout;
|
nllO1Oi <= wire_nllO01l_dataout;
|
nlliOOi <= wire_nlll00l_dataout;
|
nllO1Ol <= wire_nllOi0O_dataout;
|
nlliOOl <= wire_nllO00i_dataout;
|
nllOi0i <= wire_nllOiiO_dataout;
|
nllO01i <= wire_nllO00l_dataout;
|
nllOi0l <= wire_nlO101O_dataout;
|
nllO01l <= wire_nllO00O_dataout;
|
nllOi1l <= wire_nllOiii_dataout;
|
nllO01O <= wire_nllOili_dataout;
|
nllOi1O <= wire_nllOiil_dataout;
|
nllOi0O <= wire_nllOill_dataout;
|
nllOO0i <= wire_nlO10ii_dataout;
|
nllOiii <= wire_nllOilO_dataout;
|
|
nllOiil <= wire_nllOiOi_dataout;
|
|
nllOiiO <= wire_nlO10ii_dataout;
|
|
nllOO0l <= wire_nlO10il_dataout;
|
nllOO0l <= wire_nlO10il_dataout;
|
nllOO0O <= wire_nlO10iO_dataout;
|
nllOO0O <= wire_nlO10iO_dataout;
|
|
nllOO1i <= wire_nlO100i_dataout;
|
|
nllOO1l <= wire_nlO100l_dataout;
|
|
nllOO1O <= wire_nlO100O_dataout;
|
nllOOii <= wire_nlO10li_dataout;
|
nllOOii <= wire_nlO10li_dataout;
|
nllOOil <= wire_nlO10ll_dataout;
|
nllOOil <= wire_nlO10ll_dataout;
|
nllOOiO <= wire_nlO10lO_dataout;
|
nllOOiO <= wire_nlO10lO_dataout;
|
nllOOli <= wire_nlO10Oi_dataout;
|
nllOOli <= wire_nlO10Oi_dataout;
|
nllOOll <= wire_nlO10Ol_dataout;
|
nllOOll <= wire_nlO10Ol_dataout;
|
nllOOlO <= wire_nlO10OO_dataout;
|
nllOOlO <= wire_nlO10OO_dataout;
|
nllOOOi <= wire_nlO1i1i_dataout;
|
nllOOOi <= wire_nlO1i1i_dataout;
|
nllOOOl <= wire_nlO1i1l_dataout;
|
nllOOOl <= wire_nlO1i1l_dataout;
|
nllOOOO <= wire_nlO1i1O_dataout;
|
nllOOOO <= wire_nlO1i1O_dataout;
|
nlO100i <= wire_nlO1lii_dataout;
|
|
nlO100l <= wire_nlO1lil_dataout;
|
|
nlO100O <= wire_nlOi0il_dataout;
|
|
nlO101i <= wire_nlO1l0i_dataout;
|
nlO101i <= wire_nlO1l0i_dataout;
|
nlO101l <= wire_nlO1l0l_dataout;
|
nlO101l <= wire_nlOi00i_dataout;
|
nlO101O <= wire_nlO1l0O_dataout;
|
|
nlO110i <= wire_nlO1iii_dataout;
|
nlO110i <= wire_nlO1iii_dataout;
|
nlO110l <= wire_nlO1iil_dataout;
|
nlO110l <= wire_nlO1iil_dataout;
|
nlO110O <= wire_nlO1iiO_dataout;
|
nlO110O <= wire_nlO1iiO_dataout;
|
nlO111i <= wire_nlO1i0i_dataout;
|
nlO111i <= wire_nlO1i0i_dataout;
|
nlO111l <= wire_nlO1i0l_dataout;
|
nlO111l <= wire_nlO1i0l_dataout;
|
| Line 7498... |
Line 7796... |
nlO11ll <= wire_nlO1iOl_dataout;
|
nlO11ll <= wire_nlO1iOl_dataout;
|
nlO11lO <= wire_nlO1iOO_dataout;
|
nlO11lO <= wire_nlO1iOO_dataout;
|
nlO11Oi <= wire_nlO1l1i_dataout;
|
nlO11Oi <= wire_nlO1l1i_dataout;
|
nlO11Ol <= wire_nlO1l1l_dataout;
|
nlO11Ol <= wire_nlO1l1l_dataout;
|
nlO11OO <= wire_nlO1l1O_dataout;
|
nlO11OO <= wire_nlO1l1O_dataout;
|
nlOi00i <= wire_nlOi0Oi_dataout;
|
|
nlOi00l <= wire_nlOi0Ol_dataout;
|
|
nlOi01i <= wire_nlOi0li_dataout;
|
nlOi01i <= wire_nlOi0li_dataout;
|
nlOi01l <= wire_nlOi0ll_dataout;
|
nlOi01O <= wire_nlili0O_dout;
|
nlOi01O <= wire_nlOi0lO_dataout;
|
nlOi1ll <= wire_nlOi00l_dataout;
|
nlOi0ii <= wire_nliliOl_dout;
|
nlOi1lO <= wire_nlOi00O_dataout;
|
|
nlOi1Oi <= wire_nlOi0ii_dataout;
|
|
nlOi1Ol <= wire_nlOi0il_dataout;
|
nlOi1OO <= wire_nlOi0iO_dataout;
|
nlOi1OO <= wire_nlOi0iO_dataout;
|
nlOil1i <= wire_nlOil1O_dataout;
|
nlOiilO <= wire_nlOiiOl_dataout;
|
nlOil1l <= wire_nlOl1iO_dataout;
|
nlOiiOi <= wire_nlOl10l_dataout;
|
|
nlOil0l <= wire_nlOl10O_dataout;
|
|
nlOil0O <= wire_nlOl1ii_dataout;
|
|
nlOilii <= wire_nlOl1il_dataout;
|
|
nlOilil <= wire_nlOl1iO_dataout;
|
nlOiliO <= wire_nlOl1li_dataout;
|
nlOiliO <= wire_nlOl1li_dataout;
|
nlOilli <= wire_nlOl1ll_dataout;
|
nlOilli <= wire_nlOl1ll_dataout;
|
nlOilll <= wire_nlOl1lO_dataout;
|
nlOilll <= wire_nlOl1lO_dataout;
|
nlOillO <= wire_nlOl1Oi_dataout;
|
nlOillO <= wire_nlOl1Oi_dataout;
|
nlOilOi <= wire_nlOl1Ol_dataout;
|
nlOilOi <= wire_nlOl1Ol_dataout;
|
| Line 7529... |
Line 7831... |
nlOiOll <= wire_nlOl0lO_dataout;
|
nlOiOll <= wire_nlOl0lO_dataout;
|
nlOiOlO <= wire_nlOl0Oi_dataout;
|
nlOiOlO <= wire_nlOl0Oi_dataout;
|
nlOiOOi <= wire_nlOl0Ol_dataout;
|
nlOiOOi <= wire_nlOl0Ol_dataout;
|
nlOiOOl <= wire_nlOl0OO_dataout;
|
nlOiOOl <= wire_nlOl0OO_dataout;
|
nlOiOOO <= wire_nlOli1i_dataout;
|
nlOiOOO <= wire_nlOli1i_dataout;
|
nlOl10i <= wire_nlOli0l_dataout;
|
nlOl10i <= wire_nlOlOOi_dataout;
|
nlOl10l <= wire_nlOli0O_dataout;
|
|
nlOl10O <= wire_nlOliii_dataout;
|
|
nlOl11i <= wire_nlOli1l_dataout;
|
nlOl11i <= wire_nlOli1l_dataout;
|
nlOl11l <= wire_nlOli1O_dataout;
|
nlOl11l <= wire_nlOli1O_dataout;
|
nlOl11O <= wire_nlOli0i_dataout;
|
nlOl11O <= wire_nlOli0i_dataout;
|
nlOl1ii <= wire_nlOliil_dataout;
|
nlOlOlO <= wire_nlOO11O_dataout;
|
nlOl1il <= wire_nlOO11l_dataout;
|
nlOO00i <= wire_nlOOO1i_dataout;
|
nlOO00i <= wire_nlOOi0O_dataout;
|
|
nlOO00l <= wire_nlOOiii_dataout;
|
|
nlOO00O <= wire_nlOOiil_dataout;
|
|
nlOO01i <= wire_nlOOi1O_dataout;
|
nlOO01i <= wire_nlOOi1O_dataout;
|
nlOO01l <= wire_nlOOi0i_dataout;
|
nlOO01l <= wire_nlOOi0i_dataout;
|
nlOO01O <= wire_nlOOi0l_dataout;
|
nlOO01O <= wire_nlOOi0l_dataout;
|
nlOO0ii <= wire_nlOOiiO_dataout;
|
nlOO10i <= wire_nlOO00O_dataout;
|
nlOO0il <= wire_nlOOO0l_dataout;
|
nlOO10l <= wire_nlOO0ii_dataout;
|
nlOO10O <= wire_nlOO0iO_dataout;
|
nlOO10O <= wire_nlOO0il_dataout;
|
nlOO11i <= wire_nlOO1ii_dataout;
|
nlOO11l <= wire_nlOO00l_dataout;
|
|
nlOO1ii <= wire_nlOO0iO_dataout;
|
nlOO1il <= wire_nlOO0li_dataout;
|
nlOO1il <= wire_nlOO0li_dataout;
|
nlOO1iO <= wire_nlOO0ll_dataout;
|
nlOO1iO <= wire_nlOO0ll_dataout;
|
nlOO1li <= wire_nlOO0lO_dataout;
|
nlOO1li <= wire_nlOO0lO_dataout;
|
nlOO1ll <= wire_nlOO0Oi_dataout;
|
nlOO1ll <= wire_nlOO0Oi_dataout;
|
nlOO1lO <= wire_nlOO0Ol_dataout;
|
nlOO1lO <= wire_nlOO0Ol_dataout;
|
nlOO1Oi <= wire_nlOO0OO_dataout;
|
nlOO1Oi <= wire_nlOO0OO_dataout;
|
nlOO1Ol <= wire_nlOOi1i_dataout;
|
nlOO1Ol <= wire_nlOOi1i_dataout;
|
nlOO1OO <= wire_nlOOi1l_dataout;
|
nlOO1OO <= wire_nlOOi1l_dataout;
|
nlOOO0i <= wire_n1001i_dataout;
|
nlOOlOO <= wire_n101lO_dataout;
|
end
|
end
|
|
nlliiO_clk_prev <= wire_nl0ii_clkout;
|
end
|
end
|
assign
|
assign
|
wire_nlli1l_CLRN = ((nli01Ol64 ^ nli01Ol63) & (~ nlilill));
|
wire_nlliiO_CLRN = ((nli010i60 ^ nli010i59) & (~ nlili1O)),
|
initial
|
wire_nlliiO_PRN = (nli011O62 ^ nli011O61);
|
begin
|
|
nl010i = 0;
|
|
nlll0l = 0;
|
|
nlOO0l = 0;
|
|
end
|
|
always @ (clk or wire_nlOO0i_PRN or wire_nlOO0i_CLRN)
|
|
begin
|
|
if (wire_nlOO0i_PRN == 1'b0)
|
|
begin
|
|
nl010i <= 1;
|
|
nlll0l <= 1;
|
|
nlOO0l <= 1;
|
|
end
|
|
else if (wire_nlOO0i_CLRN == 1'b0)
|
|
begin
|
|
nl010i <= 0;
|
|
nlll0l <= 0;
|
|
nlOO0l <= 0;
|
|
end
|
|
else
|
|
if (clk != nlOO0i_clk_prev && clk == 1'b1)
|
|
begin
|
|
nl010i <= wire_nl01il_dataout;
|
|
nlll0l <= (~ nlOO1O);
|
|
nlOO0l <= wire_nlOi0l_o;
|
|
end
|
|
nlOO0i_clk_prev <= clk;
|
|
end
|
|
assign
|
|
wire_nlOO0i_CLRN = (nli00Ol60 ^ nli00Ol59),
|
|
wire_nlOO0i_PRN = ((nli00Oi62 ^ nli00Oi61) & (~ reset));
|
|
event nl010i_event;
|
|
event nlll0l_event;
|
|
event nlOO0l_event;
|
|
initial
|
|
#1 ->nl010i_event;
|
|
initial
|
|
#1 ->nlll0l_event;
|
|
initial
|
|
#1 ->nlOO0l_event;
|
|
always @(nl010i_event)
|
|
nl010i <= 1;
|
|
always @(nlll0l_event)
|
|
nlll0l <= 1;
|
|
always @(nlOO0l_event)
|
|
nlOO0l <= 1;
|
|
initial
|
initial
|
begin
|
begin
|
niOO0i = 0;
|
niOO0i = 0;
|
niOO0l = 0;
|
niOO0l = 0;
|
niOO0O = 0;
|
niOO0O = 0;
|
| Line 7641... |
Line 7894... |
nlilOl = 0;
|
nlilOl = 0;
|
nliO0l = 0;
|
nliO0l = 0;
|
nliO0O = 0;
|
nliO0O = 0;
|
nliOii = 0;
|
nliOii = 0;
|
nliOil = 0;
|
nliOil = 0;
|
nll0ii = 0;
|
nll00i = 0;
|
nll0iO = 0;
|
nll00l = 0;
|
nll0li = 0;
|
nll01i = 0;
|
|
nll01l = 0;
|
|
nll01O = 0;
|
|
nll0Ol = 0;
|
nll11i = 0;
|
nll11i = 0;
|
nll11l = 0;
|
|
nll1il = 0;
|
nll1il = 0;
|
nll1iO = 0;
|
nll1iO = 0;
|
nll1li = 0;
|
nll1OO = 0;
|
nll1ll = 0;
|
nlli1i = 0;
|
nll1lO = 0;
|
nlli1l = 0;
|
nll1Oi = 0;
|
nllill = 0;
|
nlli0i = 0;
|
|
nlli0O = 0;
|
|
nlliii = 0;
|
|
nlliil = 0;
|
|
nllilO = 0;
|
|
nlliOi = 0;
|
nlliOi = 0;
|
nlliOl = 0;
|
nlliOl = 0;
|
nlliOO = 0;
|
nlliOO = 0;
|
nlll0i = 0;
|
nlll0i = 0;
|
nlll1i = 0;
|
nlll0l = 0;
|
nlll1l = 0;
|
nlll0O = 0;
|
nlll1O = 0;
|
nlllii = 0;
|
nllO0i = 0;
|
nlllil = 0;
|
nllO0l = 0;
|
nllliO = 0;
|
nllO0O = 0;
|
nlllli = 0;
|
nllO1i = 0;
|
nlllll = 0;
|
nllO1l = 0;
|
|
nllO1O = 0;
|
|
nllOii = 0;
|
|
nllOil = 0;
|
nllOil = 0;
|
nllOiO = 0;
|
nllOiO = 0;
|
nllOli = 0;
|
nllOli = 0;
|
nllOll = 0;
|
nllOll = 0;
|
nllOlO = 0;
|
nllOlO = 0;
|
| Line 7689... |
Line 7936... |
nlO01O = 0;
|
nlO01O = 0;
|
nlO0ii = 0;
|
nlO0ii = 0;
|
nlO0il = 0;
|
nlO0il = 0;
|
nlO0iO = 0;
|
nlO0iO = 0;
|
nlO0li = 0;
|
nlO0li = 0;
|
|
nlO0ll = 0;
|
|
nlO0lO = 0;
|
|
nlO0Oi = 0;
|
|
nlO0Ol = 0;
|
|
nlO0OO = 0;
|
nlO10i = 0;
|
nlO10i = 0;
|
nlO10l = 0;
|
nlO10l = 0;
|
nlO10O = 0;
|
nlO10O = 0;
|
nlO11i = 0;
|
nlO11i = 0;
|
nlO11l = 0;
|
nlO11l = 0;
|
| Line 7704... |
Line 7956... |
nlO1ll = 0;
|
nlO1ll = 0;
|
nlO1lO = 0;
|
nlO1lO = 0;
|
nlO1Oi = 0;
|
nlO1Oi = 0;
|
nlO1Ol = 0;
|
nlO1Ol = 0;
|
nlO1OO = 0;
|
nlO1OO = 0;
|
nlOlOO = 0;
|
nlOi1i = 0;
|
nlOO1i = 0;
|
nlOi1l = 0;
|
nlOO1l = 0;
|
|
nlOO1O = 0;
|
|
nlOOii = 0;
|
nlOOii = 0;
|
|
nlOOil = 0;
|
|
nlOOiO = 0;
|
|
nlOOli = 0;
|
|
nlOOOi = 0;
|
end
|
end
|
always @ (clk or wire_nlOO0O_PRN or reset)
|
always @ ( posedge clk or negedge wire_nlOOlO_CLRN)
|
begin
|
begin
|
if (wire_nlOO0O_PRN == 1'b0)
|
if (wire_nlOOlO_CLRN == 1'b0)
|
begin
|
|
niOO0i <= 1;
|
|
niOO0l <= 1;
|
|
niOO0O <= 1;
|
|
niOO1i <= 1;
|
|
niOO1l <= 1;
|
|
niOO1O <= 1;
|
|
niOOii <= 1;
|
|
niOOil <= 1;
|
|
niOOiO <= 1;
|
|
niOOli <= 1;
|
|
niOOll <= 1;
|
|
niOOlO <= 1;
|
|
niOOOi <= 1;
|
|
niOOOl <= 1;
|
|
niOOOO <= 1;
|
|
nl010l <= 1;
|
|
nl011l <= 1;
|
|
nl011O <= 1;
|
|
nl1i0i <= 1;
|
|
nli10l <= 1;
|
|
nli10O <= 1;
|
|
nli11O <= 1;
|
|
nli1ll <= 1;
|
|
nlil0i <= 1;
|
|
nlil0O <= 1;
|
|
nlil1O <= 1;
|
|
nlilii <= 1;
|
|
nlilOl <= 1;
|
|
nliO0l <= 1;
|
|
nliO0O <= 1;
|
|
nliOii <= 1;
|
|
nliOil <= 1;
|
|
nll0ii <= 1;
|
|
nll0iO <= 1;
|
|
nll0li <= 1;
|
|
nll11i <= 1;
|
|
nll11l <= 1;
|
|
nll1il <= 1;
|
|
nll1iO <= 1;
|
|
nll1li <= 1;
|
|
nll1ll <= 1;
|
|
nll1lO <= 1;
|
|
nll1Oi <= 1;
|
|
nlli0i <= 1;
|
|
nlli0O <= 1;
|
|
nlliii <= 1;
|
|
nlliil <= 1;
|
|
nllilO <= 1;
|
|
nlliOi <= 1;
|
|
nlliOl <= 1;
|
|
nlliOO <= 1;
|
|
nlll0i <= 1;
|
|
nlll1i <= 1;
|
|
nlll1l <= 1;
|
|
nlll1O <= 1;
|
|
nllO0i <= 1;
|
|
nllO0l <= 1;
|
|
nllO0O <= 1;
|
|
nllO1i <= 1;
|
|
nllO1l <= 1;
|
|
nllO1O <= 1;
|
|
nllOii <= 1;
|
|
nllOil <= 1;
|
|
nllOiO <= 1;
|
|
nllOli <= 1;
|
|
nllOll <= 1;
|
|
nllOlO <= 1;
|
|
nllOOi <= 1;
|
|
nllOOl <= 1;
|
|
nllOOO <= 1;
|
|
nlO00i <= 1;
|
|
nlO00l <= 1;
|
|
nlO00O <= 1;
|
|
nlO01i <= 1;
|
|
nlO01l <= 1;
|
|
nlO01O <= 1;
|
|
nlO0ii <= 1;
|
|
nlO0il <= 1;
|
|
nlO0iO <= 1;
|
|
nlO0li <= 1;
|
|
nlO10i <= 1;
|
|
nlO10l <= 1;
|
|
nlO10O <= 1;
|
|
nlO11i <= 1;
|
|
nlO11l <= 1;
|
|
nlO11O <= 1;
|
|
nlO1ii <= 1;
|
|
nlO1il <= 1;
|
|
nlO1iO <= 1;
|
|
nlO1li <= 1;
|
|
nlO1ll <= 1;
|
|
nlO1lO <= 1;
|
|
nlO1Oi <= 1;
|
|
nlO1Ol <= 1;
|
|
nlO1OO <= 1;
|
|
nlOlOO <= 1;
|
|
nlOO1i <= 1;
|
|
nlOO1l <= 1;
|
|
nlOO1O <= 1;
|
|
nlOOii <= 1;
|
|
end
|
|
else if (reset == 1'b1)
|
|
begin
|
begin
|
niOO0i <= 0;
|
niOO0i <= 0;
|
niOO0l <= 0;
|
niOO0l <= 0;
|
niOO0O <= 0;
|
niOO0O <= 0;
|
niOO1i <= 0;
|
niOO1i <= 0;
|
| Line 7849... |
Line 8000... |
nlilOl <= 0;
|
nlilOl <= 0;
|
nliO0l <= 0;
|
nliO0l <= 0;
|
nliO0O <= 0;
|
nliO0O <= 0;
|
nliOii <= 0;
|
nliOii <= 0;
|
nliOil <= 0;
|
nliOil <= 0;
|
nll0ii <= 0;
|
nll00i <= 0;
|
nll0iO <= 0;
|
nll00l <= 0;
|
nll0li <= 0;
|
nll01i <= 0;
|
|
nll01l <= 0;
|
|
nll01O <= 0;
|
|
nll0Ol <= 0;
|
nll11i <= 0;
|
nll11i <= 0;
|
nll11l <= 0;
|
|
nll1il <= 0;
|
nll1il <= 0;
|
nll1iO <= 0;
|
nll1iO <= 0;
|
nll1li <= 0;
|
nll1OO <= 0;
|
nll1ll <= 0;
|
nlli1i <= 0;
|
nll1lO <= 0;
|
nlli1l <= 0;
|
nll1Oi <= 0;
|
nllill <= 0;
|
nlli0i <= 0;
|
|
nlli0O <= 0;
|
|
nlliii <= 0;
|
|
nlliil <= 0;
|
|
nllilO <= 0;
|
|
nlliOi <= 0;
|
nlliOi <= 0;
|
nlliOl <= 0;
|
nlliOl <= 0;
|
nlliOO <= 0;
|
nlliOO <= 0;
|
nlll0i <= 0;
|
nlll0i <= 0;
|
nlll1i <= 0;
|
nlll0l <= 0;
|
nlll1l <= 0;
|
nlll0O <= 0;
|
nlll1O <= 0;
|
nlllii <= 0;
|
nllO0i <= 0;
|
nlllil <= 0;
|
nllO0l <= 0;
|
nllliO <= 0;
|
nllO0O <= 0;
|
nlllli <= 0;
|
nllO1i <= 0;
|
nlllll <= 0;
|
nllO1l <= 0;
|
|
nllO1O <= 0;
|
|
nllOii <= 0;
|
|
nllOil <= 0;
|
nllOil <= 0;
|
nllOiO <= 0;
|
nllOiO <= 0;
|
nllOli <= 0;
|
nllOli <= 0;
|
nllOll <= 0;
|
nllOll <= 0;
|
nllOlO <= 0;
|
nllOlO <= 0;
|
| Line 7897... |
Line 8042... |
nlO01O <= 0;
|
nlO01O <= 0;
|
nlO0ii <= 0;
|
nlO0ii <= 0;
|
nlO0il <= 0;
|
nlO0il <= 0;
|
nlO0iO <= 0;
|
nlO0iO <= 0;
|
nlO0li <= 0;
|
nlO0li <= 0;
|
|
nlO0ll <= 0;
|
|
nlO0lO <= 0;
|
|
nlO0Oi <= 0;
|
|
nlO0Ol <= 0;
|
|
nlO0OO <= 0;
|
nlO10i <= 0;
|
nlO10i <= 0;
|
nlO10l <= 0;
|
nlO10l <= 0;
|
nlO10O <= 0;
|
nlO10O <= 0;
|
nlO11i <= 0;
|
nlO11i <= 0;
|
nlO11l <= 0;
|
nlO11l <= 0;
|
| Line 7912... |
Line 8062... |
nlO1ll <= 0;
|
nlO1ll <= 0;
|
nlO1lO <= 0;
|
nlO1lO <= 0;
|
nlO1Oi <= 0;
|
nlO1Oi <= 0;
|
nlO1Ol <= 0;
|
nlO1Ol <= 0;
|
nlO1OO <= 0;
|
nlO1OO <= 0;
|
nlOlOO <= 0;
|
nlOi1i <= 0;
|
nlOO1i <= 0;
|
nlOi1l <= 0;
|
nlOO1l <= 0;
|
|
nlOO1O <= 0;
|
|
nlOOii <= 0;
|
nlOOii <= 0;
|
|
nlOOil <= 0;
|
|
nlOOiO <= 0;
|
|
nlOOli <= 0;
|
|
nlOOOi <= 0;
|
end
|
end
|
else
|
else
|
if (clk != nlOO0O_clk_prev && clk == 1'b1)
|
|
begin
|
begin
|
niOO0i <= wire_nl110O_dataout;
|
niOO0i <= wire_nl110O_dataout;
|
niOO0l <= wire_nl11ii_dataout;
|
niOO0l <= wire_nl11ii_dataout;
|
niOO0O <= wire_nl11il_dataout;
|
niOO0O <= wire_nl11il_dataout;
|
niOO1i <= wire_nl111O_dataout;
|
niOO1i <= wire_nl111O_dataout;
|
| Line 7945... |
Line 8096... |
nli10l <= wire_nli1ii_dataout;
|
nli10l <= wire_nli1ii_dataout;
|
nli10O <= nli1ll;
|
nli10O <= nli1ll;
|
nli11O <= nli10O;
|
nli11O <= nli10O;
|
nli1ll <= nli1Ol;
|
nli1ll <= nli1Ol;
|
nlil0i <= wire_nlilli_dataout;
|
nlil0i <= wire_nlilli_dataout;
|
nlil0O <= ((~ nll11i) & (nll1lO & nliOOi));
|
nlil0O <= ((~ nll1il) & (nll00i & nll10l));
|
nlil1O <= nll1li;
|
nlil1O <= nll01l;
|
nlilii <= wire_nlilOO_dataout;
|
nlilii <= wire_nlilOO_dataout;
|
nlilOl <= (nll11i | nliOli);
|
nlilOl <= (nll1il | nll11l);
|
nliO0l <= nliOOi;
|
nliO0l <= nll10l;
|
nliO0O <= nliOll;
|
nliO0O <= nll11O;
|
nliOii <= nliOil;
|
nliOii <= nll11i;
|
nliOil <= wire_nll11O_dataout;
|
nliOil <= wire_nliOll_dataout;
|
nll0ii <= nll01l;
|
nll00i <= nll00l;
|
nll0iO <= wire_nll0lO_dataout;
|
nll00l <= nliOOiO;
|
nll0li <= wire_nlO0lO_o;
|
nll01i <= niO1i;
|
nll11i <= wire_nll10l_dataout;
|
nll01l <= nll01O;
|
nll11l <= nlO11l;
|
nll01O <= nll010O;
|
nll1il <= nll1iO;
|
nll0Ol <= nll0iO;
|
nll1iO <= nil1i;
|
nll11i <= wire_nll1li_dataout;
|
nll1li <= nll1ll;
|
nll1il <= wire_nll1lO_dataout;
|
nll1ll <= nll01Oi;
|
nll1iO <= nlO1iO;
|
nll1lO <= nll1Oi;
|
nll1OO <= nll01i;
|
nll1Oi <= nll111i;
|
nlli1i <= wire_nlli0i_dataout;
|
nlli0i <= nll0Oi;
|
nlli1l <= wire_nlOi0i_o;
|
nlli0O <= wire_nlliiO_dataout;
|
nllill <= nlli0l;
|
nlliii <= wire_nlO0Ol_o;
|
nlliOi <= wire_nlll1i_dataout;
|
nlliil <= nli01OO;
|
nlliOl <= wire_nlOi0O_o;
|
nllilO <= wire_nlll0O_dataout;
|
nlliOO <= nli010l;
|
nlliOi <= wire_nlllii_dataout;
|
|
nlliOl <= wire_nlllil_dataout;
|
|
nlliOO <= wire_nllliO_dataout;
|
|
nlll0i <= wire_nlllOi_dataout;
|
nlll0i <= wire_nlllOi_dataout;
|
nlll1i <= wire_nlllli_dataout;
|
nlll0l <= wire_nlllOl_dataout;
|
nlll1l <= wire_nlllll_dataout;
|
nlll0O <= wire_nlllOO_dataout;
|
nlll1O <= wire_nllllO_dataout;
|
nlllii <= wire_nllO1i_dataout;
|
nllO0i <= niOO1O;
|
nlllil <= wire_nllO1l_dataout;
|
nllO0l <= niOO0i;
|
nllliO <= wire_nllO1O_dataout;
|
nllO0O <= niOO0l;
|
nlllli <= wire_nllO0i_dataout;
|
nllO1i <= nl1i0i;
|
nlllll <= wire_nllO0l_dataout;
|
nllO1l <= niOO1i;
|
nllOil <= nl1i0i;
|
nllO1O <= niOO1l;
|
nllOiO <= niOO1i;
|
nllOii <= niOO0O;
|
nllOli <= niOO1l;
|
nllOil <= niOOii;
|
nllOll <= niOO1O;
|
nllOiO <= niOOil;
|
nllOlO <= niOO0i;
|
nllOli <= niOOiO;
|
nllOOi <= niOO0l;
|
nllOll <= niOOli;
|
nllOOl <= niOO0O;
|
nllOlO <= niOOll;
|
nllOOO <= niOOii;
|
nllOOi <= niOOlO;
|
nlO00i <= writedata[3];
|
nllOOl <= niOOOi;
|
nlO00l <= writedata[4];
|
nllOOO <= niOOOl;
|
nlO00O <= writedata[5];
|
nlO00i <= writedata[10];
|
nlO01i <= writedata[0];
|
nlO00l <= writedata[11];
|
nlO01l <= writedata[1];
|
nlO00O <= writedata[12];
|
nlO01O <= writedata[2];
|
nlO01i <= writedata[7];
|
nlO0ii <= writedata[6];
|
nlO01l <= writedata[8];
|
nlO0il <= writedata[7];
|
nlO01O <= writedata[9];
|
nlO0iO <= writedata[8];
|
nlO0ii <= writedata[13];
|
nlO0li <= writedata[9];
|
nlO0il <= writedata[14];
|
nlO0ll <= writedata[10];
|
nlO0iO <= writedata[15];
|
nlO0lO <= writedata[11];
|
nlO0li <= wire_nlO0lO_o;
|
nlO0Oi <= writedata[12];
|
nlO10i <= address[1];
|
nlO0Ol <= writedata[13];
|
nlO10l <= address[2];
|
nlO0OO <= writedata[14];
|
nlO10O <= address[3];
|
nlO10i <= niOOll;
|
nlO11i <= niOOOO;
|
nlO10l <= niOOlO;
|
nlO11l <= wire_nlOi1i_o;
|
nlO10O <= niOOOi;
|
nlO11O <= address[0];
|
nlO11i <= niOOil;
|
nlO1ii <= address[4];
|
nlO11l <= niOOiO;
|
nlO1il <= wire_nlO0ll_dataout;
|
nlO11O <= niOOli;
|
nlO1iO <= writedata[0];
|
nlO1ii <= niOOOl;
|
nlO1li <= writedata[1];
|
nlO1il <= niOOOO;
|
nlO1ll <= writedata[2];
|
nlO1iO <= wire_nlOiil_o;
|
nlO1lO <= writedata[3];
|
nlO1li <= address[0];
|
nlO1Oi <= writedata[4];
|
nlO1ll <= address[1];
|
nlO1Ol <= writedata[5];
|
nlO1lO <= address[2];
|
nlO1OO <= writedata[6];
|
nlO1Oi <= address[3];
|
nlOlOO <= wire_nlO0Ol_o;
|
nlO1Ol <= address[4];
|
nlOO1i <= nlOO1O;
|
nlO1OO <= wire_nlOi1O_dataout;
|
nlOO1l <= wire_nlOi1i_o;
|
nlOi1i <= writedata[15];
|
nlOO1O <= wire_nlOi1O_o;
|
nlOi1l <= wire_nlOi0i_o;
|
nlOOii <= wire_nlOOil_dataout;
|
nlOOii <= wire_nlOi0O_o;
|
|
nlOOil <= nlOOli;
|
|
nlOOiO <= wire_nlOiil_o;
|
|
nlOOli <= wire_nlOili_o;
|
|
nlOOOi <= wire_nlOOOl_dataout;
|
end
|
end
|
nlOO0O_clk_prev <= clk;
|
|
end
|
end
|
assign
|
assign
|
wire_nlOO0O_PRN = (nli00OO58 ^ nli00OO57);
|
wire_nlOOlO_CLRN = ((nli001O58 ^ nli001O57) & (~ reset));
|
and(wire_n0000i_dataout, wire_n000ll_dataout, nli1i1l);
|
and(wire_n0000i_dataout, wire_n000ll_dataout, nli100l);
|
and(wire_n0000l_dataout, wire_n000lO_dataout, nli1i1l);
|
and(wire_n0000l_dataout, wire_n000lO_dataout, nli100l);
|
and(wire_n0000O_dataout, wire_n000Oi_dataout, nli1i1l);
|
and(wire_n0000O_dataout, wire_n000Oi_dataout, nli100l);
|
assign wire_n0001i_dataout = (nli1i1i === 1'b1) ? wire_n00iiO_dataout : wire_n000il_dataout;
|
assign wire_n0001i_dataout = (nli100i === 1'b1) ? wire_n00iiO_dataout : wire_n000il_dataout;
|
assign wire_n0001l_dataout = (nli1i1i === 1'b1) ? wire_n00ili_dataout : wire_n000iO_dataout;
|
assign wire_n0001l_dataout = (nli100i === 1'b1) ? wire_n00ili_dataout : wire_n000iO_dataout;
|
and(wire_n0001O_dataout, wire_n000li_dataout, nli1i1l);
|
and(wire_n0001O_dataout, wire_n000li_dataout, nli100l);
|
and(wire_n000ii_dataout, wire_n000Ol_dataout, nli1i1l);
|
assign wire_n000i_dataout = (n01OO === 1'b1) ? wire_n00ii_o[1] : n00iO;
|
and(wire_n000il_dataout, wire_n000OO_dataout, nli1i1l);
|
and(wire_n000ii_dataout, wire_n000Ol_dataout, nli100l);
|
and(wire_n000iO_dataout, wire_n00i1i_dataout, nli1i1l);
|
and(wire_n000il_dataout, wire_n000OO_dataout, nli100l);
|
|
and(wire_n000iO_dataout, wire_n00i1i_dataout, nli100l);
|
|
assign wire_n000l_dataout = (n01OO === 1'b1) ? wire_n00ii_o[2] : n01Ol;
|
and(wire_n000li_dataout, wire_n00i1l_o[0], ~(wire_n00i1O_o));
|
and(wire_n000li_dataout, wire_n00i1l_o[0], ~(wire_n00i1O_o));
|
and(wire_n000ll_dataout, wire_n00i1l_o[1], ~(wire_n00i1O_o));
|
and(wire_n000ll_dataout, wire_n00i1l_o[1], ~(wire_n00i1O_o));
|
and(wire_n000lO_dataout, wire_n00i1l_o[2], ~(wire_n00i1O_o));
|
and(wire_n000lO_dataout, wire_n00i1l_o[2], ~(wire_n00i1O_o));
|
|
and(wire_n000O_dataout, wire_n00ii_o[3], n01OO);
|
and(wire_n000Oi_dataout, wire_n00i1l_o[3], ~(wire_n00i1O_o));
|
and(wire_n000Oi_dataout, wire_n00i1l_o[3], ~(wire_n00i1O_o));
|
and(wire_n000Ol_dataout, wire_n00i1l_o[4], ~(wire_n00i1O_o));
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and(wire_n000Ol_dataout, wire_n00i1l_o[4], ~(wire_n00i1O_o));
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and(wire_n000OO_dataout, wire_n00i1l_o[5], ~(wire_n00i1O_o));
|
and(wire_n000OO_dataout, wire_n00i1l_o[5], ~(wire_n00i1O_o));
|
assign wire_n0011i_dataout = (nli1i1i === 1'b1) ? nli10Ol : wire_n0011l_dataout;
|
assign wire_n0011l_dataout = (nli100i === 1'b1) ? nli101l : wire_n0011O_dataout;
|
and(wire_n0011l_dataout, nli10OO, nli1i1l);
|
and(wire_n0011O_dataout, nli101O, nli100l);
|
assign wire_n001ll_dataout = (nli1i1i === 1'b1) ? wire_n00i0i_dataout : wire_n0001O_dataout;
|
and(wire_n001i_dataout, wire_n000i_dataout, ~(nli0i1i));
|
assign wire_n001lO_dataout = (nli1i1i === 1'b1) ? wire_n00i0l_dataout : wire_n0000i_dataout;
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or(wire_n001l_dataout, wire_n000l_dataout, nli0i1i);
|
assign wire_n001Oi_dataout = (nli1i1i === 1'b1) ? wire_n00i0O_dataout : wire_n0000l_dataout;
|
assign wire_n001ll_dataout = (nli100i === 1'b1) ? wire_n00i0i_dataout : wire_n0001O_dataout;
|
assign wire_n001Ol_dataout = (nli1i1i === 1'b1) ? wire_n00iii_dataout : wire_n0000O_dataout;
|
assign wire_n001lO_dataout = (nli100i === 1'b1) ? wire_n00i0l_dataout : wire_n0000i_dataout;
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assign wire_n001OO_dataout = (nli1i1i === 1'b1) ? wire_n00iil_dataout : wire_n000ii_dataout;
|
or(wire_n001O_dataout, wire_n000O_dataout, nli0i1i);
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and(wire_n00i0i_dataout, wire_n00i1l_o[0], ~(nli1i1O));
|
assign wire_n001Oi_dataout = (nli100i === 1'b1) ? wire_n00i0O_dataout : wire_n0000l_dataout;
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and(wire_n00i0l_dataout, wire_n00i1l_o[1], ~(nli1i1O));
|
assign wire_n001Ol_dataout = (nli100i === 1'b1) ? wire_n00iii_dataout : wire_n0000O_dataout;
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and(wire_n00i0O_dataout, wire_n00i1l_o[2], ~(nli1i1O));
|
assign wire_n001OO_dataout = (nli100i === 1'b1) ? wire_n00iil_dataout : wire_n000ii_dataout;
|
|
and(wire_n00i0i_dataout, wire_n00i1l_o[0], ~(nli100O));
|
|
and(wire_n00i0l_dataout, wire_n00i1l_o[1], ~(nli100O));
|
|
and(wire_n00i0O_dataout, wire_n00i1l_o[2], ~(nli100O));
|
and(wire_n00i1i_dataout, wire_n00i1l_o[6], ~(wire_n00i1O_o));
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and(wire_n00i1i_dataout, wire_n00i1l_o[6], ~(wire_n00i1O_o));
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and(wire_n00iii_dataout, wire_n00i1l_o[3], ~(nli1i1O));
|
and(wire_n00iii_dataout, wire_n00i1l_o[3], ~(nli100O));
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and(wire_n00iil_dataout, wire_n00i1l_o[4], ~(nli1i1O));
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and(wire_n00iil_dataout, wire_n00i1l_o[4], ~(nli100O));
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and(wire_n00iiO_dataout, wire_n00i1l_o[5], ~(nli1i1O));
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and(wire_n00iiO_dataout, wire_n00i1l_o[5], ~(nli100O));
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and(wire_n00ili_dataout, wire_n00i1l_o[6], ~(nli1i1O));
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and(wire_n00ili_dataout, wire_n00i1l_o[6], ~(nli100O));
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and(wire_n00l0i_dataout, (~ n01Oli), ~(nli1i0i));
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and(wire_n00l0i_dataout, (~ n01OiO), ~(nli10ii));
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and(wire_n00l1O_dataout, n01Oli, ~(nli1i0i));
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and(wire_n00l1O_dataout, n01OiO, ~(nli10ii));
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and(wire_n00lii_dataout, wire_n00lli_dataout, ~((~ nli1iiO)));
|
and(wire_n00lii_dataout, wire_n00lli_dataout, ~((~ nli10lO)));
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and(wire_n00lil_dataout, nli1iii, ~((~ nli1iiO)));
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and(wire_n00lil_dataout, nli10li, ~((~ nli10lO)));
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or(wire_n00liO_dataout, wire_n00lll_dataout, (~ nli1iiO));
|
or(wire_n00liO_dataout, wire_n00lll_dataout, (~ nli10lO));
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and(wire_n00lli_dataout, nli1i0O, ~(nli1iii));
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and(wire_n00lli_dataout, nli10iO, ~(nli10li));
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and(wire_n00lll_dataout, (~ nli1i0O), ~(nli1iii));
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and(wire_n00lll_dataout, (~ nli10iO), ~(nli10li));
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or(wire_n00O1l_dataout, wire_n00O0i_o[0], nli1iiO);
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or(wire_n00O1l_dataout, wire_n00O0i_o[0], nli10lO);
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and(wire_n00O1O_dataout, wire_n00O0i_o[1], ~(nli1iiO));
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and(wire_n00O1O_dataout, wire_n00O0i_o[1], ~(nli10lO));
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and(wire_n0100i_dataout, n0110i, ~(wire_n1i1li_dout));
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and(wire_n0100i_dataout, wire_n1OiiO_o, ~(wire_n1i10O_dout));
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and(wire_n0100l_dataout, n0110l, ~(wire_n1i1li_dout));
|
and(wire_n0100l_dataout, n0110l, ~(wire_n1i10O_dout));
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and(wire_n0100O_dataout, n0110O, ~(wire_n1i1li_dout));
|
and(wire_n0100O_dataout, wire_n1Oili_dataout, ~(wire_n1i10O_dout));
|
or(wire_n010i_dataout, wire_n01ii_dataout, nli0ili);
|
and(wire_n0101i_dataout, wire_n1Oi0O_o, ~(wire_n1i10O_dout));
|
and(wire_n010ii_dataout, wire_n1OiiO_dataout, ~(wire_n1i1li_dout));
|
and(wire_n0101l_dataout, wire_n1Oiil_dataout, ~(wire_n1i10O_dout));
|
and(wire_n010il_dataout, n011il, ~(wire_n1i1li_dout));
|
and(wire_n0101O_dataout, n0111O, ~(wire_n1i10O_dout));
|
and(wire_n010iO_dataout, n011iO, ~(wire_n1i1li_dout));
|
and(wire_n010i_dataout, wire_n01ii_dataout, ~(nli00OO));
|
assign wire_n010l_dataout = (n011i === 1'b1) ? wire_n01il_o[1] : n01iO;
|
and(wire_n010ii_dataout, wire_n1Oill_o, ~(wire_n1i10O_dout));
|
and(wire_n010li_dataout, n011li, ~(wire_n1i1li_dout));
|
and(wire_n010il_dataout, wire_n1OiOl_o, ~(wire_n1i10O_dout));
|
and(wire_n010ll_dataout, wire_n1Oili_o, ~(wire_n1i1li_dout));
|
or(wire_n010iO_dataout, wire_n1Ol1i_o, wire_n1i10O_dout);
|
and(wire_n010lO_dataout, wire_n1OilO_dataout, ~(wire_n1i1li_dout));
|
or(wire_n010l_dataout, wire_n01il_dataout, nli00OO);
|
assign wire_n010O_dataout = (n011i === 1'b1) ? wire_n01il_o[2] : n1OOO;
|
assign wire_n010lO_dataout = (wire_n010Oi_o[1] === 1'b1) ? (~ ((~ n1i01i) & (~ n01i0i))) : (n1i01i | n01i0i);
|
and(wire_n010Oi_dataout, n011Oi, ~(wire_n1i1li_dout));
|
or(wire_n010O_dataout, wire_n01iO_dataout, nli00OO);
|
and(wire_n010Ol_dataout, wire_n1OiOi_o, ~(wire_n1i1li_dout));
|
and(wire_n011iO_dataout, n1OOiO, ~(wire_n1i10O_dout));
|
and(wire_n010OO_dataout, n011OO, ~(wire_n1i1li_dout));
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and(wire_n011li_dataout, n1OOli, ~(wire_n1i10O_dout));
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and(wire_n011l_dataout, wire_n010l_dataout, ~(nli0ili));
|
and(wire_n011ll_dataout, n1OOll, ~(wire_n1i10O_dout));
|
or(wire_n011O_dataout, wire_n010O_dataout, nli0ili);
|
and(wire_n011lO_dataout, wire_n1Oi0l_dataout, ~(wire_n1i10O_dout));
|
or(wire_n01i0i_dataout, wire_n1Ol0l_o, wire_n1i1li_dout);
|
and(wire_n011Oi_dataout, n1OOOi, ~(wire_n1i10O_dout));
|
and(wire_n01i1i_dataout, wire_n1OiOl_dataout, ~(wire_n1i1li_dout));
|
and(wire_n011Ol_dataout, n1OOOl, ~(wire_n1i10O_dout));
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and(wire_n01i1l_dataout, wire_n1OiOO_o, ~(wire_n1i1li_dout));
|
and(wire_n011OO_dataout, n1OOOO, ~(wire_n1i10O_dout));
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and(wire_n01i1O_dataout, wire_n1Ol1O_o, ~(wire_n1i1li_dout));
|
and(wire_n01i1l_dataout, wire_n010lO_dataout, ~(n01i1i));
|
and(wire_n01ii_dataout, wire_n01il_o[3], n011i);
|
assign wire_n01ii_dataout = (n011O === 1'b1) ? wire_n01li_o[1] : n01ll;
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assign wire_n01iii_dataout = (wire_n01iil_o[1] === 1'b1) ? (~ ((~ n1i00l) & (~ n01iOl))) : (n1i00l | n01iOl);
|
assign wire_n01il_dataout = (n011O === 1'b1) ? wire_n01li_o[2] : n011l;
|
and(wire_n01ilO_dataout, wire_n01iii_dataout, ~(n01ill));
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and(wire_n01iO_dataout, wire_n01li_o[3], n011O);
|
or(wire_n01Oll_dataout, (n00O1i & (~ nli10Oi)), (n00O0O & (~ nli10Oi)));
|
assign wire_n01lii_dataout = (n00O0l === 1'b1) ? wire_n01lll_dataout : wire_n01liO_dataout;
|
|
assign wire_n01lil_dataout = (n00O0l === 1'b1) ? wire_n01llO_dataout : wire_n01liO_dataout;
|
|
and(wire_n01liO_dataout, nli11Ol, n00O1i);
|
|
or(wire_n01lll_dataout, n01OOO, nli11Ol);
|
|
or(wire_n01llO_dataout, n01l0l, nli11Ol);
|
|
or(wire_n01Oli_dataout, (n00O1i & (~ nli11OO)), (n00O0O & (~ nli11OO)));
|
and(wire_n0i00i_dataout, wire_n0i0ii_o[1], wire_n0i0il_o);
|
and(wire_n0i00i_dataout, wire_n0i0ii_o[1], wire_n0i0il_o);
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and(wire_n0i00l_dataout, wire_n0i0ii_o[2], wire_n0i0il_o);
|
and(wire_n0i00l_dataout, wire_n0i0ii_o[2], wire_n0i0il_o);
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and(wire_n0i00O_dataout, wire_n0i0ii_o[3], wire_n0i0il_o);
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and(wire_n0i00O_dataout, wire_n0i0ii_o[3], wire_n0i0il_o);
|
and(wire_n0i01O_dataout, wire_n0i0ii_o[0], wire_n0i0il_o);
|
and(wire_n0i01O_dataout, wire_n0i0ii_o[0], wire_n0i0il_o);
|
and(wire_n0iilO_dataout, wire_n0il1i_o[0], wire_n0il1l_o);
|
and(wire_n0iilO_dataout, wire_n0il1i_o[0], wire_n0il1l_o);
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| Line 8108... |
Line 8270... |
and(wire_n0ilil_dataout, wire_n00OOO_q_b[5], n0iOii);
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and(wire_n0ilil_dataout, wire_n00OOO_q_b[5], n0iOii);
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and(wire_n0iliO_dataout, wire_n00OOO_q_b[6], n0iOii);
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and(wire_n0iliO_dataout, wire_n00OOO_q_b[6], n0iOii);
|
and(wire_n0illi_dataout, wire_n00OOO_q_b[7], n0iOii);
|
and(wire_n0illi_dataout, wire_n00OOO_q_b[7], n0iOii);
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and(wire_n0illl_dataout, wire_n00OOO_q_b[8], n0iOii);
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and(wire_n0illl_dataout, wire_n00OOO_q_b[8], n0iOii);
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and(wire_n0illO_dataout, wire_n00OOO_q_b[9], n0iOii);
|
and(wire_n0illO_dataout, wire_n00OOO_q_b[9], n0iOii);
|
assign wire_n0l0lO_dataout = (((n0lili & nli1ill) & (~ ((~ wire_n0illl_dataout) & (n0iO0i & (~ n0l0ll))))) === 1'b1) ? n0Oi1i : wire_n0l0Oi_dataout;
|
assign wire_n0l0lO_dataout = (((n0lili & nli10Ol) & (~ ((~ wire_n0illl_dataout) & (n0iO0i & (~ n0l0ll))))) === 1'b1) ? n0Oi1i : wire_n0l0Oi_dataout;
|
and(wire_n0l0Oi_dataout, n0Oi1i, ((n0lili & (~ nli1ill)) & (~ (n0iO0i & (~ wire_n0illl_dataout)))));
|
and(wire_n0l0Oi_dataout, n0Oi1i, ((n0lili & (~ nli10Ol)) & (~ (n0iO0i & (~ wire_n0illl_dataout)))));
|
or(wire_n0lill_dataout, (~ n0iO0i), wire_n0lilO_o[1]);
|
or(wire_n0lill_dataout, (~ n0iO0i), wire_n0lilO_o[1]);
|
and(wire_n0ll0i_dataout, n0ll1O, n0lO1i);
|
and(wire_n0ll0i_dataout, n0ll1O, n0lO1i);
|
and(wire_n0ll0l_dataout, n0llll, n0lO1i);
|
and(wire_n0ll0l_dataout, n0llll, n0lO1i);
|
and(wire_n0ll0O_dataout, n0lllO, n0lO1i);
|
and(wire_n0ll0O_dataout, n0lllO, n0lO1i);
|
and(wire_n0llii_dataout, n0llOi, n0lO1i);
|
and(wire_n0llii_dataout, n0llOi, n0lO1i);
|
| Line 8121... |
Line 8283... |
and(wire_n0lliO_dataout, n0llOO, n0lO1i);
|
and(wire_n0lliO_dataout, n0llOO, n0lO1i);
|
assign wire_n0lO0i_dataout = (n0Oi1i === 1'b1) ? wire_n0iliO_dataout : wire_n0il0l_dataout;
|
assign wire_n0lO0i_dataout = (n0Oi1i === 1'b1) ? wire_n0iliO_dataout : wire_n0il0l_dataout;
|
assign wire_n0lO0l_dataout = (n0Oi1i === 1'b1) ? wire_n0illi_dataout : wire_n0il0O_dataout;
|
assign wire_n0lO0l_dataout = (n0Oi1i === 1'b1) ? wire_n0illi_dataout : wire_n0il0O_dataout;
|
assign wire_n0lO1l_dataout = (n0Oi1i === 1'b1) ? wire_n0ilii_dataout : wire_n0il1O_dataout;
|
assign wire_n0lO1l_dataout = (n0Oi1i === 1'b1) ? wire_n0ilii_dataout : wire_n0il1O_dataout;
|
assign wire_n0lO1O_dataout = (n0Oi1i === 1'b1) ? wire_n0ilil_dataout : wire_n0il0i_dataout;
|
assign wire_n0lO1O_dataout = (n0Oi1i === 1'b1) ? wire_n0ilil_dataout : wire_n0il0i_dataout;
|
and(wire_n0O00i_dataout, wire_n0ilil_dataout, nli1ilO);
|
and(wire_n0O00i_dataout, wire_n0ilil_dataout, nli10OO);
|
and(wire_n0O00l_dataout, wire_n0iliO_dataout, nli1ilO);
|
and(wire_n0O00l_dataout, wire_n0iliO_dataout, nli10OO);
|
and(wire_n0O00O_dataout, wire_n0illi_dataout, nli1ilO);
|
and(wire_n0O00O_dataout, wire_n0illi_dataout, nli10OO);
|
and(wire_n0O01i_dataout, wire_n0il0l_dataout, nli1ilO);
|
and(wire_n0O01i_dataout, wire_n0il0l_dataout, nli10OO);
|
and(wire_n0O01l_dataout, wire_n0il0O_dataout, nli1ilO);
|
and(wire_n0O01l_dataout, wire_n0il0O_dataout, nli10OO);
|
and(wire_n0O01O_dataout, wire_n0ilii_dataout, nli1ilO);
|
and(wire_n0O01O_dataout, wire_n0ilii_dataout, nli10OO);
|
and(wire_n0O0ii_dataout, wire_n0illl_dataout, nli1ilO);
|
and(wire_n0O0ii_dataout, wire_n0illl_dataout, nli10OO);
|
and(wire_n0O0il_dataout, wire_n0illO_dataout, nli1ilO);
|
and(wire_n0O0il_dataout, wire_n0illO_dataout, nli10OO);
|
and(wire_n0O1Ol_dataout, wire_n0il1O_dataout, nli1ilO);
|
and(wire_n0O1Ol_dataout, wire_n0il1O_dataout, nli10OO);
|
and(wire_n0O1OO_dataout, wire_n0il0i_dataout, nli1ilO);
|
and(wire_n0O1OO_dataout, wire_n0il0i_dataout, nli10OO);
|
assign wire_n0Oi0l_dataout = (nlil01i === 1'b1) ? wire_n0Oi0O_dataout : n0Oi1i;
|
assign wire_n0Oi0l_dataout = (nlil1il === 1'b1) ? wire_n0Oi0O_dataout : n0Oi1i;
|
or(wire_n0Oi0O_dataout, (~ n0Oi1i), nli1ilO);
|
or(wire_n0Oi0O_dataout, (~ n0Oi1i), nli10OO);
|
assign wire_n0OOll_dataout = (nli1iOi === 1'b1) ? ni1i1O : wire_ni110i_dataout;
|
assign wire_n0OOll_dataout = (nli1i1i === 1'b1) ? ni1i1O : wire_ni110i_dataout;
|
assign wire_n0OOlO_dataout = (nli1iOi === 1'b1) ? ni1i0i : wire_ni110l_dataout;
|
assign wire_n0OOlO_dataout = (nli1i1i === 1'b1) ? ni1i0i : wire_ni110l_dataout;
|
assign wire_n0OOOi_dataout = (nli1iOi === 1'b1) ? ni1i0l : wire_ni110O_dataout;
|
assign wire_n0OOOi_dataout = (nli1i1i === 1'b1) ? ni1i0l : wire_ni110O_dataout;
|
assign wire_n0OOOl_dataout = (nli1iOi === 1'b1) ? ni1i0O : wire_ni11ii_dataout;
|
assign wire_n0OOOl_dataout = (nli1i1i === 1'b1) ? ni1i0O : wire_ni11ii_dataout;
|
assign wire_n0OOOO_dataout = (nli1iOi === 1'b1) ? ni1iii : wire_ni11il_dataout;
|
assign wire_n0OOOO_dataout = (nli1i1i === 1'b1) ? ni1iii : wire_ni11il_dataout;
|
and(wire_n1000i_dataout, wire_n10iil_dataout, ~(n1i11l));
|
and(wire_n1000i_dataout, wire_n10iii_dataout, ~(n10OOi));
|
and(wire_n1000l_dataout, wire_n10iiO_dataout, ~(n1i11l));
|
and(wire_n1000l_dataout, wire_n10iil_dataout, ~(n10OOi));
|
and(wire_n1000O_dataout, (~ nil1i), ~(n1i11l));
|
and(wire_n1000O_dataout, wire_n10iiO_dataout, ~(n10OOi));
|
and(wire_n1001i_dataout, wire_n10i0l_dataout, ~(n1i11l));
|
and(wire_n1001i_dataout, wire_n10i0l_dataout, ~(n10OOi));
|
and(wire_n1001l_dataout, wire_n10i0O_dataout, ~(n1i11l));
|
and(wire_n1001l_dataout, (~ niO1i), ~(n10OOi));
|
and(wire_n1001O_dataout, wire_n10iii_dataout, ~(n1i11l));
|
and(wire_n1001O_dataout, wire_n10i0O_dataout, ~(n10OOi));
|
and(wire_n100ii_dataout, wire_n10ili_dataout, ~(n1i11l));
|
assign wire_n100i_dataout = (n11OO === 1'b1) ? wire_n100O_o[1] : n10ii;
|
and(wire_n100il_dataout, wire_n10ill_dataout, ~(n1i11l));
|
and(wire_n100ii_dataout, wire_n10ili_dataout, ~(n10OOi));
|
and(wire_n100iO_dataout, wire_n10ilO_dataout, ~(n1i11l));
|
and(wire_n100il_dataout, wire_n10ill_dataout, ~(n10OOi));
|
and(wire_n100li_dataout, wire_n10iOi_dataout, ~(n1i11l));
|
and(wire_n100iO_dataout, wire_n10ilO_dataout, ~(n10OOi));
|
and(wire_n100ll_dataout, wire_n10iOl_dataout, ~(n1i11l));
|
and(wire_n100l_dataout, wire_n100O_o[2], n11OO);
|
and(wire_n100lO_dataout, wire_n10iOO_dataout, ~(n1i11l));
|
and(wire_n100li_dataout, wire_n10iOi_dataout, ~(n10OOi));
|
and(wire_n100Oi_dataout, wire_n10l1i_dataout, ~(n1i11l));
|
and(wire_n100ll_dataout, wire_n10iOl_dataout, ~(n10OOi));
|
and(wire_n100Ol_dataout, wire_n10l1l_dataout, ~(n1i11l));
|
and(wire_n100lO_dataout, wire_n10iOO_dataout, ~(n10OOi));
|
and(wire_n100OO_dataout, wire_n10l1O_dataout, ~(n1i11l));
|
and(wire_n100Oi_dataout, wire_n10l1i_dataout, ~(n10OOi));
|
or(wire_n10i0i_dataout, wire_n10lii_dataout, n1i11l);
|
and(wire_n100Ol_dataout, wire_n10l1l_dataout, ~(n10OOi));
|
and(wire_n10i0l_dataout, wire_nlOOOil_o, ~((~ nil1i)));
|
or(wire_n100OO_dataout, wire_n10l1O_dataout, n10OOi);
|
and(wire_n10i0O_dataout, wire_nlOOOli_dataout, ~((~ nil1i)));
|
or(wire_n101l_dataout, wire_n100i_dataout, nli000O);
|
and(wire_n10i1i_dataout, wire_n10l0i_dataout, ~(n1i11l));
|
and(wire_n101lO_dataout, wire_n10i1i_dataout, ~(n10OOi));
|
and(wire_n10i1l_dataout, wire_n10l0l_dataout, ~(n1i11l));
|
or(wire_n101O_dataout, wire_n100l_dataout, nli000O);
|
and(wire_n10i1O_dataout, wire_n10l0O_dataout, ~(n1i11l));
|
and(wire_n101Oi_dataout, wire_n10i1l_dataout, ~(n10OOi));
|
and(wire_n10iii_dataout, wire_nlOOOll_dataout, ~((~ nil1i)));
|
and(wire_n101Ol_dataout, wire_n10i1O_dataout, ~(n10OOi));
|
and(wire_n10iil_dataout, wire_nlOOOlO_o, ~((~ nil1i)));
|
and(wire_n101OO_dataout, wire_n10i0i_dataout, ~(n10OOi));
|
and(wire_n10iiO_dataout, wire_nlOOOOl_o, ~((~ nil1i)));
|
and(wire_n10i0i_dataout, wire_nlOOOil_o, ~((~ niO1i)));
|
and(wire_n10ili_dataout, wire_n1111i_o, ~((~ nil1i)));
|
and(wire_n10i0l_dataout, wire_nlOOOli_o, ~((~ niO1i)));
|
and(wire_n10ill_dataout, wire_n1111O_dataout, ~((~ nil1i)));
|
and(wire_n10i0O_dataout, wire_nlOOOlO_o, ~((~ niO1i)));
|
and(wire_n10ilO_dataout, wire_n1110i_o, ~((~ nil1i)));
|
and(wire_n10i1i_dataout, wire_nlOOO0i_o, ~((~ niO1i)));
|
and(wire_n10iOi_dataout, wire_n1110l_o, ~((~ nil1i)));
|
and(wire_n10i1l_dataout, wire_nlOOO0O_dataout, ~((~ niO1i)));
|
and(wire_n10iOl_dataout, wire_n111ii_dataout, ~((~ nil1i)));
|
and(wire_n10i1O_dataout, wire_nlOOOii_dataout, ~((~ niO1i)));
|
and(wire_n10iOO_dataout, wire_n111il_o, ~((~ nil1i)));
|
and(wire_n10iii_dataout, wire_nlOOOOl_dataout, ~((~ niO1i)));
|
and(wire_n10l0i_dataout, wire_n111Ol_o, ~((~ nil1i)));
|
and(wire_n10iil_dataout, wire_nlOOOOO_o, ~((~ niO1i)));
|
and(wire_n10l0l_dataout, wire_n1101i_o, ~((~ nil1i)));
|
and(wire_n10iiO_dataout, wire_n1111i_o, ~((~ niO1i)));
|
and(wire_n10l0O_dataout, wire_n1101O_o, ~((~ nil1i)));
|
and(wire_n10ili_dataout, wire_n1111O_dataout, ~((~ niO1i)));
|
and(wire_n10l1i_dataout, wire_n111li_dataout, ~((~ nil1i)));
|
and(wire_n10ill_dataout, wire_n1110i_o, ~((~ niO1i)));
|
and(wire_n10l1l_dataout, wire_n111ll_dataout, ~((~ nil1i)));
|
and(wire_n10ilO_dataout, wire_n1110O_dataout, ~((~ niO1i)));
|
and(wire_n10l1O_dataout, wire_n111lO_o, ~((~ nil1i)));
|
and(wire_n10iOi_dataout, wire_n111ii_dataout, ~((~ niO1i)));
|
and(wire_n10lii_dataout, wire_n1100l_o, ~((~ nil1i)));
|
and(wire_n10iOl_dataout, wire_n111il_o, ~((~ niO1i)));
|
and(wire_n10O0l_dataout, n0l1i, ~(n1i11l));
|
and(wire_n10iOO_dataout, wire_n111li_o, ~((~ niO1i)));
|
and(wire_n10O0O_dataout, nil0O, ~(n1i11l));
|
and(wire_n10l1i_dataout, wire_n111lO_o, ~((~ niO1i)));
|
and(wire_n10Oii_dataout, nilli, ~(n1i11l));
|
and(wire_n10l1l_dataout, wire_n111Ol_o, ~((~ niO1i)));
|
and(wire_n10Oil_dataout, nilll, ~(n1i11l));
|
and(wire_n10l1O_dataout, wire_n1101i_o, ~((~ niO1i)));
|
and(wire_n10OiO_dataout, nillO, ~(n1i11l));
|
and(wire_n10O0i_dataout, niOll, ~(n10OOi));
|
and(wire_n10Oli_dataout, nilOi, ~(n1i11l));
|
and(wire_n10O0l_dataout, niOlO, ~(n10OOi));
|
and(wire_n10Oll_dataout, nilOl, ~(n1i11l));
|
and(wire_n10O0O_dataout, niOOi, ~(n10OOi));
|
and(wire_n10OlO_dataout, nilOO, ~(n1i11l));
|
and(wire_n10O1i_dataout, n0O1i, ~(n10OOi));
|
and(wire_n10OOi_dataout, niO1i, ~(n1i11l));
|
and(wire_n10O1l_dataout, niO0O, ~(n10OOi));
|
and(wire_n10OOl_dataout, niO1l, ~(n1i11l));
|
and(wire_n10O1O_dataout, niOli, ~(n10OOi));
|
and(wire_n10OOO_dataout, nilii, ~(n1i11l));
|
and(wire_n10Oii_dataout, niOOl, ~(n10OOi));
|
and(wire_n110ii_dataout, wire_n110li_dataout, ~(nl0OOOl));
|
and(wire_n10Oil_dataout, niOOO, ~(n10OOi));
|
and(wire_n110il_dataout, wire_n110ll_dataout, ~(nl0OOOl));
|
and(wire_n10OiO_dataout, nl11i, ~(n10OOi));
|
and(wire_n110iO_dataout, nli11ii, ~(nl0OOOl));
|
and(wire_n10Oli_dataout, nl11l, ~(n10OOi));
|
and(wire_n110li_dataout, nl0OO0O, ~(nli11ii));
|
and(wire_n10Oll_dataout, niOii, ~(n10OOi));
|
and(wire_n110ll_dataout, (~ nl0OO0O), ~(nli11ii));
|
and(wire_n10OOl_dataout, wire_n10OOO_dataout, niO1i);
|
and(wire_n110Oi_dataout, nl0OO0O, ~(nli111l));
|
or(wire_n10OOO_dataout, (~ n10OlO), ((~ n10lOO) & niO1i));
|
and(wire_n110Ol_dataout, (~ nl0OO0O), ~(nli111l));
|
and(wire_n1100i_dataout, wire_n110ii_dataout, ~(nl0OO1l));
|
and(wire_n110OO_dataout, wire_n11i0i_dataout, ~(nl0OOll));
|
and(wire_n1100l_dataout, nl0OOli, ~(nl0OO1l));
|
and(wire_n1111O_dataout, (~ nl0OOOO), n1010l);
|
and(wire_n1100O_dataout, nl0OliO, ~(nl0OOli));
|
and(wire_n111ii_dataout, wire_n11i1l_dataout, n101ll);
|
and(wire_n1101O_dataout, wire_n1100O_dataout, ~(nl0OO1l));
|
and(wire_n111li_dataout, nl0OO0O, n101li);
|
and(wire_n110ii_dataout, (~ nl0OliO), ~(nl0OOli));
|
and(wire_n111ll_dataout, nl0OOll, n101ll);
|
and(wire_n110iO_dataout, nl0OliO, ~(nl0OO0l));
|
and(wire_n11i0i_dataout, wire_n11iii_dataout, ~(nl0OOiO));
|
and(wire_n110li_dataout, (~ nl0OliO), ~(nl0OO0l));
|
and(wire_n11i0l_dataout, nl0OOil, ~(nl0OOiO));
|
and(wire_n110ll_dataout, wire_n110OO_dataout, ~(nl0OlOl));
|
and(wire_n11i0O_dataout, wire_n11iil_dataout, ~(nl0OOiO));
|
and(wire_n110lO_dataout, nl0OllO, ~(nl0OlOl));
|
and(wire_n11i1i_dataout, nl0OOiO, ~(nl0OOll));
|
and(wire_n110Oi_dataout, wire_n11i1i_dataout, ~(nl0OlOl));
|
and(wire_n11i1l_dataout, wire_n11i0l_dataout, ~(nl0OOll));
|
and(wire_n110Ol_dataout, wire_n11i1l_dataout, ~(nl0OlOl));
|
and(wire_n11i1O_dataout, wire_n11i0O_dataout, ~(nl0OOll));
|
and(wire_n110OO_dataout, wire_n11i1O_dataout, ~(nl0OllO));
|
or(wire_n11ii_dataout, wire_n11iO_dataout, nli0i1l);
|
and(wire_n1110O_dataout, nl0OliO, n1010O);
|
and(wire_n11iii_dataout, nl0OO0O, ~(nl0OOil));
|
and(wire_n1111O_dataout, wire_n110Oi_dataout, n101ii);
|
and(wire_n11iil_dataout, (~ nl0OO0O), ~(nl0OOil));
|
and(wire_n111ii_dataout, nl0OlOl, n101ii);
|
or(wire_n11il_dataout, wire_n11li_dataout, nli0i1l);
|
and(wire_n11i0i_dataout, (~ nl0OliO), ~(nl0Olll));
|
assign wire_n11iO_dataout = (n110l === 1'b1) ? wire_n11ll_o[1] : n11lO;
|
and(wire_n11i1i_dataout, nl0Olll, ~(nl0OllO));
|
and(wire_n11iOO_dataout, (~ nl0OOOi), ~(nl0OOOl));
|
and(wire_n11i1l_dataout, wire_n11i0i_dataout, ~(nl0OllO));
|
and(wire_n11l0i_dataout, nl0OOOl, ~(n10liO));
|
and(wire_n11i1O_dataout, nl0OliO, ~(nl0Olll));
|
and(wire_n11l0O_dataout, wire_n11liO_dataout, ~(nli110O));
|
and(wire_n11ill_dataout, (~ nl0OO1i), ~(nl0OO1l));
|
and(wire_n11l1i_dataout, nl0OOOi, ~(nl0OOOl));
|
and(wire_n11ilO_dataout, nl0OO1i, ~(nl0OO1l));
|
or(wire_n11l1O_dataout, (~ nl0OOOl), n10liO);
|
or(wire_n11iOl_dataout, (~ nl0OO1l), n10l0l);
|
and(wire_n11li_dataout, wire_n11ll_o[2], n110l);
|
and(wire_n11iOO_dataout, nl0OO1l, ~(n10l0l));
|
and(wire_n11lii_dataout, wire_n11lli_dataout, ~(nli110O));
|
and(wire_n11l0i_dataout, wire_n11lii_dataout, ~(nl0OOiO));
|
and(wire_n11lil_dataout, wire_n11lll_dataout, ~(nli110O));
|
and(wire_n11l0l_dataout, wire_n11lil_dataout, ~(nl0OOii));
|
and(wire_n11liO_dataout, wire_n11llO_dataout, ~(nli110i));
|
or(wire_n11l0O_dataout, nl0OO0O, nl0OOii);
|
or(wire_n11lli_dataout, nli111O, nli110i);
|
and(wire_n11l1l_dataout, wire_n11l0l_dataout, ~(nl0OOiO));
|
and(wire_n11lll_dataout, wire_n11lOi_dataout, ~(nli110i));
|
and(wire_n11l1O_dataout, wire_n11l0O_dataout, ~(nl0OOiO));
|
and(wire_n11llO_dataout, nli111i, ~(nli111O));
|
and(wire_n11lii_dataout, wire_n11liO_dataout, ~(nl0OOii));
|
and(wire_n11lOi_dataout, (~ nli111i), ~(nli111O));
|
and(wire_n11lil_dataout, nl0OO0i, ~(nl0OO0O));
|
and(wire_n11Oil_dataout, nli11iO, ~(nli11li));
|
and(wire_n11liO_dataout, (~ nl0OO0i), ~(nl0OO0O));
|
and(wire_n11OiO_dataout, (~ nli11iO), ~(nli11li));
|
and(wire_n11O0i_dataout, nl0OOlO, ~(nl0OOOi));
|
or(wire_n1i00i_dataout, (~ n1i1lO), nli11Ol);
|
and(wire_n11O0l_dataout, (~ nl0OOlO), ~(nl0OOOi));
|
or(wire_n1i01l_dataout, wire_n1i01O_dataout, wire_n1i1li_dout);
|
or(wire_n1i0ll_dataout, wire_n1ii0l_dataout, wire_n1i10O_dout);
|
or(wire_n1i01O_dataout, wire_n1i00i_dataout, wire_n1Oili_o);
|
and(wire_n1i0lO_dataout, wire_n1ii0O_dataout, ~(wire_n1i10O_dout));
|
or(wire_n1i0OO_dataout, wire_n1iiiO_dataout, wire_n1i1li_dout);
|
and(wire_n1i0Oi_dataout, wire_n1iiii_dataout, ~(wire_n1i10O_dout));
|
or(wire_n1i10i_dataout, (~ n1i11i), ((~ n10O0i) & nil1i));
|
or(wire_n1i0Ol_dataout, wire_n1iiil_dataout, wire_n1i10O_dout);
|
and(wire_n1i11O_dataout, wire_n1i10i_dataout, nil1i);
|
or(wire_n1i0OO_dataout, wire_n1iiiO_dataout, wire_n1i10O_dout);
|
and(wire_n1i1Oi_dataout, wire_n1i1Ol_dataout, ~(wire_n1i1li_dout));
|
and(wire_n1i1iO_dataout, wire_n1i1li_dataout, ~(wire_n1i10O_dout));
|
or(wire_n1i1Ol_dataout, wire_n1i1OO_dataout, wire_n1Ol1O_o);
|
or(wire_n1i1li_dataout, wire_n1i1ll_dataout, wire_n1OiOl_o);
|
and(wire_n1i1OO_dataout, n1i00l, ~(wire_n1OiOl_dataout));
|
and(wire_n1i1ll_dataout, n1i01i, ~(wire_n1Oili_dataout));
|
or(wire_n1ii0i_dataout, wire_n1iiOi_dataout, wire_n1i1li_dout);
|
or(wire_n1i1Oi_dataout, wire_n1i1Ol_dataout, wire_n1i10O_dout);
|
or(wire_n1ii0l_dataout, wire_n1iiOl_dataout, wire_n1i1li_dout);
|
or(wire_n1i1Ol_dataout, wire_n1i1OO_dataout, wire_n1Oi0O_o);
|
or(wire_n1ii0O_dataout, wire_n1iiOO_dataout, wire_n1i1li_dout);
|
or(wire_n1i1OO_dataout, (~ n1i1il), nli111l);
|
and(wire_n1ii1i_dataout, wire_n1iili_dataout, ~(wire_n1i1li_dout));
|
or(wire_n1ii0i_dataout, wire_n1iiOi_dataout, wire_n1i10O_dout);
|
and(wire_n1ii1l_dataout, wire_n1iill_dataout, ~(wire_n1i1li_dout));
|
or(wire_n1ii0l_dataout, wire_n1iiOl_dataout, wire_n1OiOl_o);
|
or(wire_n1ii1O_dataout, wire_n1iilO_dataout, wire_n1i1li_dout);
|
or(wire_n1ii0O_dataout, wire_n1iiOO_dataout, wire_n1OiOl_o);
|
or(wire_n1iii_dataout, wire_n1iiO_o[1], (~ nli0i0l));
|
or(wire_n1ii1i_dataout, wire_n1iili_dataout, wire_n1i10O_dout);
|
and(wire_n1iiii_dataout, wire_n1il1i_dataout, ~(wire_n1i1li_dout));
|
or(wire_n1ii1l_dataout, wire_n1iill_dataout, wire_n1i10O_dout);
|
or(wire_n1iiil_dataout, wire_n1il1l_dataout, wire_n1i1li_dout);
|
and(wire_n1ii1O_dataout, wire_n1iilO_dataout, ~(wire_n1i10O_dout));
|
or(wire_n1iiiO_dataout, wire_n1il1O_dataout, wire_n1Ol1O_o);
|
or(wire_n1iiii_dataout, wire_n1il1i_dataout, wire_n1OiOl_o);
|
or(wire_n1iil_dataout, wire_n1iiO_o[2], (~ nli0i0l));
|
and(wire_n1iiil_dataout, wire_n1il1l_dataout, ~(wire_n1OiOl_o));
|
or(wire_n1iili_dataout, wire_n1il0i_dataout, wire_n1Ol1O_o);
|
or(wire_n1iiiO_dataout, wire_n1il1O_dataout, wire_n1OiOl_o);
|
or(wire_n1iill_dataout, wire_n1il0l_dataout, wire_n1Ol1O_o);
|
or(wire_n1iili_dataout, wire_n1il0i_dataout, wire_n1OiOl_o);
|
and(wire_n1iilO_dataout, wire_n1il0O_dataout, ~(wire_n1Ol1O_o));
|
or(wire_n1iill_dataout, wire_n1il0l_dataout, wire_n1OiOl_o);
|
or(wire_n1iiOi_dataout, wire_n1ilii_dataout, wire_n1Ol1O_o);
|
or(wire_n1iilO_dataout, wire_n1il0O_dataout, wire_n1OiOl_o);
|
or(wire_n1iiOl_dataout, wire_n1ilil_dataout, wire_n1Ol1O_o);
|
or(wire_n1iiOi_dataout, wire_n1ilii_dataout, wire_n1OiOl_o);
|
or(wire_n1iiOO_dataout, wire_n1iliO_dataout, wire_n1Ol1O_o);
|
or(wire_n1iiOl_dataout, wire_n1ilil_dataout, wire_n1Oili_dataout);
|
or(wire_n1il0i_dataout, wire_n1ilOi_dataout, wire_n1OiOl_dataout);
|
or(wire_n1iiOO_dataout, wire_n1iliO_dataout, wire_n1Oili_dataout);
|
and(wire_n1il0l_dataout, wire_n1ilOl_dataout, ~(wire_n1OiOl_dataout));
|
or(wire_n1il0i_dataout, wire_n1ilOi_dataout, wire_n1Oili_dataout);
|
or(wire_n1il0O_dataout, wire_n1ilOO_dataout, wire_n1OiOl_dataout);
|
or(wire_n1il0l_dataout, wire_n1ilOl_dataout, wire_n1Oili_dataout);
|
or(wire_n1il1i_dataout, wire_n1illi_dataout, wire_n1Ol1O_o);
|
or(wire_n1il0O_dataout, wire_n1ilOO_dataout, wire_n1Oili_dataout);
|
or(wire_n1il1l_dataout, wire_n1illl_dataout, wire_n1Ol1O_o);
|
and(wire_n1il1i_dataout, wire_n1illi_dataout, ~(wire_n1Oili_dataout));
|
or(wire_n1il1O_dataout, wire_n1illO_dataout, wire_n1OiOl_dataout);
|
or(wire_n1il1l_dataout, wire_n1illl_dataout, wire_n1Oili_dataout);
|
or(wire_n1ilii_dataout, wire_n1iO1i_dataout, wire_n1OiOl_dataout);
|
or(wire_n1il1O_dataout, wire_n1illO_dataout, wire_n1Oili_dataout);
|
or(wire_n1ilil_dataout, wire_n1iO1l_dataout, wire_n1OiOl_dataout);
|
or(wire_n1ilii_dataout, wire_n1iO1i_dataout, wire_n1Oili_dataout);
|
or(wire_n1iliO_dataout, wire_n1iO1O_dataout, wire_n1OiOl_dataout);
|
or(wire_n1ilil_dataout, wire_n1iO1l_dataout, n0110l);
|
or(wire_n1illi_dataout, wire_n1iO0i_dataout, wire_n1OiOl_dataout);
|
or(wire_n1iliO_dataout, wire_n1iO1O_dataout, n0110l);
|
or(wire_n1illl_dataout, wire_n1iO0l_dataout, wire_n1OiOl_dataout);
|
or(wire_n1illi_dataout, wire_n1iO0i_dataout, n0110l);
|
or(wire_n1illO_dataout, wire_n1iO0O_dataout, n011OO);
|
or(wire_n1illl_dataout, wire_n1iO0l_dataout, n0110l);
|
or(wire_n1ilOi_dataout, wire_n1iOii_dataout, n011OO);
|
and(wire_n1illO_dataout, wire_n1iO0O_dataout, ~(n0110l));
|
or(wire_n1ilOl_dataout, wire_n1iOil_dataout, n011OO);
|
or(wire_n1ilOi_dataout, wire_n1iOii_dataout, n0110l);
|
or(wire_n1ilOO_dataout, wire_n1iOiO_dataout, n011OO);
|
or(wire_n1ilOl_dataout, wire_n1iOil_dataout, n0110l);
|
or(wire_n1iO0i_dataout, wire_n1iOOi_dataout, n011OO);
|
or(wire_n1ilOO_dataout, wire_n1iOiO_dataout, n0110l);
|
or(wire_n1iO0l_dataout, wire_n1iOOl_dataout, n011OO);
|
or(wire_n1iO0i_dataout, wire_n1iOOi_dataout, wire_n1Oiil_dataout);
|
or(wire_n1iO0O_dataout, wire_n1iOOO_dataout, wire_n1OilO_dataout);
|
or(wire_n1iO0l_dataout, wire_n1iOOl_dataout, wire_n1Oiil_dataout);
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and(wire_n1iO1i_dataout, wire_n1iOli_dataout, ~(n011OO));
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and(wire_n1iO0O_dataout, wire_n1iOOO_dataout, ~(wire_n1Oiil_dataout));
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or(wire_n1iO1l_dataout, wire_n1iOll_dataout, n011OO);
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or(wire_n1iO1i_dataout, wire_n1iOli_dataout, n0110l);
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or(wire_n1iO1O_dataout, wire_n1iOlO_dataout, n011OO);
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or(wire_n1iO1l_dataout, wire_n1iOll_dataout, wire_n1Oiil_dataout);
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or(wire_n1iOii_dataout, wire_n1l11i_dataout, wire_n1OilO_dataout);
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or(wire_n1iO1O_dataout, wire_n1iOlO_dataout, wire_n1Oiil_dataout);
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or(wire_n1iOil_dataout, wire_n1l11l_dataout, wire_n1OilO_dataout);
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or(wire_n1iOii_dataout, wire_n1l11i_dataout, wire_n1Oiil_dataout);
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or(wire_n1iOiO_dataout, wire_n1l11O_dataout, wire_n1OilO_dataout);
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or(wire_n1iOil_dataout, wire_n1l11l_dataout, wire_n1Oiil_dataout);
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and(wire_n1iOli_dataout, wire_n1l10i_dataout, ~(wire_n1OilO_dataout));
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or(wire_n1iOiO_dataout, wire_n1l11O_dataout, wire_n1Oiil_dataout);
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or(wire_n1iOll_dataout, wire_n1l10l_dataout, wire_n1OilO_dataout);
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or(wire_n1iOli_dataout, wire_n1l10i_dataout, wire_n1Oiil_dataout);
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or(wire_n1iOlO_dataout, wire_n1l10O_dataout, wire_n1OilO_dataout);
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or(wire_n1iOll_dataout, wire_n1l10l_dataout, wire_n1OiiO_o);
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or(wire_n1iOOi_dataout, wire_n1l1ii_dataout, wire_n1OilO_dataout);
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or(wire_n1iOlO_dataout, wire_n1l10O_dataout, wire_n1OiiO_o);
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or(wire_n1iOOl_dataout, wire_n1l1il_dataout, wire_n1OilO_dataout);
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or(wire_n1iOOi_dataout, wire_n1l1ii_dataout, wire_n1OiiO_o);
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or(wire_n1iOOO_dataout, wire_n1l1iO_dataout, wire_n1OiOi_o);
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or(wire_n1iOOl_dataout, wire_n1l1il_dataout, wire_n1OiiO_o);
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and(wire_n1l00i_dataout, wire_n1l0Oi_dataout, ~(nli11OO));
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and(wire_n1iOOO_dataout, wire_n1l1iO_dataout, ~(wire_n1OiiO_o));
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or(wire_n1l00l_dataout, wire_n1l0Ol_dataout, nli11OO);
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or(wire_n1l00i_dataout, wire_n1l0Oi_dataout, nli111O);
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or(wire_n1l00O_dataout, wire_n1l0OO_dataout, nli11OO);
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or(wire_n1l00l_dataout, wire_n1l0Ol_dataout, nli111O);
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or(wire_n1l01i_dataout, wire_n1l0li_dataout, n011Oi);
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or(wire_n1l00O_dataout, wire_n1l0OO_dataout, nli111O);
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or(wire_n1l01l_dataout, wire_n1l0ll_dataout, n011Oi);
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or(wire_n1l01i_dataout, wire_n1l0li_dataout, nli111O);
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or(wire_n1l01O_dataout, wire_n1l0lO_dataout, nli11OO);
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or(wire_n1l01l_dataout, wire_n1l0ll_dataout, nli111O);
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or(wire_n1l0ii_dataout, wire_n1li1i_dataout, nli11OO);
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or(wire_n1l01O_dataout, wire_n1l0lO_dataout, nli111O);
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or(wire_n1l0il_dataout, wire_n1li1l_dataout, nli11OO);
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or(wire_n1l0ii_dataout, wire_n1li1i_dataout, nli111O);
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or(wire_n1l0iO_dataout, wire_n1li1O_dataout, nli11OO);
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and(wire_n1l0il_dataout, wire_n1li1l_dataout, ~(wire_n1Oill_o));
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or(wire_n1l0li_dataout, wire_n1li0i_dataout, nli11OO);
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assign wire_n1l0iO_dataout = (wire_n1Oill_o === 1'b1) ? nii00O : wire_n1li1O_dataout;
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or(wire_n1l0ll_dataout, wire_n1li0l_dataout, nli11OO);
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assign wire_n1l0li_dataout = (wire_n1Oill_o === 1'b1) ? nii0ii : wire_n1li0i_dataout;
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and(wire_n1l0lO_dataout, wire_n1li0O_dataout, ~(wire_n1OiOO_o));
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assign wire_n1l0ll_dataout = (wire_n1Oill_o === 1'b1) ? nii0il : wire_n1li0l_dataout;
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assign wire_n1l0Oi_dataout = (wire_n1OiOO_o === 1'b1) ? nii00O : wire_n1liii_dataout;
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assign wire_n1l0lO_dataout = (wire_n1Oill_o === 1'b1) ? nii0iO : wire_n1li0O_dataout;
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assign wire_n1l0Ol_dataout = (wire_n1OiOO_o === 1'b1) ? nii0ii : wire_n1liil_dataout;
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assign wire_n1l0Oi_dataout = (wire_n1Oill_o === 1'b1) ? nii0li : wire_n1liii_dataout;
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assign wire_n1l0OO_dataout = (wire_n1OiOO_o === 1'b1) ? nii0il : wire_n1liiO_dataout;
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assign wire_n1l0Ol_dataout = (wire_n1Oill_o === 1'b1) ? nii0ll : wire_n1liil_dataout;
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and(wire_n1l10i_dataout, wire_n1l1Oi_dataout, ~(wire_n1OiOi_o));
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assign wire_n1l0OO_dataout = (wire_n1Oill_o === 1'b1) ? nii0lO : wire_n1liiO_dataout;
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or(wire_n1l10l_dataout, wire_n1l1Ol_dataout, wire_n1OiOi_o);
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or(wire_n1l10i_dataout, wire_n1l1Oi_dataout, wire_n1OiiO_o);
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or(wire_n1l10O_dataout, wire_n1l1OO_dataout, wire_n1OiOi_o);
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or(wire_n1l10l_dataout, wire_n1l1Ol_dataout, n0111O);
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or(wire_n1l11i_dataout, wire_n1l1li_dataout, wire_n1OiOi_o);
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and(wire_n1l10O_dataout, wire_n1l1OO_dataout, ~(n0111O));
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or(wire_n1l11l_dataout, wire_n1l1ll_dataout, wire_n1OiOi_o);
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or(wire_n1l11i_dataout, wire_n1l1li_dataout, wire_n1OiiO_o);
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or(wire_n1l11O_dataout, wire_n1l1lO_dataout, wire_n1OiOi_o);
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or(wire_n1l11l_dataout, wire_n1l1ll_dataout, wire_n1OiiO_o);
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or(wire_n1l1ii_dataout, wire_n1l01i_dataout, wire_n1OiOi_o);
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or(wire_n1l11O_dataout, wire_n1l1lO_dataout, wire_n1OiiO_o);
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or(wire_n1l1il_dataout, wire_n1l01l_dataout, wire_n1OiOi_o);
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or(wire_n1l1ii_dataout, wire_n1l01i_dataout, n0111O);
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or(wire_n1l1iO_dataout, wire_n1l01O_dataout, n011Oi);
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or(wire_n1l1il_dataout, wire_n1l01l_dataout, n0111O);
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and(wire_n1l1li_dataout, wire_n1l00i_dataout, ~(n011Oi));
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or(wire_n1l1iO_dataout, wire_n1l01O_dataout, n0111O);
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or(wire_n1l1ll_dataout, wire_n1l00l_dataout, n011Oi);
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or(wire_n1l1l_dataout, wire_n1l0i_o[1], (~ nli00iO));
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or(wire_n1l1lO_dataout, wire_n1l00O_dataout, n011Oi);
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or(wire_n1l1li_dataout, wire_n1l00i_dataout, n0111O);
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or(wire_n1l1Oi_dataout, wire_n1l0ii_dataout, n011Oi);
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or(wire_n1l1ll_dataout, wire_n1l00l_dataout, n0111O);
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or(wire_n1l1Ol_dataout, wire_n1l0il_dataout, n011Oi);
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or(wire_n1l1lO_dataout, wire_n1l00O_dataout, n0111O);
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or(wire_n1l1OO_dataout, wire_n1l0iO_dataout, n011Oi);
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or(wire_n1l1O_dataout, wire_n1l0i_o[2], (~ nli00iO));
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assign wire_n1li0i_dataout = (wire_n1OiOO_o === 1'b1) ? nii0lO : wire_n1liOi_dataout;
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or(wire_n1l1Oi_dataout, wire_n1l0ii_dataout, n0111O);
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assign wire_n1li0l_dataout = (wire_n1OiOO_o === 1'b1) ? nii0Oi : wire_n1liOl_dataout;
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or(wire_n1l1Ol_dataout, wire_n1l0il_dataout, nli111O);
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or(wire_n1li0O_dataout, wire_n1liOO_dataout, wire_n1Oili_o);
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and(wire_n1l1OO_dataout, wire_n1l0iO_dataout, ~(nli111O));
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assign wire_n1li1i_dataout = (wire_n1OiOO_o === 1'b1) ? nii0iO : wire_n1lili_dataout;
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and(wire_n1li0i_dataout, wire_n1liOi_dataout, ~(wire_n1Oi0O_o));
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assign wire_n1li1l_dataout = (wire_n1OiOO_o === 1'b1) ? nii0li : wire_n1lill_dataout;
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or(wire_n1li0l_dataout, wire_n1liOl_dataout, wire_n1Oi0O_o);
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assign wire_n1li1O_dataout = (wire_n1OiOO_o === 1'b1) ? nii0ll : wire_n1lilO_dataout;
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or(wire_n1li0O_dataout, wire_n1liOO_dataout, wire_n1Oi0O_o);
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or(wire_n1lii_dataout, wire_n1lll_o[1], (~ nli0iil));
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assign wire_n1li1i_dataout = (wire_n1Oill_o === 1'b1) ? nii0Oi : wire_n1lili_dataout;
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and(wire_n1liii_dataout, wire_n1ll1i_dataout, ~(wire_n1Oili_o));
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or(wire_n1li1l_dataout, wire_n1lill_dataout, wire_n1Oi0O_o);
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and(wire_n1liil_dataout, wire_n1ll1l_dataout, ~(wire_n1Oili_o));
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and(wire_n1li1O_dataout, wire_n1lilO_dataout, ~(wire_n1Oi0O_o));
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or(wire_n1liiO_dataout, wire_n1ll1O_dataout, wire_n1Oili_o);
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or(wire_n1liii_dataout, wire_n1ll1i_dataout, wire_n1Oi0O_o);
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or(wire_n1lil_dataout, wire_n1lll_o[2], (~ nli0iil));
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or(wire_n1liil_dataout, wire_n1ll1l_dataout, wire_n1Oi0O_o);
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or(wire_n1lili_dataout, wire_n1ll0i_dataout, wire_n1Oili_o);
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and(wire_n1liiO_dataout, wire_n1ll1O_dataout, ~(wire_n1Oi0O_o));
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or(wire_n1lill_dataout, wire_n1ll0l_dataout, wire_n1Oili_o);
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or(wire_n1lili_dataout, wire_n1ll0i_dataout, wire_n1Oi0O_o);
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or(wire_n1lilO_dataout, wire_n1ll0O_dataout, wire_n1Oili_o);
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and(wire_n1lill_dataout, wire_n1ll0l_dataout, ~(n1OOOO));
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or(wire_n1liO_dataout, wire_n1lll_o[3], (~ nli0iil));
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or(wire_n1lilO_dataout, wire_n1ll0O_dataout, n1OOOO);
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and(wire_n1liOi_dataout, wire_n1llii_dataout, ~(wire_n1Oili_o));
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and(wire_n1liOi_dataout, wire_n1llii_dataout, ~(n1OOOO));
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or(wire_n1liOl_dataout, wire_n1llil_dataout, wire_n1Oili_o);
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or(wire_n1liOl_dataout, wire_n1llil_dataout, n1OOOO);
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and(wire_n1liOO_dataout, wire_n1lliO_dataout, ~(n011li));
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and(wire_n1liOO_dataout, wire_n1lliO_dataout, ~(n1OOOO));
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and(wire_n1ll0i_dataout, wire_n1llOi_dataout, ~(n011li));
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or(wire_n1ll0i_dataout, wire_n1llOi_dataout, n1OOOO);
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or(wire_n1ll0l_dataout, wire_n1llOl_dataout, n011li);
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and(wire_n1ll0l_dataout, wire_n1llOl_dataout, ~(n1OOOl));
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or(wire_n1ll0O_dataout, wire_n1llOO_dataout, n011li);
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assign wire_n1ll0O_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[0] : wire_n1llOO_dataout;
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or(wire_n1ll1i_dataout, wire_n1llli_dataout, n011li);
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or(wire_n1ll1i_dataout, wire_n1llli_dataout, n1OOOO);
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and(wire_n1ll1l_dataout, wire_n1llll_dataout, ~(n011li));
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or(wire_n1ll1l_dataout, wire_n1llll_dataout, n1OOOO);
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or(wire_n1ll1O_dataout, wire_n1lllO_dataout, n011li);
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and(wire_n1ll1O_dataout, wire_n1lllO_dataout, ~(n1OOOO));
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or(wire_n1lli_dataout, wire_n1lll_o[4], (~ nli0iil));
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assign wire_n1llii_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[1] : wire_n1lO1i_dataout;
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and(wire_n1llii_dataout, wire_n1lO1i_dataout, ~(n011li));
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assign wire_n1llil_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[2] : wire_n1lO1l_dataout;
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or(wire_n1llil_dataout, wire_n1lO1l_dataout, n011li);
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assign wire_n1lliO_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[3] : wire_n1lO1O_dataout;
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and(wire_n1lliO_dataout, wire_n1lO1O_dataout, ~(n011iO));
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assign wire_n1llli_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[4] : wire_n1lO0i_dataout;
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assign wire_n1llli_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[0] : wire_n1lO0i_dataout;
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assign wire_n1llll_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[5] : wire_n1lO0l_dataout;
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assign wire_n1llll_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[1] : wire_n1lO0l_dataout;
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assign wire_n1lllO_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[6] : wire_n1lO0O_dataout;
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assign wire_n1lllO_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[2] : wire_n1lO0O_dataout;
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assign wire_n1llOi_dataout = (n1OOOl === 1'b1) ? wire_n1i10l_dout[7] : wire_n1lOii_dataout;
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assign wire_n1llOi_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[3] : wire_n1lOii_dataout;
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and(wire_n1llOl_dataout, wire_n1lOil_dataout, ~(n1OOOi));
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assign wire_n1llOl_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[4] : wire_n1lOil_dataout;
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assign wire_n1llOO_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[8] : wire_n1lOiO_dataout;
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assign wire_n1llOO_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[5] : wire_n1lOiO_dataout;
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assign wire_n1lO0i_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[12] : wire_n1lOOi_dataout;
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assign wire_n1lO0i_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[8] : wire_n1lOOi_dataout;
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assign wire_n1lO0l_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[13] : wire_n1lOOl_dataout;
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assign wire_n1lO0l_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[9] : wire_n1lOOl_dataout;
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assign wire_n1lO0O_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[14] : wire_n1lOOO_dataout;
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assign wire_n1lO0O_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[10] : wire_n1lOOO_dataout;
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assign wire_n1lO1i_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[9] : wire_n1lOli_dataout;
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assign wire_n1lO1i_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[6] : wire_n1lOli_dataout;
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assign wire_n1lO1l_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[10] : wire_n1lOll_dataout;
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assign wire_n1lO1l_dataout = (n011iO === 1'b1) ? wire_n1i1iO_dout[7] : wire_n1lOll_dataout;
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assign wire_n1lO1O_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[11] : wire_n1lOlO_dataout;
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and(wire_n1lO1O_dataout, wire_n1lOlO_dataout, ~(n011il));
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assign wire_n1lOii_dataout = (n1OOOi === 1'b1) ? wire_n1i10l_dout[15] : wire_n1O11i_dataout;
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assign wire_n1lOii_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[11] : wire_n1O11i_dataout;
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or(wire_n1lOil_dataout, wire_n1O11l_dataout, wire_n1Oi0l_dataout);
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assign wire_n1lOil_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[12] : wire_n1O11l_dataout;
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and(wire_n1lOiO_dataout, wire_n1O11O_dataout, ~(wire_n1Oi0l_dataout));
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assign wire_n1lOiO_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[13] : wire_n1O11O_dataout;
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and(wire_n1lOli_dataout, wire_n1O10i_dataout, ~(wire_n1Oi0l_dataout));
|
assign wire_n1lOli_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[14] : wire_n1O10i_dataout;
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or(wire_n1lOll_dataout, wire_n1O10l_dataout, wire_n1Oi0l_dataout);
|
assign wire_n1lOll_dataout = (n011il === 1'b1) ? wire_n1i1iO_dout[15] : wire_n1O10l_dataout;
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or(wire_n1lOlO_dataout, wire_n1O10O_dataout, wire_n1Oi0l_dataout);
|
or(wire_n1lOlO_dataout, wire_n1O10O_dataout, wire_n1OiiO_dataout);
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or(wire_n1lOOi_dataout, wire_n1O1ii_dataout, wire_n1Oi0l_dataout);
|
and(wire_n1lOOi_dataout, wire_n1O1ii_dataout, ~(wire_n1OiiO_dataout));
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or(wire_n1lOOl_dataout, wire_n1O1il_dataout, wire_n1Oi0l_dataout);
|
and(wire_n1lOOl_dataout, wire_n1O1il_dataout, ~(wire_n1OiiO_dataout));
|
and(wire_n1lOOO_dataout, wire_n1O1iO_dataout, ~(wire_n1Oi0l_dataout));
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or(wire_n1lOOO_dataout, wire_n1O1iO_dataout, wire_n1OiiO_dataout);
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assign wire_n1O00i_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[7] : wire_n1O0Oi_dataout;
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assign wire_n1O00i_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[3] : wire_n1O0Oi_dataout;
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and(wire_n1O00l_dataout, wire_n1O0Ol_dataout, ~(n1OOiO));
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assign wire_n1O00l_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[4] : wire_n1O0Ol_dataout;
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and(wire_n1O00O_dataout, wire_n1i10l_dout[8], n1OOiO);
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assign wire_n1O00O_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[5] : wire_n1O0OO_dataout;
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assign wire_n1O01i_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[4] : wire_n1O0li_dataout;
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assign wire_n1O01i_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[0] : wire_n1O0li_dataout;
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assign wire_n1O01l_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[5] : wire_n1O0ll_dataout;
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assign wire_n1O01l_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[1] : wire_n1O0ll_dataout;
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assign wire_n1O01O_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[6] : wire_n1O0lO_dataout;
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assign wire_n1O01O_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[2] : wire_n1O0lO_dataout;
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and(wire_n1O0ii_dataout, wire_n1i10l_dout[9], n1OOiO);
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assign wire_n1O0ii_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[6] : wire_n1Oi1i_dataout;
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assign wire_n1O0il_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[10] : wire_n1Oi1i_dataout;
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assign wire_n1O0il_dataout = (n0110l === 1'b1) ? wire_n1i1iO_dout[7] : wire_n1Oi1l_dataout;
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assign wire_n1O0iO_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[11] : wire_n1O0Ol_dataout;
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and(wire_n1O0iO_dataout, wire_n1Oi1O_dataout, ~(n0110i));
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or(wire_n1O0l_dataout, wire_n1OiO_o[1], (~ nli00lO));
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and(wire_n1O0l_dataout, wire_n1Oil_dataout, ~(nli0iiO));
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or(wire_n1O0li_dataout, wire_n1i10l_dout[12], ~(n1OOiO));
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and(wire_n1O0li_dataout, wire_n1i1iO_dout[8], n0110i);
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assign wire_n1O0ll_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[13] : wire_n1O0Ol_dataout;
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and(wire_n1O0ll_dataout, wire_n1i1iO_dout[9], n0110i);
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assign wire_n1O0lO_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[14] : wire_n1O0OO_dataout;
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assign wire_n1O0lO_dataout = (n0110i === 1'b1) ? wire_n1i1iO_dout[10] : wire_n1Oi0l_dataout;
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or(wire_n1O0O_dataout, wire_n1OiO_o[2], (~ nli00lO));
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or(wire_n1O0O_dataout, wire_n1OiO_dataout, nli0iiO);
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assign wire_n1O0Oi_dataout = (n1OOiO === 1'b1) ? wire_n1i10l_dout[15] : wire_n1Oi1i_dataout;
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assign wire_n1O0Oi_dataout = (n0110i === 1'b1) ? wire_n1i1iO_dout[11] : wire_n1Oi1O_dataout;
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or(wire_n1O0Ol_dataout, (~ nli111i), nli111l);
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or(wire_n1O0Ol_dataout, wire_n1i1iO_dout[12], ~(n0110i));
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and(wire_n1O0OO_dataout, nli111i, ~(nli111l));
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assign wire_n1O0OO_dataout = (n0110i === 1'b1) ? wire_n1i1iO_dout[13] : wire_n1Oi1O_dataout;
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or(wire_n1O10i_dataout, wire_n1O1Oi_dataout, n1OOll);
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and(wire_n1O10i_dataout, wire_n1O1Oi_dataout, ~(wire_n1OiiO_dataout));
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and(wire_n1O10l_dataout, wire_n1O1Ol_dataout, ~(n1OOll));
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or(wire_n1O10l_dataout, wire_n1O1Ol_dataout, wire_n1OiiO_dataout);
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and(wire_n1O10O_dataout, wire_n1O1OO_dataout, ~(n1OOll));
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and(wire_n1O10O_dataout, wire_n1O1OO_dataout, ~(n0110O));
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or(wire_n1O11i_dataout, wire_n1O1li_dataout, wire_n1Oi0l_dataout);
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or(wire_n1O11i_dataout, wire_n1O1li_dataout, wire_n1OiiO_dataout);
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and(wire_n1O11l_dataout, wire_n1O1ll_dataout, ~(n1OOll));
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or(wire_n1O11l_dataout, wire_n1O1ll_dataout, wire_n1OiiO_dataout);
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and(wire_n1O11O_dataout, wire_n1O1lO_dataout, ~(n1OOll));
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or(wire_n1O11O_dataout, wire_n1O1lO_dataout, wire_n1OiiO_dataout);
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and(wire_n1O1ii_dataout, wire_n1O01i_dataout, ~(n1OOll));
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and(wire_n1O1ii_dataout, wire_n1O01i_dataout, ~(n0110O));
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and(wire_n1O1il_dataout, wire_n1O01l_dataout, ~(n1OOll));
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or(wire_n1O1il_dataout, wire_n1O01l_dataout, n0110O);
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or(wire_n1O1iO_dataout, wire_n1O01O_dataout, n1OOll);
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and(wire_n1O1iO_dataout, wire_n1O01O_dataout, ~(n0110O));
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and(wire_n1O1li_dataout, wire_n1O00i_dataout, ~(n1OOll));
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and(wire_n1O1li_dataout, wire_n1O00i_dataout, ~(n0110O));
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and(wire_n1O1ll_dataout, wire_n1O00l_dataout, ~(n1OOli));
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and(wire_n1O1ll_dataout, wire_n1O00l_dataout, ~(n0110O));
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assign wire_n1O1lO_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[0] : wire_n1O00O_dataout;
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and(wire_n1O1lO_dataout, wire_n1O00O_dataout, ~(n0110O));
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assign wire_n1O1Oi_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[1] : wire_n1O0ii_dataout;
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or(wire_n1O1Oi_dataout, wire_n1O0ii_dataout, n0110O);
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assign wire_n1O1Ol_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[2] : wire_n1O0il_dataout;
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and(wire_n1O1Ol_dataout, wire_n1O0il_dataout, ~(n0110O));
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assign wire_n1O1OO_dataout = (n1OOli === 1'b1) ? wire_n1i10l_dout[3] : wire_n1O0iO_dataout;
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and(wire_n1O1OO_dataout, wire_n1O0iO_dataout, ~(n0110l));
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and(wire_n1Oi0l_dataout, nli11iO, n1OOlO);
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and(wire_n1Oi0i_dataout, nli11Oi, ~(nli11Ol));
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or(wire_n1Oi1i_dataout, (~ nli111i), nli111l);
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or(wire_n1Oi0l_dataout, (~ nli11Oi), nli11Ol);
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or(wire_n1Oii_dataout, wire_n1OiO_o[3], (~ nli00lO));
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assign wire_n1Oi1i_dataout = (n0110i === 1'b1) ? wire_n1i1iO_dout[14] : wire_n1Oi0i_dataout;
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and(wire_n1Oiil_dataout, n1i1il, n0110i);
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assign wire_n1Oi1l_dataout = (n0110i === 1'b1) ? wire_n1i1iO_dout[15] : wire_n1Oi0l_dataout;
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or(wire_n1Oil_dataout, wire_n1OiO_o[4], (~ nli00lO));
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or(wire_n1Oi1O_dataout, (~ nli11Oi), nli11Ol);
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and(wire_n1Oili_dataout, nli11li, n0110O);
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or(wire_n1Oii_dataout, wire_n1Oli_dataout, nli0iiO);
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and(wire_n1Ol0i_dataout, nli11lO, ~(nli11iO));
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and(wire_n1OiiO_dataout, nli10ii, n011ii);
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and(wire_n1Ol0l_dataout, wire_n1Olii_dataout, ~(nli11iO));
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assign wire_n1Oil_dataout = (n1O0i === 1'b1) ? wire_n1Oll_o[1] : n1OlO;
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and(wire_n1Ol0O_dataout, nli11il, ~(nli11lO));
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and(wire_n1OilO_dataout, n1i1lO, n011Ol);
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and(wire_n1Ol1O_dataout, wire_n1Ol0O_dataout, ~(nli11iO));
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assign wire_n1OiO_dataout = (n1O0i === 1'b1) ? wire_n1Oll_o[2] : n1O1O;
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and(wire_n1Olii_dataout, (~ nli11il), ~(nli11lO));
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and(wire_n1OiOl_dataout, nli10il, n0101i);
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and(wire_n1Olll_dataout, wire_n1OlOl_dataout, ~(nli11Oi));
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and(wire_n1Oli_dataout, wire_n1Oll_o[3], n1O0i);
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and(wire_n1OllO_dataout, nli11lO, ~(nli11Oi));
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and(wire_n1Olii_dataout, wire_n1Olli_dataout, ~(nli10ii));
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and(wire_n1OlOi_dataout, wire_n1OlOO_dataout, ~(nli11Oi));
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and(wire_n1Olil_dataout, nli100l, ~(nli10ii));
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and(wire_n1OlOl_dataout, nli11ll, ~(nli11lO));
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and(wire_n1OliO_dataout, wire_n1Olll_dataout, ~(nli10ii));
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and(wire_n1OlOO_dataout, (~ nli11ll), ~(nli11lO));
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and(wire_n1Olli_dataout, nli10iO, ~(nli100l));
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and(wire_n1Olll_dataout, (~ nli10iO), ~(nli100l));
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and(wire_n1OlOi_dataout, wire_n1OO1i_dataout, ~(nli10ii));
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and(wire_n1OlOl_dataout, nli10ll, ~(nli10ii));
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and(wire_n1OlOO_dataout, wire_n1OO1l_dataout, ~(nli10ii));
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and(wire_n1OO0O_dataout, wire_n1OOiO_dataout, ~(nli10lO));
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and(wire_n1OO1i_dataout, nli100O, ~(nli10ll));
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and(wire_n1OO1l_dataout, (~ nli100O), ~(nli10ll));
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and(wire_n1OOii_dataout, nli10li, ~(nli10lO));
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and(wire_n1OOil_dataout, wire_n1OOli_dataout, ~(nli10lO));
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and(wire_n1OOiO_dataout, nli10iO, ~(nli10li));
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and(wire_n1OOli_dataout, (~ nli10iO), ~(nli10li));
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and(wire_ni01il_dataout, wire_ni01lO_o[0], wire_ni01Oi_o);
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and(wire_ni01il_dataout, wire_ni01lO_o[0], wire_ni01Oi_o);
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and(wire_ni01iO_dataout, wire_ni01lO_o[1], wire_ni01Oi_o);
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and(wire_ni01iO_dataout, wire_ni01lO_o[1], wire_ni01Oi_o);
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and(wire_ni01li_dataout, wire_ni01lO_o[2], wire_ni01Oi_o);
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and(wire_ni01li_dataout, wire_ni01lO_o[2], wire_ni01Oi_o);
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and(wire_ni01ll_dataout, wire_ni01lO_o[3], wire_ni01Oi_o);
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and(wire_ni01ll_dataout, wire_ni01lO_o[3], wire_ni01Oi_o);
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and(wire_ni0i0i_dataout, wire_ni0i0l_o[3], wire_ni0i0O_o);
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and(wire_ni0i0i_dataout, wire_ni0i0l_o[3], wire_ni0i0O_o);
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| Line 8436... |
Line 8586... |
and(wire_ni0ilO_dataout, wire_ni1O0i_q_b[5], ni0lli);
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and(wire_ni0ilO_dataout, wire_ni1O0i_q_b[5], ni0lli);
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and(wire_ni0iOi_dataout, wire_ni1O0i_q_b[6], ni0lli);
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and(wire_ni0iOi_dataout, wire_ni1O0i_q_b[6], ni0lli);
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and(wire_ni0iOl_dataout, wire_ni1O0i_q_b[7], ni0lli);
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and(wire_ni0iOl_dataout, wire_ni1O0i_q_b[7], ni0lli);
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and(wire_ni0iOO_dataout, wire_ni1O0i_q_b[8], ni0lli);
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and(wire_ni0iOO_dataout, wire_ni1O0i_q_b[8], ni0lli);
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and(wire_ni0l1i_dataout, wire_ni1O0i_q_b[9], ni0lli);
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and(wire_ni0l1i_dataout, wire_ni1O0i_q_b[9], ni0lli);
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and(wire_ni10il_dataout, nli1l1l, ~(nli1l1O));
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and(wire_ni10il_dataout, nli1i0l, ~(nli1i0O));
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and(wire_ni10iO_dataout, (~ nli1l1l), ~(nli1l1O));
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and(wire_ni10iO_dataout, (~ nli1i0l), ~(nli1i0O));
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and(wire_ni110i_dataout, ni1l0i, ni10Ol);
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and(wire_ni110i_dataout, ni1l0i, ni10Ol);
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and(wire_ni110l_dataout, ni1l0l, ni10Ol);
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and(wire_ni110l_dataout, ni1l0l, ni10Ol);
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and(wire_ni110O_dataout, ni1l0O, ni10Ol);
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and(wire_ni110O_dataout, ni1l0O, ni10Ol);
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assign wire_ni111i_dataout = (nli1iOi === 1'b1) ? ni1iil : wire_ni11iO_dataout;
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assign wire_ni111i_dataout = (nli1i1i === 1'b1) ? ni1iil : wire_ni11iO_dataout;
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assign wire_ni111l_dataout = (nli1iOi === 1'b1) ? ni1iiO : wire_ni11li_dataout;
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assign wire_ni111l_dataout = (nli1i1i === 1'b1) ? ni1iiO : wire_ni11li_dataout;
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assign wire_ni111O_dataout = (nli1iOi === 1'b1) ? ni1ili : wire_ni11ll_dataout;
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assign wire_ni111O_dataout = (nli1i1i === 1'b1) ? ni1ili : wire_ni11ll_dataout;
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and(wire_ni11ii_dataout, ni1lii, ni10Ol);
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and(wire_ni11ii_dataout, ni1lii, ni10Ol);
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and(wire_ni11il_dataout, ni1lil, ni10Ol);
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and(wire_ni11il_dataout, ni1lil, ni10Ol);
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and(wire_ni11iO_dataout, ni1liO, ni10Ol);
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and(wire_ni11iO_dataout, ni1liO, ni10Ol);
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and(wire_ni11li_dataout, ni1lli, ni10Ol);
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and(wire_ni11li_dataout, ni1lli, ni10Ol);
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and(wire_ni11ll_dataout, ni1lll, ni10Ol);
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and(wire_ni11ll_dataout, ni1lll, ni10Ol);
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and(wire_niii0i_dataout, nli1l0O, nli1lil);
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and(wire_niii0i_dataout, nli1iiO, nli1ill);
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or(wire_niii1i_dataout, niiilO, nil1OO);
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or(wire_niii1i_dataout, niiilO, nil1OO);
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assign wire_niii1O_dataout = (nli1lii === 1'b1) ? nli1l0l : wire_niii0i_dataout;
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assign wire_niii1O_dataout = (nli1ili === 1'b1) ? nli1iil : wire_niii0i_dataout;
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assign wire_niiiOi_dataout = (nli1lii === 1'b1) ? wire_niiO0O_dataout : wire_niil0l_dataout;
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assign wire_niiiOi_dataout = (nli1ili === 1'b1) ? wire_niiO0O_dataout : wire_niil0l_dataout;
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assign wire_niiiOl_dataout = (nli1lii === 1'b1) ? wire_niiOii_dataout : wire_niil0O_dataout;
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assign wire_niiiOl_dataout = (nli1ili === 1'b1) ? wire_niiOii_dataout : wire_niil0O_dataout;
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assign wire_niiiOO_dataout = (nli1lii === 1'b1) ? wire_niiOil_dataout : wire_niilii_dataout;
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assign wire_niiiOO_dataout = (nli1ili === 1'b1) ? wire_niiOil_dataout : wire_niilii_dataout;
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assign wire_niil0i_dataout = (nli1lii === 1'b1) ? wire_niiOlO_dataout : wire_niilll_dataout;
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assign wire_niil0i_dataout = (nli1ili === 1'b1) ? wire_niiOlO_dataout : wire_niilll_dataout;
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and(wire_niil0l_dataout, wire_niillO_dataout, nli1lil);
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and(wire_niil0l_dataout, wire_niillO_dataout, nli1ill);
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and(wire_niil0O_dataout, wire_niilOi_dataout, nli1lil);
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and(wire_niil0O_dataout, wire_niilOi_dataout, nli1ill);
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assign wire_niil1i_dataout = (nli1lii === 1'b1) ? wire_niiOiO_dataout : wire_niilil_dataout;
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assign wire_niil1i_dataout = (nli1ili === 1'b1) ? wire_niiOiO_dataout : wire_niilil_dataout;
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assign wire_niil1l_dataout = (nli1lii === 1'b1) ? wire_niiOli_dataout : wire_niiliO_dataout;
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assign wire_niil1l_dataout = (nli1ili === 1'b1) ? wire_niiOli_dataout : wire_niiliO_dataout;
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assign wire_niil1O_dataout = (nli1lii === 1'b1) ? wire_niiOll_dataout : wire_niilli_dataout;
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assign wire_niil1O_dataout = (nli1ili === 1'b1) ? wire_niiOll_dataout : wire_niilli_dataout;
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and(wire_niilii_dataout, wire_niilOl_dataout, nli1lil);
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and(wire_niilii_dataout, wire_niilOl_dataout, nli1ill);
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and(wire_niilil_dataout, wire_niilOO_dataout, nli1lil);
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and(wire_niilil_dataout, wire_niilOO_dataout, nli1ill);
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and(wire_niiliO_dataout, wire_niiO1i_dataout, nli1lil);
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and(wire_niiliO_dataout, wire_niiO1i_dataout, nli1ill);
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and(wire_niilli_dataout, wire_niiO1l_dataout, nli1lil);
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and(wire_niilli_dataout, wire_niiO1l_dataout, nli1ill);
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and(wire_niilll_dataout, wire_niiO1O_dataout, nli1lil);
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and(wire_niilll_dataout, wire_niiO1O_dataout, nli1ill);
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and(wire_niillO_dataout, wire_niiO0i_o[0], ~(wire_niiO0l_o));
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and(wire_niillO_dataout, wire_niiO0i_o[0], ~(wire_niiO0l_o));
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and(wire_niilOi_dataout, wire_niiO0i_o[1], ~(wire_niiO0l_o));
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and(wire_niilOi_dataout, wire_niiO0i_o[1], ~(wire_niiO0l_o));
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and(wire_niilOl_dataout, wire_niiO0i_o[2], ~(wire_niiO0l_o));
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and(wire_niilOl_dataout, wire_niiO0i_o[2], ~(wire_niiO0l_o));
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and(wire_niilOO_dataout, wire_niiO0i_o[3], ~(wire_niiO0l_o));
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and(wire_niilOO_dataout, wire_niiO0i_o[3], ~(wire_niiO0l_o));
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and(wire_niiO0O_dataout, wire_niiO0i_o[0], ~(nli1liO));
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and(wire_niiO0O_dataout, wire_niiO0i_o[0], ~(nli1ilO));
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and(wire_niiO1i_dataout, wire_niiO0i_o[4], ~(wire_niiO0l_o));
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and(wire_niiO1i_dataout, wire_niiO0i_o[4], ~(wire_niiO0l_o));
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and(wire_niiO1l_dataout, wire_niiO0i_o[5], ~(wire_niiO0l_o));
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and(wire_niiO1l_dataout, wire_niiO0i_o[5], ~(wire_niiO0l_o));
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and(wire_niiO1O_dataout, wire_niiO0i_o[6], ~(wire_niiO0l_o));
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and(wire_niiO1O_dataout, wire_niiO0i_o[6], ~(wire_niiO0l_o));
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and(wire_niiOii_dataout, wire_niiO0i_o[1], ~(nli1liO));
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and(wire_niiOii_dataout, wire_niiO0i_o[1], ~(nli1ilO));
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and(wire_niiOil_dataout, wire_niiO0i_o[2], ~(nli1liO));
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and(wire_niiOil_dataout, wire_niiO0i_o[2], ~(nli1ilO));
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and(wire_niiOiO_dataout, wire_niiO0i_o[3], ~(nli1liO));
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and(wire_niiOiO_dataout, wire_niiO0i_o[3], ~(nli1ilO));
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and(wire_niiOli_dataout, wire_niiO0i_o[4], ~(nli1liO));
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and(wire_niiOli_dataout, wire_niiO0i_o[4], ~(nli1ilO));
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and(wire_niiOll_dataout, wire_niiO0i_o[5], ~(nli1liO));
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and(wire_niiOll_dataout, wire_niiO0i_o[5], ~(nli1ilO));
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and(wire_niiOlO_dataout, wire_niiO0i_o[6], ~(nli1liO));
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and(wire_niiOlO_dataout, wire_niiO0i_o[6], ~(nli1ilO));
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and(wire_nil10l_dataout, nii0OO, ~(nli1lli));
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and(wire_nil10l_dataout, nii0OO, ~(nli1iOi));
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and(wire_nil10O_dataout, (~ nii0OO), ~(nli1lli));
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and(wire_nil10O_dataout, (~ nii0OO), ~(nli1iOi));
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and(wire_nil1iO_dataout, nli1llO, ~(nli1lOi));
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and(wire_nil1iO_dataout, nli1iOO, ~(nli1l1i));
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and(wire_nil1l_dataout, wire_nil1O_dataout, ~(((~ n0l1i) | (~ wire_nl1ii_syncstatus[0]))));
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and(wire_nil1li_dataout, (~ nli1iOO), ~(nli1l1i));
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and(wire_nil1li_dataout, (~ nli1llO), ~(nli1lOi));
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assign wire_nill0O_dataout = (nliil0l === 1'b1) ? wire_nilO1i_dataout : niliil;
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or(wire_nil1O_dataout, n0iil, (wire_nl1ii_syncstatus[0] & wire_nl1ii_rlv));
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assign wire_nillii_dataout = (nliil0l === 1'b1) ? wire_nilO1l_dataout : nilill;
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assign wire_nill0O_dataout = (nliilOi === 1'b1) ? wire_nilO1i_dataout : niliil;
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assign wire_nillil_dataout = (nliil0l === 1'b1) ? wire_nilO1O_dataout : nililO;
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assign wire_nillii_dataout = (nliilOi === 1'b1) ? wire_nilO1l_dataout : nilill;
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assign wire_nilliO_dataout = (nliil0l === 1'b1) ? wire_nilO0i_dataout : niliOi;
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assign wire_nillil_dataout = (nliilOi === 1'b1) ? wire_nilO1O_dataout : nililO;
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assign wire_nillli_dataout = (nliil0l === 1'b1) ? wire_nilO0l_dataout : niliOl;
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assign wire_nilliO_dataout = (nliilOi === 1'b1) ? wire_nilO0i_dataout : niliOi;
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assign wire_nillll_dataout = (nliil0l === 1'b1) ? wire_nilO0O_dataout : niliOO;
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assign wire_nillli_dataout = (nliilOi === 1'b1) ? wire_nilO0l_dataout : niliOl;
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assign wire_nilllO_dataout = (nliil0l === 1'b1) ? wire_nilOii_dataout : nill1i;
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assign wire_nillll_dataout = (nliilOi === 1'b1) ? wire_nilO0O_dataout : niliOO;
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assign wire_nillOi_dataout = (nliil0l === 1'b1) ? wire_nilOil_dataout : nill1l;
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assign wire_nilllO_dataout = (nliilOi === 1'b1) ? wire_nilOii_dataout : nill1i;
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assign wire_nillOl_dataout = (nliil0l === 1'b1) ? wire_nilOiO_dataout : nill1O;
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assign wire_nillOi_dataout = (nliilOi === 1'b1) ? wire_nilOil_dataout : nill1l;
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assign wire_nillOO_dataout = (nliil0l === 1'b1) ? wire_nilOli_dataout : nill0i;
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assign wire_nillOl_dataout = (nliilOi === 1'b1) ? wire_nilOiO_dataout : nill1O;
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assign wire_nilO0i_dataout = (nli1l0i === 1'b1) ? nilOOO : n0Olii;
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assign wire_nillOO_dataout = (nliilOi === 1'b1) ? wire_nilOli_dataout : nill0i;
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assign wire_nilO0l_dataout = (nli1l0i === 1'b1) ? niO11i : n0Olil;
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assign wire_nilO0i_dataout = (nli1O1i === 1'b1) ? nilOOO : n0Olii;
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assign wire_nilO0O_dataout = (nli1l0i === 1'b1) ? niO11l : n0OliO;
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assign wire_nilO0l_dataout = (nli1O1i === 1'b1) ? niO11i : n0Olil;
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assign wire_nilO1i_dataout = (nli1l0i === 1'b1) ? nill0l : n0Ol0i;
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assign wire_nilO0O_dataout = (nli1O1i === 1'b1) ? niO11l : n0OliO;
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assign wire_nilO1l_dataout = (nli1l0i === 1'b1) ? nilOOi : n0Ol0l;
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assign wire_nilO1i_dataout = (nli1O1i === 1'b1) ? nill0l : n0Ol0i;
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assign wire_nilO1O_dataout = (nli1l0i === 1'b1) ? nilOOl : n0Ol0O;
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assign wire_nilO1l_dataout = (nli1O1i === 1'b1) ? nilOOi : n0Ol0l;
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assign wire_nilOii_dataout = (nli1l0i === 1'b1) ? niO11O : n0Olli;
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assign wire_nilO1O_dataout = (nli1O1i === 1'b1) ? nilOOl : n0Ol0O;
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assign wire_nilOil_dataout = (nli1l0i === 1'b1) ? niO10i : n0Olll;
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assign wire_nilOii_dataout = (nli1O1i === 1'b1) ? niO11O : n0Olli;
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assign wire_nilOiO_dataout = (nli1l0i === 1'b1) ? niO10l : n0Ol1O;
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assign wire_nilOil_dataout = (nli1O1i === 1'b1) ? niO10i : n0Olll;
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assign wire_nilOli_dataout = (nli1l0i === 1'b1) ? niO10O : n0OO1l;
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assign wire_nilOiO_dataout = (nli1O1i === 1'b1) ? niO10l : n0Ol1O;
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assign wire_nilOli_dataout = (nli1O1i === 1'b1) ? niO10O : n0OO1l;
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assign wire_niO0ll_dataout = (wire_niO0lO_o[1] === 1'b1) ? (~ ((~ mii_tx_en) & (~ niOi1O))) : (mii_tx_en | niOi1O);
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assign wire_niO0ll_dataout = (wire_niO0lO_o[1] === 1'b1) ? (~ ((~ mii_tx_en) & (~ niOi1O))) : (mii_tx_en | niOi1O);
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assign wire_niO1iO_dataout = (nliilOi === 1'b1) ? wire_niO1li_dataout : niO1ii;
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assign wire_niO1iO_dataout = (nliil0l === 1'b1) ? wire_niO1li_dataout : niO1ii;
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or(wire_niO1li_dataout, (~ niO1ii), nli1O1i);
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and(wire_niO1l_dataout, wire_niO1O_dataout, ~(((~ n0O1i) | (~ wire_nl0ii_syncstatus[0]))));
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or(wire_niO1li_dataout, (~ niO1ii), nli1l0i);
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or(wire_niO1O_dataout, n0lil, ((wire_nl0ii_syncstatus[0] & wire_nl0ii_rlv) & (nlii1Ol22 ^ nlii1Ol21)));
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assign wire_niOi0l_dataout = (wire_niOi0O_o[1] === 1'b1) ? (~ ((~ nii00l) | (~ niOl1i))) : (niOill & (nii00l & niOl1i));
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assign wire_niOi0l_dataout = (wire_niOi0O_o[1] === 1'b1) ? (~ ((~ nii00l) | (~ niOl1i))) : (niOill & (nii00l & niOl1i));
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and(wire_niOi1i_dataout, wire_niO0ll_dataout, ~(niO0OO));
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and(wire_niOi1i_dataout, wire_niO0ll_dataout, ~(niO0OO));
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and(wire_niOilO_dataout, wire_niOi0l_dataout, ~(niOiOl));
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and(wire_niOilO_dataout, wire_niOi0l_dataout, ~(niOiOl));
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and(wire_nl000i_dataout, nl0i1i, ~((nl00OO & (~ nl00Ol))));
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and(wire_nl000i_dataout, nl0i1i, ~((nl00OO & (~ nl00Ol))));
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or(wire_nl00il_dataout, wire_nl00iO_dataout, nlliil);
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or(wire_nl00il_dataout, wire_nl00iO_dataout, nlliOO);
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and(wire_nl00iO_dataout, nl010l, ~((nli1O0O & nlO11l)));
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and(wire_nl00iO_dataout, nl010l, ~((nli1liO & nlO1iO)));
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and(wire_nl010O_dataout, wire_nl01iO_dataout, ~((~ nl00ll)));
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and(wire_nl010O_dataout, wire_nl01iO_dataout, ~((~ nl00ll)));
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and(wire_nl01ii_dataout, wire_nl01li_dataout, ~((~ nl00ll)));
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and(wire_nl01ii_dataout, wire_nl01li_dataout, ~((~ nl00ll)));
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or(wire_nl01il_dataout, wire_nl01ll_dataout, (~ nl00ll));
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or(wire_nl01il_dataout, wire_nl01ll_dataout, (~ nl00ll));
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assign wire_nl01iO_dataout = (nli1O0i === 1'b1) ? wire_nl000i_dataout : wire_nl01lO_dataout;
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assign wire_nl01iO_dataout = (nli1lii === 1'b1) ? wire_nl000i_dataout : wire_nl01lO_dataout;
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assign wire_nl01li_dataout = (nli1O0i === 1'b1) ? nl00Ol : wire_nl01Oi_dataout;
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assign wire_nl01li_dataout = (nli1lii === 1'b1) ? nl00Ol : wire_nl01Oi_dataout;
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assign wire_nl01ll_dataout = (nli1O0i === 1'b1) ? nl00OO : wire_nl01Ol_dataout;
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assign wire_nl01ll_dataout = (nli1lii === 1'b1) ? nl00OO : wire_nl01Ol_dataout;
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assign wire_nl01lO_dataout = (nli1O1O === 1'b1) ? wire_nl01OO_dataout : nl011l;
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assign wire_nl01lO_dataout = (nli1l0O === 1'b1) ? wire_nl01OO_dataout : nl011l;
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and(wire_nl01O_dataout, wire_nl11O_locked, ~(reset));
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assign wire_nl01Oi_dataout = (nli1l0O === 1'b1) ? nli0lO : nl011O;
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assign wire_nl01Oi_dataout = (nli1O1O === 1'b1) ? nli0lO : nl011O;
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assign wire_nl01Ol_dataout = (nli1l0O === 1'b1) ? nli0Oi : nl010i;
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assign wire_nl01Ol_dataout = (nli1O1O === 1'b1) ? nli0Oi : nl010i;
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and(wire_nl01OO_dataout, (~ nli0Ol), ~((nli0Oi & (~ nli0lO))));
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and(wire_nl01OO_dataout, (~ nli0Ol), ~((nli0Oi & (~ nli0lO))));
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and(wire_nl101i_dataout, wire_nl1i1l_o, nlO11l);
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and(wire_nl101i_dataout, wire_nl1i1l_o, nlO1iO);
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and(wire_nl101l_dataout, wire_nl1i1O_o, nlO11l);
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and(wire_nl101l_dataout, wire_nl1i1O_o, nlO1iO);
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and(wire_nl110i_dataout, wire_nl100l_o, nlO11l);
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and(wire_nl110i_dataout, wire_nl100l_o, nlO1iO);
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and(wire_nl110l_dataout, wire_nl100O_o, nlO11l);
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and(wire_nl110l_dataout, wire_nl100O_o, nlO1iO);
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and(wire_nl110O_dataout, wire_nl10ii_o, nlO11l);
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and(wire_nl110O_dataout, wire_nl10ii_o, nlO1iO);
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and(wire_nl111l_dataout, wire_nl101O_o, nlO11l);
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and(wire_nl111l_dataout, wire_nl101O_o, nlO1iO);
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and(wire_nl111O_dataout, wire_nl100i_o, nlO11l);
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and(wire_nl111O_dataout, wire_nl100i_o, nlO1iO);
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and(wire_nl11ii_dataout, wire_nl10il_o, nlO11l);
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and(wire_nl11ii_dataout, wire_nl10il_o, nlO1iO);
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and(wire_nl11il_dataout, wire_nl10iO_o, nlO11l);
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and(wire_nl11il_dataout, wire_nl10iO_o, nlO1iO);
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and(wire_nl11iO_dataout, wire_nl10li_o, nlO11l);
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and(wire_nl11iO_dataout, wire_nl10li_o, nlO1iO);
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and(wire_nl11li_dataout, wire_nl10ll_o, nlO11l);
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and(wire_nl11li_dataout, wire_nl10ll_o, nlO1iO);
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and(wire_nl11ll_dataout, wire_nl10lO_o, nlO11l);
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and(wire_nl11ll_dataout, wire_nl10lO_o, nlO1iO);
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and(wire_nl11lO_dataout, wire_nl10Oi_o, nlO11l);
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and(wire_nl11lO_dataout, wire_nl10Oi_o, nlO1iO);
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and(wire_nl11Oi_dataout, wire_nl10Ol_o, nlO11l);
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and(wire_nl11Oi_dataout, wire_nl10Ol_o, nlO1iO);
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and(wire_nl11Ol_dataout, wire_nl10OO_o, nlO11l);
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and(wire_nl11Ol_dataout, wire_nl10OO_o, nlO1iO);
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and(wire_nl11OO_dataout, wire_nl1i1i_o, nlO11l);
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and(wire_nl11OO_dataout, wire_nl1i1i_o, nlO1iO);
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and(wire_nl1lii_dataout, nli1OO, nli1O1l);
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and(wire_nl1lii_dataout, nli1OO, nli1l0l);
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and(wire_nl1lil_dataout, nli01O, nli1O1l);
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and(wire_nl1lil_dataout, nli01O, nli1l0l);
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and(wire_nl1liO_dataout, nli00i, nli1O1l);
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and(wire_nl1liO_dataout, nli00i, nli1l0l);
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and(wire_nl1lli_dataout, nli00l, nli1O1l);
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and(wire_nl1lli_dataout, nli00l, nli1l0l);
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and(wire_nl1lll_dataout, nli00O, nli1O1l);
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and(wire_nl1lll_dataout, nli00O, nli1l0l);
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and(wire_nl1llO_dataout, nli0ii, nli1O1l);
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and(wire_nl1llO_dataout, nli0ii, nli1l0l);
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and(wire_nl1lOi_dataout, nli0il, nli1O1l);
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and(wire_nl1lOi_dataout, nli0il, nli1l0l);
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and(wire_nl1lOl_dataout, nli0iO, nli1O1l);
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and(wire_nl1lOl_dataout, nli0iO, nli1l0l);
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and(wire_nl1lOO_dataout, nli0li, nli1O1l);
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and(wire_nl1lOO_dataout, nli0li, nli1l0l);
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and(wire_nl1O0i_dataout, nli0Ol, nli1O1l);
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and(wire_nl1O0i_dataout, nli0Ol, nli1l0l);
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and(wire_nl1O0l_dataout, nli0OO, nli1O1l);
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and(wire_nl1O0l_dataout, nli0OO, nli1l0l);
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and(wire_nl1O0O_dataout, nlii1i, nli1O1l);
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and(wire_nl1O0O_dataout, nlii1i, nli1l0l);
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and(wire_nl1O1i_dataout, nli0ll, nli1O1l);
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and(wire_nl1O1i_dataout, nli0ll, nli1l0l);
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and(wire_nl1O1l_dataout, nli0lO, nli1O1l);
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and(wire_nl1O1l_dataout, nli0lO, nli1l0l);
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and(wire_nl1O1O_dataout, nli0Oi, nli1O1l);
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and(wire_nl1O1O_dataout, nli0Oi, nli1l0l);
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and(wire_nl1Oii_dataout, nlii1O, nli1O1l);
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and(wire_nl1Oii_dataout, nlii1O, nli1l0l);
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or(wire_nli01i_dataout, wire_nli01l_dataout, nll01lO);
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or(wire_nli01i_dataout, wire_nli01l_dataout, nll010l);
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and(wire_nli01l_dataout, nli1Ol, ~(nli1lO));
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and(wire_nli01l_dataout, nli1Ol, ~(nli1lO));
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or(wire_nli1ii_dataout, wire_nli1il_dataout, nli10O);
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or(wire_nli1ii_dataout, wire_nli1il_dataout, nli10O);
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and(wire_nli1il_dataout, nli10l, ~((nll11l & (nli010i & (~ nlO11l)))));
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and(wire_nli1il_dataout, nli10l, ~((nll1iO & (nli1O0l & (~ nlO1iO)))));
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and(wire_nli1l_dataout, wire_nl01O_locked, ~(reset));
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and(wire_nlii0l_dataout, nlii0i, ~(nl00ll));
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and(wire_nlii0l_dataout, nlii0i, ~(nl00ll));
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and(wire_nlii0O_dataout, nliill, ~(nl00ll));
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and(wire_nlii0O_dataout, nliill, ~(nl00ll));
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and(wire_nliiii_dataout, nliilO, ~(nl00ll));
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and(wire_nliiii_dataout, nliilO, ~(nl00ll));
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and(wire_nliiil_dataout, nliiOl, ~(nl00ll));
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and(wire_nliiil_dataout, nliiOl, ~(nl00ll));
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and(wire_nliiiO_dataout, nliiOO, ~(nl00ll));
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and(wire_nliiiO_dataout, nliiOO, ~(nl00ll));
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or(wire_nliil1l_dataout, wire_nliil1O_dataout, nliiOlO);
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or(wire_nliil1O_dataout, (((~ nliiOlO) & (~ nliilOO)) & nl0O11O), (((~ nliiOlO) & nliilOO) & nl0O10i));
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and(wire_nliili_dataout, nlil1l, ~(nl00ll));
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and(wire_nliili_dataout, nlil1l, ~(nl00ll));
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or(wire_nliilli_dataout, wire_nliilll_dataout, nlil10l);
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and(wire_nliiO0i_dataout, wire_nliiOii_o[3], ~(nl0O11O));
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or(wire_nliilll_dataout, (((~ nlil10l) & (~ nliiOil)) & nl0O1OO), (((~ nlil10l) & nliiOil) & nl0O01i));
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and(wire_nliiO0l_dataout, wire_nliiOii_o[4], ~(nl0O11O));
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and(wire_nliiOiO_dataout, wire_nliiOOO_o[0], ~(nl0O1OO));
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and(wire_nliiO0O_dataout, wire_nliiOii_o[5], ~(nl0O11O));
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and(wire_nliiOli_dataout, wire_nliiOOO_o[1], ~(nl0O1OO));
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and(wire_nliiO1i_dataout, wire_nliiOii_o[0], ~(nl0O11O));
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and(wire_nliiOll_dataout, wire_nliiOOO_o[2], ~(nl0O1OO));
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and(wire_nliiO1l_dataout, wire_nliiOii_o[1], ~(nl0O11O));
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and(wire_nliiOlO_dataout, wire_nliiOOO_o[3], ~(nl0O1OO));
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and(wire_nliiO1O_dataout, wire_nliiOii_o[2], ~(nl0O11O));
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and(wire_nliiOOi_dataout, wire_nliiOOO_o[4], ~(nl0O1OO));
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and(wire_nliiOil_dataout, wire_nliiOll_o[0], ~(nl0O10i));
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and(wire_nliiOOl_dataout, wire_nliiOOO_o[5], ~(nl0O1OO));
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and(wire_nliiOiO_dataout, wire_nliiOll_o[1], ~(nl0O10i));
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and(wire_nlil0lO_dataout, wire_nlili1O_o[0], ~(nl0O01l));
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and(wire_nliiOli_dataout, wire_nliiOll_o[2], ~(nl0O10i));
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and(wire_nlil0Oi_dataout, wire_nlili1O_o[1], ~(nl0O01l));
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and(wire_nlil00i_dataout, wire_nlil0li_o[0], ~(nl0O10l));
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and(wire_nlil0Ol_dataout, wire_nlili1O_o[2], ~(nl0O01l));
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and(wire_nlil00l_dataout, wire_nlil0li_o[1], ~(nl0O10l));
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and(wire_nlil0OO_dataout, wire_nlili1O_o[3], ~(nl0O01l));
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and(wire_nlil00O_dataout, wire_nlil0li_o[2], ~(nl0O10l));
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and(wire_nlil11i_dataout, wire_nlil10i_o[0], ~(nl0O01i));
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and(wire_nlil0ii_dataout, wire_nlil0li_o[3], ~(nl0O10l));
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and(wire_nlil11l_dataout, wire_nlil10i_o[1], ~(nl0O01i));
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and(wire_nlil0il_dataout, wire_nlil0li_o[4], ~(nl0O10l));
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and(wire_nlil11O_dataout, wire_nlil10i_o[2], ~(nl0O01i));
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and(wire_nlil0iO_dataout, wire_nlil0li_o[5], ~(nl0O10l));
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or(wire_nlil1Oi_dataout, wire_nlil1Ol_dataout, nliliil);
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and(wire_nlil0ll_dataout, wire_nlil0Ol_o[0], ~(nl0O10O));
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or(wire_nlil1Ol_dataout, (((~ nliliil) & (~ nlil0ll)) & nl0O01l), (((~ nliliil) & nlil0ll) & nl0O01O));
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and(wire_nlil0lO_dataout, wire_nlil0Ol_o[1], ~(nl0O10O));
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and(wire_nlili0i_dataout, wire_nliliii_o[0], ~(nl0O01O));
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and(wire_nlil0Oi_dataout, wire_nlil0Ol_o[2], ~(nl0O10O));
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and(wire_nlili0l_dataout, wire_nliliii_o[1], ~(nl0O01O));
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or(wire_nlil10l_dataout, wire_nlil10O_dataout, nlil0OO);
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and(wire_nlili0O_dataout, wire_nliliii_o[2], ~(nl0O01O));
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or(wire_nlil10O_dataout, (((~ nlil0OO) & (~ nlil01O)) & nl0O10l), (((~ nlil0OO) & nlil01O) & nl0O10O));
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and(wire_nlili1i_dataout, wire_nlili1O_o[4], ~(nl0O01l));
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or(wire_nlilli_dataout, wire_nlilll_dataout, (nll1OO & (~ nlilii)));
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and(wire_nlili1l_dataout, wire_nlili1O_o[5], ~(nl0O01l));
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and(wire_nlilll_dataout, nlil0i, ~(((~ nll1OO) & nlil0i)));
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or(wire_nlilli_dataout, wire_nlilll_dataout, (nll1il & (~ nlilii)));
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and(wire_nlilOO_dataout, wire_nliO1i_dataout, ~((nll1iO & (nli1Oll & (~ nlO1iO)))));
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and(wire_nlilll_dataout, nlil0i, ~(((~ nll1il) & nlil0i)));
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or(wire_nliO1i_dataout, nlilii, (nll1OO & nlil0i));
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and(wire_nlilOO_dataout, wire_nliO1i_dataout, ~((nll11l & (nli01iO & (~ nlO11l)))));
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assign wire_nliOll_dataout = (nl00ll === 1'b1) ? wire_nliOlO_dataout : wire_nliOOO_dataout;
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or(wire_nliO1i_dataout, nlilii, (nll1il & nlil0i));
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and(wire_nliOlO_dataout, nliOiO, ((~ nll10l) & ((~ nl0i1i) & (~ nl00Oi))));
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and(wire_nliOO0O_dataout, wire_nliOOii_dataout, ~(wire_nlill1i_dout));
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and(wire_nliOlOl_dataout, wire_nliOlOO_dataout, ~(wire_nliliil_dout));
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or(wire_nliOOii_dataout, wire_nliOOil_dataout, wire_nlO0O0l_o);
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or(wire_nliOlOO_dataout, wire_nliOO1i_dataout, wire_nlO0O1i_o);
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and(wire_nliOOil_dataout, nll01lO, ~((wire_nlO0Oll_o | (wire_nlO0OOi_o | wire_nlO0OiO_o))));
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and(wire_nliOO0i_dataout, wire_nliliii_dout, ~(wire_nliliil_dout));
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and(wire_nliOOll_dataout, wire_nliliOO_dout, ~(wire_nlill1i_dout));
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and(wire_nliOO0O_dataout, wire_nliOOii_dataout, ~(wire_nliliil_dout));
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and(wire_nliOOOi_dataout, wire_nliOOOl_dataout, ~(wire_nlill1i_dout));
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and(wire_nliOO1i_dataout, nll010l, ~((wire_nlO0Oii_o | (wire_nlO0OiO_o | wire_nlO0O0l_o))));
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or(wire_nliOOOl_dataout, wire_nliOOOO_dataout, nil1i);
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or(wire_nliOOii_dataout, wire_nliOOil_dataout, niO1i);
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and(wire_nliOOOO_dataout, nliOO0l, ~(nl0O00i));
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and(wire_nliOOil_dataout, nliOlOi, ~(nl0O1ii));
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and(wire_nll000l_dataout, ((~ nl0O0lO) & nl0O00O), ~(wire_nlill1i_dout));
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and(wire_nliOOO_dataout, nliOiO, ~(nll10l));
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and(wire_nll001i_dataout, wire_nll001l_dataout, ~(wire_nlill1i_dout));
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and(wire_nll000i_dataout, wire_nll00ii_dataout, ~(wire_nliliil_dout));
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or(wire_nll001l_dataout, wire_nll001O_dataout, wire_nlO0Oii_o);
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and(wire_nll000l_dataout, wire_nll00il_dataout, ~(wire_nliliil_dout));
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and(wire_nll001O_dataout, nll01Oi, ~(wire_nlO0Oll_o));
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assign wire_nll000O_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[0] : wire_nll00iO_dataout;
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and(wire_nll00li_dataout, wire_nll00Oi_dataout, ~(wire_nlill1i_dout));
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and(wire_nll001O_dataout, wire_nll000O_dataout, ~(wire_nliliil_dout));
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and(wire_nll00ll_dataout, wire_nll00Ol_dataout, ~(wire_nlill1i_dout));
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assign wire_nll00ii_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[1] : wire_nll00li_dataout;
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and(wire_nll00lO_dataout, wire_nll00OO_dataout, ~(wire_nlill1i_dout));
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assign wire_nll00il_dataout = (nl0O1il === 1'b1) ? wire_nll00OO_o[2] : wire_nll00ll_dataout;
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assign wire_nll00Oi_dataout = (nl0O00l === 1'b1) ? wire_nll0iii_o[0] : wire_nll0i1i_dataout;
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and(wire_nll00iO_dataout, wire_nll00lO_dataout, ~((~ nlOl10i)));
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assign wire_nll00Ol_dataout = (nl0O00l === 1'b1) ? wire_nll0iii_o[1] : wire_nll0i1l_dataout;
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and(wire_nll00li_dataout, wire_nll00Oi_dataout, ~((~ nlOl10i)));
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assign wire_nll00OO_dataout = (nl0O00l === 1'b1) ? wire_nll0iii_o[2] : wire_nll0i1O_dataout;
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and(wire_nll00ll_dataout, wire_nll00Ol_dataout, ~((~ nlOl10i)));
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assign wire_nll010i_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[14] : nll11OO;
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and(wire_nll00lO_dataout, nll01lO, ~(nlOlOlO));
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assign wire_nll010l_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[15] : nll101i;
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and(wire_nll00Oi_dataout, nll01OO, ~(nlOlOlO));
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assign wire_nll010O_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[16] : nll101l;
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and(wire_nll00Ol_dataout, nll001i, ~(nlOlOlO));
|
assign wire_nll011i_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[11] : nll11lO;
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assign wire_nll011i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[18] : nll11lO;
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assign wire_nll011l_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[12] : nll11Oi;
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assign wire_nll011l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[19] : nll11Oi;
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assign wire_nll011O_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[13] : nll11Ol;
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assign wire_nll011O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[20] : nll11Ol;
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assign wire_nll01ii_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[17] : nll101O;
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and(wire_nll01ii_dataout, wire_nlO0llO_o, ~(wire_nliliil_dout));
|
assign wire_nll01il_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[18] : nll100i;
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and(wire_nll01iO_dataout, wire_nll01li_dataout, ~(wire_nliliil_dout));
|
assign wire_nll01iO_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[19] : nll100l;
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or(wire_nll01li_dataout, wire_nll01ll_dataout, wire_nlO0O1O_o);
|
assign wire_nll01li_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[20] : nll100O;
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and(wire_nll01ll_dataout, nll010O, ~(wire_nlO0Oii_o));
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and(wire_nll01Ol_dataout, wire_nlO0O1i_o, ~(wire_nlill1i_dout));
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and(wire_nll01Oi_dataout, ((~ nl0O1OO) & nl0O1iO), ~(wire_nliliil_dout));
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and(wire_nll0i0i_dataout, nll000i, ~(nlOO11i));
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and(wire_nll0i1O_dataout, (nll0i0l | wire_nliliiO_dout), ~(wire_nliliil_dout));
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and(wire_nll0i0l_dataout, nll00ii, ~(nlOO11i));
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and(wire_nll0iii_dataout, (nlOi1lO | nlOi1ll), ~(wire_nliliil_dout));
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and(wire_nll0i0O_dataout, nll00il, ~(nlOO11i));
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and(wire_nll0iil_dataout, (nlOi1ll | nlO101l), ~(wire_nliliil_dout));
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and(wire_nll0i1i_dataout, wire_nll0i0i_dataout, ~((~ nlOl1il)));
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and(wire_nll0llO_dataout, wire_nll0OOi_dataout, ~(wire_nliliil_dout));
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and(wire_nll0i1l_dataout, wire_nll0i0l_dataout, ~((~ nlOl1il)));
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and(wire_nll0lOi_dataout, wire_nll0OOl_dataout, ~(wire_nliliil_dout));
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and(wire_nll0i1O_dataout, wire_nll0i0O_dataout, ~((~ nlOl1il)));
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and(wire_nll0lOl_dataout, wire_nll0OOO_dataout, ~(wire_nliliil_dout));
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and(wire_nll0ill_dataout, (nlOi01i | nlOi1OO), ~(wire_nlill1i_dout));
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and(wire_nll0lOO_dataout, wire_nlli11i_dataout, ~(wire_nliliil_dout));
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and(wire_nll0ilO_dataout, (nlOi1OO | nlO100O), ~(wire_nlill1i_dout));
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and(wire_nll0O0i_dataout, wire_nlli10l_dataout, ~(wire_nliliil_dout));
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or(wire_nll0lO_dataout, nll0ii, nli001i);
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and(wire_nll0O0l_dataout, wire_nlli10O_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O0i_dataout, wire_nlli10l_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0O0O_dataout, wire_nlli1ii_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O0l_dataout, wire_nlli10O_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0O1i_dataout, wire_nlli11l_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O0O_dataout, wire_nlli1ii_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0O1l_dataout, wire_nlli11O_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O1i_dataout, wire_nlli11l_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0O1O_dataout, wire_nlli10i_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O1l_dataout, wire_nlli11O_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0Oii_dataout, wire_nlli1il_dataout, ~(wire_nliliil_dout));
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and(wire_nll0O1O_dataout, wire_nlli10i_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0Oil_dataout, wire_nlli1iO_dataout, ~(wire_nliliil_dout));
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and(wire_nll0Oii_dataout, wire_nlli1il_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0OiO_dataout, wire_nlli1li_dataout, ~(wire_nliliil_dout));
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and(wire_nll0Oil_dataout, wire_nlli1iO_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0Oli_dataout, wire_nlli1ll_dataout, ~(wire_nliliil_dout));
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and(wire_nll0OiO_dataout, wire_nlli1li_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0Oll_dataout, wire_nlli1lO_dataout, ~(wire_nliliil_dout));
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and(wire_nll0Oli_dataout, wire_nlli1ll_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0OlO_dataout, wire_nlli1Oi_dataout, ~(wire_nliliil_dout));
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and(wire_nll0Oll_dataout, wire_nlli1lO_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0OOi_dataout, wire_nlli1Ol_dataout, ~(nlOi01l));
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and(wire_nll0OlO_dataout, wire_nlli1Oi_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0OOl_dataout, wire_nlli1OO_dataout, ~(nlOi01l));
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and(wire_nll0OOi_dataout, wire_nlli1Ol_dataout, ~(wire_nlill1i_dout));
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and(wire_nll0OOO_dataout, wire_nlli01i_dataout, ~(nlOi01l));
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and(wire_nll0OOl_dataout, wire_nlli1OO_dataout, ~(wire_nlill1i_dout));
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and(wire_nll100i_dataout, wire_nll1ili_dataout, ~(wire_nliliil_dout));
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and(wire_nll0OOO_dataout, wire_nlli01i_dataout, ~(wire_nlill1i_dout));
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and(wire_nll100l_dataout, wire_nll1ill_dataout, ~(wire_nliliil_dout));
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assign wire_nll10i_dataout = (nli01lO === 1'b1) ? nlO01O : nliOil;
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and(wire_nll100O_dataout, wire_nll1ilO_dataout, ~(wire_nliliil_dout));
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and(wire_nll10il_dataout, wire_nll1iOl_dataout, ~(wire_nlill1i_dout));
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and(wire_nll101i_dataout, wire_nll1iii_dataout, ~(wire_nliliil_dout));
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and(wire_nll10iO_dataout, wire_nll1iOO_dataout, ~(wire_nlill1i_dout));
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and(wire_nll101l_dataout, wire_nll1iil_dataout, ~(wire_nliliil_dout));
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and(wire_nll10l_dataout, wire_nll10O_dataout, ~(nll11i));
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and(wire_nll101O_dataout, wire_nll1iiO_dataout, ~(wire_nliliil_dout));
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and(wire_nll10li_dataout, wire_nll1l1i_dataout, ~(wire_nlill1i_dout));
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and(wire_nll10ii_dataout, wire_nll1iOi_dataout, ~(wire_nliliil_dout));
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and(wire_nll10ll_dataout, wire_nll1l1l_dataout, ~(wire_nlill1i_dout));
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and(wire_nll10il_dataout, wire_nll1iOl_dataout, ~(wire_nliliil_dout));
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and(wire_nll10lO_dataout, wire_nll1l1O_dataout, ~(wire_nlill1i_dout));
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and(wire_nll10iO_dataout, wire_nll1iOO_dataout, ~(wire_nliliil_dout));
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assign wire_nll10O_dataout = (nli01lO === 1'b1) ? nlO0iO : nll11i;
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and(wire_nll10li_dataout, wire_nll1l1i_dataout, ~(wire_nliliil_dout));
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and(wire_nll10Oi_dataout, wire_nll1l0i_dataout, ~(wire_nlill1i_dout));
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and(wire_nll10ll_dataout, wire_nll1l1l_dataout, ~(wire_nliliil_dout));
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and(wire_nll10Ol_dataout, wire_nll1l0l_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll10lO_dataout, wire_nll1l1O_dataout, ~(wire_nliliil_dout));
|
and(wire_nll10OO_dataout, wire_nll1l0O_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll10Oi_dataout, wire_nll1l0i_dataout, ~(wire_nliliil_dout));
|
and(wire_nll11O_dataout, wire_nll10i_dataout, ~(nll10ii));
|
and(wire_nll10Ol_dataout, wire_nll1l0l_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i0i_dataout, wire_nll1lli_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll10OO_dataout, wire_nll1l0O_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i0l_dataout, wire_nll1lll_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i0i_dataout, wire_nll1lli_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i0O_dataout, wire_nll1llO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i0l_dataout, wire_nll1lll_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i1i_dataout, wire_nll1lii_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i0O_dataout, wire_nll1llO_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i1l_dataout, wire_nll1lil_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i1i_dataout, wire_nll1lii_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1i1O_dataout, wire_nll1liO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i1l_dataout, wire_nll1lil_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1iii_dataout, wire_nll1lOi_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1i1O_dataout, wire_nll1liO_dataout, ~(wire_nliliil_dout));
|
and(wire_nll1iil_dataout, wire_nll1lOl_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1iii_dataout, wire_nll1lOi_dataout, ~(niO1i));
|
and(wire_nll1iiO_dataout, wire_nll1lOO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1iil_dataout, wire_nll1lOl_dataout, ~(niO1i));
|
and(wire_nll1ili_dataout, wire_nll1O1i_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1iiO_dataout, wire_nll1lOO_dataout, ~(niO1i));
|
and(wire_nll1ill_dataout, wire_nll1O1l_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1ili_dataout, wire_nll1O1i_dataout, ~(niO1i));
|
and(wire_nll1ilO_dataout, wire_nll1O1O_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1ill_dataout, wire_nll1O1l_dataout, ~(niO1i));
|
and(wire_nll1iOi_dataout, wire_nll1O0i_dataout, ~(wire_nlill1i_dout));
|
and(wire_nll1ilO_dataout, wire_nll1O1O_dataout, ~(niO1i));
|
and(wire_nll1iOl_dataout, wire_nll1O0l_dataout, ~(nil1i));
|
and(wire_nll1iOi_dataout, wire_nll1O0i_dataout, ~(niO1i));
|
and(wire_nll1iOO_dataout, wire_nll1O0O_dataout, ~(nil1i));
|
and(wire_nll1iOl_dataout, wire_nll1O0l_dataout, ~(niO1i));
|
and(wire_nll1l0i_dataout, wire_nll1Oli_dataout, ~(nil1i));
|
and(wire_nll1iOO_dataout, wire_nll1O0O_dataout, ~(niO1i));
|
and(wire_nll1l0l_dataout, wire_nll1Oll_dataout, ~(nil1i));
|
and(wire_nll1l0i_dataout, wire_nll1Oli_dataout, ~(niO1i));
|
and(wire_nll1l0O_dataout, wire_nll1OlO_dataout, ~(nil1i));
|
and(wire_nll1l0l_dataout, wire_nll1Oll_dataout, ~(niO1i));
|
and(wire_nll1l1i_dataout, wire_nll1Oii_dataout, ~(nil1i));
|
and(wire_nll1l0O_dataout, wire_nll1OlO_dataout, ~(niO1i));
|
and(wire_nll1l1l_dataout, wire_nll1Oil_dataout, ~(nil1i));
|
and(wire_nll1l1i_dataout, wire_nll1Oii_dataout, ~(niO1i));
|
and(wire_nll1l1O_dataout, wire_nll1OiO_dataout, ~(nil1i));
|
and(wire_nll1l1l_dataout, wire_nll1Oil_dataout, ~(niO1i));
|
and(wire_nll1lii_dataout, wire_nll1OOi_dataout, ~(nil1i));
|
and(wire_nll1l1O_dataout, wire_nll1OiO_dataout, ~(niO1i));
|
and(wire_nll1lil_dataout, wire_nll1OOl_dataout, ~(nil1i));
|
and(wire_nll1li_dataout, wire_nll1ll_dataout, ~(nll11OO));
|
and(wire_nll1liO_dataout, wire_nll1OOO_dataout, ~(nil1i));
|
and(wire_nll1lii_dataout, wire_nll1OOi_dataout, ~(niO1i));
|
and(wire_nll1lli_dataout, wire_nll011i_dataout, ~(nil1i));
|
and(wire_nll1lil_dataout, wire_nll1OOl_dataout, ~(niO1i));
|
and(wire_nll1lll_dataout, wire_nll011l_dataout, ~(nil1i));
|
and(wire_nll1liO_dataout, wire_nll1OOO_dataout, ~(niO1i));
|
and(wire_nll1llO_dataout, wire_nll011O_dataout, ~(nil1i));
|
assign wire_nll1ll_dataout = (nli1OOO === 1'b1) ? nlO0li : nll11i;
|
and(wire_nll1lOi_dataout, wire_nll010i_dataout, ~(nil1i));
|
and(wire_nll1lli_dataout, wire_nll011i_dataout, ~(niO1i));
|
and(wire_nll1lOl_dataout, wire_nll010l_dataout, ~(nil1i));
|
and(wire_nll1lll_dataout, wire_nll011l_dataout, ~(niO1i));
|
and(wire_nll1lOO_dataout, wire_nll010O_dataout, ~(nil1i));
|
and(wire_nll1llO_dataout, wire_nll011O_dataout, ~(niO1i));
|
and(wire_nll1O0i_dataout, wire_nll01li_dataout, ~(nil1i));
|
and(wire_nll1lO_dataout, wire_nll1Oi_dataout, ~(nll1il));
|
assign wire_nll1O0l_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[0] : nliOOlO;
|
assign wire_nll1lOi_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[0] : nliOO0l;
|
assign wire_nll1O0O_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[1] : nll111l;
|
assign wire_nll1lOl_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[1] : nliOOli;
|
and(wire_nll1O1i_dataout, wire_nll01ii_dataout, ~(nil1i));
|
assign wire_nll1lOO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[2] : nliOOll;
|
and(wire_nll1O1l_dataout, wire_nll01il_dataout, ~(nil1i));
|
assign wire_nll1O0i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[6] : nliOOOO;
|
and(wire_nll1O1O_dataout, wire_nll01iO_dataout, ~(nil1i));
|
assign wire_nll1O0l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[7] : nll111i;
|
assign wire_nll1Oii_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[2] : nll111O;
|
assign wire_nll1O0O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[8] : nll111l;
|
assign wire_nll1Oil_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[3] : nll110i;
|
assign wire_nll1O1i_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[3] : nliOOlO;
|
assign wire_nll1OiO_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[4] : nll110l;
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assign wire_nll1O1l_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[4] : nliOOOi;
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assign wire_nll1Oli_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[5] : nll110O;
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assign wire_nll1O1O_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[5] : nliOOOl;
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assign wire_nll1Oll_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[6] : nll11ii;
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assign wire_nll1Oi_dataout = (nli1OOO === 1'b1) ? nlOi1i : nll1il;
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assign wire_nll1OlO_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[7] : nll11il;
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assign wire_nll1Oii_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[9] : nll111O;
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assign wire_nll1OOi_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[8] : nll11iO;
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assign wire_nll1Oil_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[10] : nll110i;
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assign wire_nll1OOl_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[9] : nll11li;
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assign wire_nll1OiO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[11] : nll110l;
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assign wire_nll1OOO_dataout = (nliOO0l === 1'b1) ? wire_nll01ll_o[10] : nll11ll;
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assign wire_nll1Oli_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[12] : nll110O;
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and(wire_nlli00i_dataout, wire_nllii0l_dataout, ~(wire_nlO0OiO_o));
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assign wire_nll1Oll_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[13] : nll11ii;
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and(wire_nlli00l_dataout, wire_nllii0O_dataout, ~(wire_nlO0OiO_o));
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assign wire_nll1OlO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[14] : nll11il;
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and(wire_nlli00O_dataout, wire_nlliiii_dataout, ~(wire_nlO0OiO_o));
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assign wire_nll1OOi_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[15] : nll11iO;
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and(wire_nlli01i_dataout, wire_nllii1l_dataout, ~(nlOi00O));
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assign wire_nll1OOl_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[16] : nll11li;
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and(wire_nlli01l_dataout, wire_nllii1O_dataout, ~(nlOi00O));
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assign wire_nll1OOO_dataout = (nliOlOi === 1'b1) ? wire_nll010i_o[17] : nll11ll;
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assign wire_nlli01O_dataout = (wire_nlO0OiO_o === 1'b1) ? nl00ll : wire_nllii0i_dataout;
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assign wire_nlli00i_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nlii0l_dataout : wire_nllii0l_dataout;
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and(wire_nlli0ii_dataout, wire_nlliiil_dataout, ~(wire_nlO0OiO_o));
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assign wire_nlli00l_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nlii0O_dataout : wire_nllii0O_dataout;
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assign wire_nlli0il_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nlii0l_dataout : wire_nlliiiO_dataout;
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assign wire_nlli00O_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiii_dataout : wire_nlliiii_dataout;
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assign wire_nlli0iO_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nlii0O_dataout : wire_nlliili_dataout;
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and(wire_nlli01i_dataout, wire_nllii1l_dataout, ~(wire_nlO0O0l_o));
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assign wire_nlli0li_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nliiii_dataout : wire_nlliill_dataout;
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and(wire_nlli01l_dataout, wire_nllii1O_dataout, ~(wire_nlO0O0l_o));
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assign wire_nlli0ll_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nliiil_dataout : wire_nlliilO_dataout;
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and(wire_nlli01O_dataout, wire_nllii0i_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlli0lO_dataout, wire_nlliiOi_dataout, ~(wire_nlO0OiO_o));
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or(wire_nlli0i_dataout, nll0Ol, nli010O);
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and(wire_nlli0Oi_dataout, wire_nlliiOl_dataout, ~(wire_nlO0OiO_o));
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assign wire_nlli0ii_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiil_dataout : wire_nlliiil_dataout;
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and(wire_nlli0Ol_dataout, wire_nlliiOO_dataout, ~(wire_nlO0OiO_o));
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and(wire_nlli0il_dataout, wire_nlliiiO_dataout, ~(wire_nlO0O0l_o));
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assign wire_nlli0OO_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nliiiO_dataout : wire_nllil1i_dataout;
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and(wire_nlli0iO_dataout, wire_nlliili_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlli10i_dataout, wire_nlli00l_dataout, ~(nlOi00O));
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and(wire_nlli0li_dataout, wire_nlliill_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlli10l_dataout, wire_nlli00O_dataout, ~(nlOi00O));
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assign wire_nlli0ll_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliiiO_dataout : wire_nlliilO_dataout;
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and(wire_nlli10O_dataout, wire_nlli0ii_dataout, ~(nlOi00O));
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assign wire_nlli0lO_dataout = (wire_nlO0O0l_o === 1'b1) ? wire_nliili_dataout : wire_nlliiOi_dataout;
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and(wire_nlli11i_dataout, wire_nlli01l_dataout, ~(wire_nlill1i_dout));
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and(wire_nlli0Oi_dataout, wire_nlliiOl_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlli11l_dataout, wire_nlli01O_dataout, ~(nlOi00O));
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and(wire_nlli0Ol_dataout, wire_nlliiOO_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlli11O_dataout, wire_nlli00i_dataout, ~(nlOi00O));
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assign wire_nlli0OO_dataout = (wire_nlO0O1O_o === 1'b1) ? nl00ll : nll0i0O;
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and(wire_nlli1ii_dataout, wire_nlli0il_dataout, ~(nlOi00O));
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and(wire_nlli10i_dataout, wire_nlli00l_dataout, ~(nlOi01l));
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and(wire_nlli1il_dataout, wire_nlli0iO_dataout, ~(nlOi00O));
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and(wire_nlli10l_dataout, wire_nlli00O_dataout, ~(nlOi01l));
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and(wire_nlli1iO_dataout, wire_nlli0li_dataout, ~(nlOi00O));
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and(wire_nlli10O_dataout, wire_nlli0ii_dataout, ~(nlOi01l));
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and(wire_nlli1li_dataout, wire_nlli0ll_dataout, ~(nlOi00O));
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and(wire_nlli11i_dataout, wire_nlli01l_dataout, ~(nlOi01l));
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and(wire_nlli1ll_dataout, wire_nlli0lO_dataout, ~(nlOi00O));
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and(wire_nlli11l_dataout, wire_nlli01O_dataout, ~(nlOi01l));
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and(wire_nlli1lO_dataout, wire_nlli0Oi_dataout, ~(nlOi00O));
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and(wire_nlli11O_dataout, wire_nlli00i_dataout, ~(nlOi01l));
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and(wire_nlli1Oi_dataout, wire_nlli0Ol_dataout, ~(nlOi00O));
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and(wire_nlli1ii_dataout, wire_nlli0il_dataout, ~(nlOi01l));
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and(wire_nlli1Ol_dataout, wire_nlli0OO_dataout, ~(nlOi00O));
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and(wire_nlli1il_dataout, wire_nlli0iO_dataout, ~(nlOi01l));
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and(wire_nlli1OO_dataout, wire_nllii1i_dataout, ~(nlOi00O));
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and(wire_nlli1iO_dataout, wire_nlli0li_dataout, ~(nlOi01l));
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assign wire_nllii0i_dataout = (wire_nlO0Oii_o === 1'b1) ? nl00ll : nll0ili;
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and(wire_nlli1li_dataout, wire_nlli0ll_dataout, ~(nlOi01l));
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and(wire_nllii0l_dataout, nll0iOO, ~(wire_nlO0Oii_o));
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and(wire_nlli1ll_dataout, wire_nlli0lO_dataout, ~(nlOi01l));
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and(wire_nllii0O_dataout, nll0l1i, ~(wire_nlO0Oii_o));
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and(wire_nlli1lO_dataout, wire_nlli0Oi_dataout, ~(nlOi01l));
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assign wire_nllii1i_dataout = (wire_nlO0OiO_o === 1'b1) ? wire_nliili_dataout : wire_nllil1l_dataout;
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and(wire_nlli1Oi_dataout, wire_nlli0Ol_dataout, ~(nlOi01l));
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and(wire_nllii1l_dataout, wire_nllil1O_dataout, ~(wire_nlO0OiO_o));
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assign wire_nlli1Ol_dataout = (wire_nlO0O0l_o === 1'b1) ? nl00ll : wire_nlli0OO_dataout;
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and(wire_nllii1O_dataout, wire_nllil0i_dataout, ~(wire_nlO0OiO_o));
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and(wire_nlli1OO_dataout, wire_nllii1i_dataout, ~(wire_nlO0O0l_o));
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and(wire_nlliiii_dataout, nll0l1l, ~(wire_nlO0Oii_o));
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and(wire_nllii0i_dataout, nll0iOl, ~(wire_nlO0O1O_o));
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and(wire_nlliiil_dataout, nll0l1O, ~(wire_nlO0Oii_o));
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assign wire_nllii0l_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nlii0l_dataout : nll0iOO;
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assign wire_nlliiiO_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nlii0l_dataout : nll0l0i;
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assign wire_nllii0O_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nlii0O_dataout : nll0l1i;
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assign wire_nlliili_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nlii0O_dataout : nll0l0l;
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and(wire_nllii1i_dataout, nll0ill, ~(wire_nlO0O1O_o));
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assign wire_nlliill_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nliiii_dataout : nll0l0O;
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and(wire_nllii1l_dataout, nll0ilO, ~(wire_nlO0O1O_o));
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assign wire_nlliilO_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nliiil_dataout : nll0lii;
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and(wire_nllii1O_dataout, nll0iOi, ~(wire_nlO0O1O_o));
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or(wire_nlliiO_dataout, nlli0i, nli001i);
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assign wire_nlliiii_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiii_dataout : nll0l1l;
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and(wire_nlliiOi_dataout, nll0lil, ~(wire_nlO0Oii_o));
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assign wire_nlliiil_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiil_dataout : nll0l1O;
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and(wire_nlliiOl_dataout, nll0liO, ~(wire_nlO0Oii_o));
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and(wire_nlliiiO_dataout, nll0l0i, ~(wire_nlO0O1O_o));
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and(wire_nlliiOO_dataout, nll0lli, ~(wire_nlO0Oii_o));
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and(wire_nlliili_dataout, nll0l0l, ~(wire_nlO0O1O_o));
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and(wire_nllil0i_dataout, nll0lOl, ~(wire_nlO0Oii_o));
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and(wire_nlliill_dataout, nll0l0O, ~(wire_nlO0O1O_o));
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and(wire_nllil0O_dataout, wire_nllilii_dataout, ~(wire_nlill1i_dout));
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assign wire_nlliilO_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliiiO_dataout : nll0lii;
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assign wire_nllil1i_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nliiiO_dataout : nll0lll;
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assign wire_nlliiOi_dataout = (wire_nlO0O1O_o === 1'b1) ? wire_nliili_dataout : nll0lil;
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assign wire_nllil1l_dataout = (wire_nlO0Oii_o === 1'b1) ? wire_nliili_dataout : nll0llO;
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or(wire_nlliiOl_dataout, nll0liO, wire_nlO0O1O_o);
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or(wire_nllil1O_dataout, nll0lOi, wire_nlO0Oii_o);
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and(wire_nlliiOO_dataout, nll0lli, ~(wire_nlO0O1O_o));
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and(wire_nllilii_dataout, nl0O0ii, ~((nlOi00O | nl0O0li)));
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and(wire_nllil1l_dataout, wire_nllil1O_dataout, ~(wire_nliliil_dout));
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and(wire_nlliOOO_dataout, wire_nlll00O_dataout, ~(wire_nlill1i_dout));
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and(wire_nllil1O_dataout, nl0O1li, ~((nlOi01l | nl0O1Oi)));
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and(wire_nlll00i_dataout, wire_nlllili_dataout, ~(wire_nlill1i_dout));
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and(wire_nlliOll_dataout, wire_nlll01l_dataout, ~(wire_nliliil_dout));
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and(wire_nlll00l_dataout, wire_nlllill_dataout, ~(wire_nlill1i_dout));
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and(wire_nlliOlO_dataout, wire_nlll01O_dataout, ~(wire_nliliil_dout));
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and(wire_nlll00O_dataout, wire_nlllilO_dataout, ~(nl0O0iO));
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and(wire_nlliOOi_dataout, wire_nlll00i_dataout, ~(wire_nliliil_dout));
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and(wire_nlll01i_dataout, wire_nllliii_dataout, ~(wire_nlill1i_dout));
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and(wire_nlliOOl_dataout, wire_nlll00l_dataout, ~(wire_nliliil_dout));
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and(wire_nlll01l_dataout, wire_nllliil_dataout, ~(wire_nlill1i_dout));
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and(wire_nlliOOO_dataout, wire_nlll00O_dataout, ~(wire_nliliil_dout));
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and(wire_nlll01O_dataout, wire_nllliiO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll00i_dataout, wire_nlllili_dataout, ~(nl0O1lO));
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and(wire_nlll0ii_dataout, wire_nllliOi_dataout, ~(nl0O0iO));
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and(wire_nlll00l_dataout, wire_nlllill_dataout, ~(nl0O1lO));
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and(wire_nlll0il_dataout, wire_nllliOl_dataout, ~(nl0O0iO));
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and(wire_nlll00O_dataout, wire_nlllilO_dataout, ~(nl0O1lO));
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and(wire_nlll0iO_dataout, wire_nllliOO_dataout, ~(nl0O0iO));
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and(wire_nlll01i_dataout, wire_nllliii_dataout, ~(wire_nliliil_dout));
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and(wire_nlll0li_dataout, wire_nllll1i_dataout, ~(nl0O0iO));
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and(wire_nlll01l_dataout, wire_nllliil_dataout, ~(nl0O1lO));
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and(wire_nlll0ll_dataout, wire_nllll1l_dataout, ~(nl0O0iO));
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and(wire_nlll01O_dataout, wire_nllliiO_dataout, ~(nl0O1lO));
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and(wire_nlll0lO_dataout, wire_nllll1O_dataout, ~(nl0O0iO));
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and(wire_nlll0ii_dataout, wire_nllliOi_dataout, ~(nl0O1lO));
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and(wire_nlll0O_dataout, wire_nlllOl_o[0], nli001l);
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and(wire_nlll0il_dataout, wire_nllliOl_dataout, ~(nl0O1lO));
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and(wire_nlll0Oi_dataout, wire_nllll0i_dataout, ~(nl0O0iO));
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and(wire_nlll0iO_dataout, wire_nllliOO_dataout, ~(nl0O1lO));
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and(wire_nlll0Ol_dataout, wire_nllll0l_dataout, ~(nl0O0iO));
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and(wire_nlll0li_dataout, wire_nllll1i_dataout, ~(nl0O1lO));
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and(wire_nlll0OO_dataout, wire_nllll0O_dataout, ~(nl0O0iO));
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and(wire_nlll0ll_dataout, wire_nllll1l_dataout, ~(nl0O1lO));
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and(wire_nlll10i_dataout, wire_nlll0li_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll0lO_dataout, wire_nllll1O_dataout, ~(nl0O1lO));
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and(wire_nlll10l_dataout, wire_nlll0ll_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll0Oi_dataout, wire_nllll0i_dataout, ~(nl0O1lO));
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and(wire_nlll10O_dataout, wire_nlll0lO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll0Ol_dataout, wire_nllll0l_dataout, ~(nl0O1lO));
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and(wire_nlll11i_dataout, wire_nlll0ii_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll0OO_dataout, wire_nllll0O_dataout, ~(nl0O1lO));
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and(wire_nlll11l_dataout, wire_nlll0il_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll10i_dataout, wire_nlll0li_dataout, ~(wire_nliliil_dout));
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and(wire_nlll11O_dataout, wire_nlll0iO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll10l_dataout, wire_nlll0ll_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1ii_dataout, wire_nlll0Oi_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll10O_dataout, wire_nlll0lO_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1il_dataout, wire_nlll0Ol_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll11i_dataout, wire_nlll0ii_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1iO_dataout, wire_nlll0OO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll11l_dataout, wire_nlll0il_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1li_dataout, wire_nllli1i_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll11O_dataout, wire_nlll0iO_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1ll_dataout, wire_nllli1l_dataout, ~(wire_nlill1i_dout));
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or(wire_nlll1i_dataout, nllill, nli010O);
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and(wire_nlll1lO_dataout, wire_nllli1O_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll1ii_dataout, wire_nlll0Oi_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1Oi_dataout, wire_nllli0i_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll1il_dataout, wire_nlll0Ol_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1Ol_dataout, wire_nllli0l_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll1iO_dataout, wire_nlll0OO_dataout, ~(wire_nliliil_dout));
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and(wire_nlll1OO_dataout, wire_nllli0O_dataout, ~(wire_nlill1i_dout));
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and(wire_nlll1li_dataout, wire_nllli1i_dataout, ~(wire_nliliil_dout));
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and(wire_nllli0i_dataout, wire_nllllli_dataout, ~(nl0O0iO));
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and(wire_nlll1ll_dataout, wire_nllli1l_dataout, ~(wire_nliliil_dout));
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and(wire_nllli0l_dataout, wire_nllllll_dataout, ~(nl0O0iO));
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and(wire_nlll1lO_dataout, wire_nllli1O_dataout, ~(wire_nliliil_dout));
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and(wire_nllli0O_dataout, wire_nlllllO_dataout, ~(nl0O0iO));
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and(wire_nlll1Oi_dataout, wire_nllli0i_dataout, ~(wire_nliliil_dout));
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and(wire_nllli1i_dataout, wire_nllllii_dataout, ~(nl0O0iO));
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and(wire_nlll1Ol_dataout, wire_nllli0l_dataout, ~(wire_nliliil_dout));
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and(wire_nllli1l_dataout, wire_nllllil_dataout, ~(nl0O0iO));
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and(wire_nlll1OO_dataout, wire_nllli0O_dataout, ~(wire_nliliil_dout));
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and(wire_nllli1O_dataout, wire_nlllliO_dataout, ~(nl0O0iO));
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and(wire_nllli0i_dataout, wire_nllllli_dataout, ~(nl0O1lO));
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and(wire_nlllii_dataout, wire_nlllOl_o[1], nli001l);
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and(wire_nllli0l_dataout, wire_nllllll_dataout, ~(nl0O1lO));
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and(wire_nllliii_dataout, wire_nllllOi_dataout, ~(nl0O0iO));
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and(wire_nllli0O_dataout, wire_nlllllO_dataout, ~(nl0O1lO));
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and(wire_nllliil_dataout, wire_nllllOl_dataout, ~(nl0O0iO));
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and(wire_nllli1i_dataout, wire_nllllii_dataout, ~(nl0O1lO));
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and(wire_nllliiO_dataout, wire_nllllOO_dataout, ~(nl0O0iO));
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and(wire_nllli1l_dataout, wire_nllllil_dataout, ~(nl0O1lO));
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and(wire_nlllil_dataout, wire_nlllOl_o[2], nli001l);
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and(wire_nllli1O_dataout, wire_nlllliO_dataout, ~(nl0O1lO));
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and(wire_nlllili_dataout, wire_nlllO1i_dataout, ~(nl0O0iO));
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and(wire_nllliii_dataout, wire_nllllOi_dataout, ~(nl0O1lO));
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and(wire_nlllill_dataout, wire_nlllO1l_dataout, ~(nl0O0iO));
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assign wire_nllliil_dataout = (nl0O1ll === 1'b1) ? wire_nllllOl_dataout : nllil1i;
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assign wire_nlllilO_dataout = (nl0O0il === 1'b1) ? wire_nlllO1O_dataout : nllil0l;
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assign wire_nllliiO_dataout = (nl0O1ll === 1'b1) ? wire_nllllOO_dataout : nllil0l;
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and(wire_nllliO_dataout, wire_nlllOl_o[3], nli001l);
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assign wire_nlllili_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1i_dataout : nllil0O;
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assign wire_nllliOi_dataout = (nl0O0il === 1'b1) ? wire_nlllO0i_dataout : nlliliO;
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assign wire_nlllill_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1l_dataout : nllilii;
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assign wire_nllliOl_dataout = (nl0O0il === 1'b1) ? wire_nlllO0l_dataout : nllilli;
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assign wire_nlllilO_dataout = (nl0O1ll === 1'b1) ? wire_nlllO1O_dataout : nllilil;
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assign wire_nllliOO_dataout = (nl0O0il === 1'b1) ? wire_nlllO0O_dataout : nllilll;
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assign wire_nllliOi_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0i_dataout : nlliliO;
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assign wire_nllll0i_dataout = (nl0O0il === 1'b1) ? wire_nlllOli_dataout : nllilOO;
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assign wire_nllliOl_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0l_dataout : nllilli;
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assign wire_nllll0l_dataout = (nl0O0il === 1'b1) ? wire_nlllOll_dataout : nlliO1i;
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assign wire_nllliOO_dataout = (nl0O1ll === 1'b1) ? wire_nlllO0O_dataout : nllilll;
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assign wire_nllll0O_dataout = (nl0O0il === 1'b1) ? wire_nlllOlO_dataout : nlliO1l;
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assign wire_nllll0i_dataout = (nl0O1ll === 1'b1) ? wire_nlllOli_dataout : nllilOO;
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assign wire_nllll1i_dataout = (nl0O0il === 1'b1) ? wire_nlllOii_dataout : nllillO;
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assign wire_nllll0l_dataout = (nl0O1ll === 1'b1) ? wire_nlllOll_dataout : nlliO1i;
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assign wire_nllll1l_dataout = (nl0O0il === 1'b1) ? wire_nlllOil_dataout : nllilOi;
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assign wire_nllll0O_dataout = (nl0O1ll === 1'b1) ? wire_nlllOlO_dataout : nlliO1l;
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assign wire_nllll1O_dataout = (nl0O0il === 1'b1) ? wire_nlllOiO_dataout : nllilOl;
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assign wire_nllll1i_dataout = (nl0O1ll === 1'b1) ? wire_nlllOii_dataout : nllillO;
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and(wire_nlllli_dataout, wire_nlllOl_o[4], nli001l);
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assign wire_nllll1l_dataout = (nl0O1ll === 1'b1) ? wire_nlllOil_dataout : nllilOi;
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assign wire_nllllii_dataout = (nl0O0il === 1'b1) ? wire_nlllOOi_dataout : nlliO1O;
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assign wire_nllll1O_dataout = (nl0O1ll === 1'b1) ? wire_nlllOiO_dataout : nllilOl;
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assign wire_nllllil_dataout = (nl0O0il === 1'b1) ? wire_nlllOOl_dataout : nlliO0i;
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assign wire_nllllii_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOi_dataout : nlliO1O;
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assign wire_nlllliO_dataout = (nl0O0il === 1'b1) ? wire_nlllOOO_dataout : nlliO0l;
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assign wire_nllllil_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOl_dataout : nlliO0i;
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and(wire_nlllll_dataout, wire_nlllOl_o[5], nli001l);
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assign wire_nlllliO_dataout = (nl0O1ll === 1'b1) ? wire_nlllOOO_dataout : nlliO0l;
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assign wire_nllllli_dataout = (nl0O0il === 1'b1) ? wire_nllO11i_dataout : nlliO0O;
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assign wire_nllllli_dataout = (nl0O1ll === 1'b1) ? wire_nllO11i_dataout : nlliO0O;
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assign wire_nllllll_dataout = (nl0O0il === 1'b1) ? wire_nllO11l_dataout : nlliOii;
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assign wire_nllllll_dataout = (nl0O1ll === 1'b1) ? wire_nllO11l_dataout : nlliOii;
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assign wire_nlllllO_dataout = (nl0O0il === 1'b1) ? wire_nllO11O_dataout : nlliOil;
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assign wire_nlllllO_dataout = (nl0O1ll === 1'b1) ? wire_nllO11O_dataout : nlliOil;
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and(wire_nllllO_dataout, wire_nlllOl_o[6], nli001l);
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assign wire_nllllOi_dataout = (nl0O1ll === 1'b1) ? wire_nllO10i_dataout : nlliOiO;
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assign wire_nllllOi_dataout = (nl0O0il === 1'b1) ? wire_nllO10i_dataout : nlliOiO;
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assign wire_nllllOl_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[0] : nllil1i;
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assign wire_nllllOl_dataout = (nl0O0il === 1'b1) ? wire_nllO10l_dataout : nlliOli;
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assign wire_nllllOO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[1] : nllil0l;
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assign wire_nllllOO_dataout = (nl0O0il === 1'b1) ? wire_nllO10O_dataout : nlliOll;
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assign wire_nlllO0i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[5] : nlliliO;
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assign wire_nlllO0i_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[1] : nlliliO;
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assign wire_nlllO0l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[6] : nllilli;
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assign wire_nlllO0l_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[2] : nllilli;
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assign wire_nlllO0O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[7] : nllilll;
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assign wire_nlllO0O_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[3] : nllilll;
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assign wire_nlllO1i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[2] : nllil0O;
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assign wire_nlllO1i_dataout = (nl0O0il === 1'b1) ? wire_nllO1ii_dataout : nlliOlO;
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assign wire_nlllO1l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[3] : nllilii;
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assign wire_nlllO1l_dataout = (nl0O0il === 1'b1) ? wire_nllO1il_dataout : nlliOOi;
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assign wire_nlllO1O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[4] : nllilil;
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assign wire_nlllO1O_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[0] : nllil0l;
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and(wire_nlllOi_dataout, wire_nllO0O_o[0], nli01ii);
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and(wire_nlllOi_dataout, wire_nlllOl_o[7], nli001l);
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assign wire_nlllOii_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[8] : nllillO;
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assign wire_nlllOii_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[4] : nllillO;
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assign wire_nlllOil_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[9] : nllilOi;
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assign wire_nlllOil_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[5] : nllilOi;
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assign wire_nlllOiO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[10] : nllilOl;
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assign wire_nlllOiO_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[6] : nllilOl;
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and(wire_nlllOl_dataout, wire_nllO0O_o[1], nli01ii);
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assign wire_nlllOli_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[7] : nllilOO;
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assign wire_nlllOli_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[11] : nllilOO;
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assign wire_nlllOll_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[8] : nlliO1i;
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assign wire_nlllOll_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[12] : nlliO1i;
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assign wire_nlllOlO_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[9] : nlliO1l;
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assign wire_nlllOlO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[13] : nlliO1l;
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assign wire_nlllOOi_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[10] : nlliO1O;
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and(wire_nlllOO_dataout, wire_nllO0O_o[2], nli01ii);
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assign wire_nlllOOl_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[11] : nlliO0i;
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assign wire_nlllOOi_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[14] : nlliO1O;
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assign wire_nlllOOO_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[12] : nlliO0l;
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assign wire_nlllOOl_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[15] : nlliO0i;
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and(wire_nllO00i_dataout, ((~ (nlO100l ^ nlO111O)) & nl0O0ll), ~(wire_nlill1i_dout));
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assign wire_nlllOOO_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[16] : nlliO0l;
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and(wire_nllO00l_dataout, ((~ nl0O0lO) & (nl0Oi1i & nl0O0Oi)), ~(wire_nlill1i_dout));
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and(wire_nllO01i_dataout, ((~ nl0O1OO) & (nl0O00i & nl0O01i)), ~(wire_nliliil_dout));
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and(wire_nllO00O_dataout, ((~ nl0O0lO) & nl0Oi1i), ~(wire_nlill1i_dout));
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and(wire_nllO01l_dataout, ((~ nl0O1OO) & nl0O00i), ~(wire_nliliil_dout));
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assign wire_nllO10i_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[16] : nlliOiO;
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and(wire_nllO0i_dataout, wire_nllO0O_o[6], nli01ii);
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assign wire_nllO10l_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[17] : nlliOli;
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and(wire_nllO0l_dataout, wire_nllO0O_o[7], nli01ii);
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assign wire_nllO10O_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[18] : nlliOll;
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assign wire_nllO10i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[20] : nlliOiO;
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assign wire_nllO11i_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[13] : nlliO0O;
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assign wire_nllO11i_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[17] : nlliO0O;
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assign wire_nllO11l_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[14] : nlliOii;
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assign wire_nllO11l_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[18] : nlliOii;
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assign wire_nllO11O_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[15] : nlliOil;
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assign wire_nllO11O_dataout = ((~ nll0lll) === 1'b1) ? wire_nllO10l_o[19] : nlliOil;
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assign wire_nllO1ii_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[19] : nlliOlO;
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and(wire_nllO1i_dataout, wire_nllO0O_o[3], nli01ii);
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assign wire_nllO1il_dataout = ((~ nll0lOO) === 1'b1) ? wire_nllO1iO_o[20] : nlliOOi;
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and(wire_nllO1l_dataout, wire_nllO0O_o[4], nli01ii);
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and(wire_nllOili_dataout, wire_nllOiOl_dataout, ~(wire_nlill1i_dout));
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and(wire_nllO1O_dataout, wire_nllO0O_o[5], nli01ii);
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and(wire_nllOill_dataout, wire_nllOiOO_dataout, ~(wire_nlill1i_dout));
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and(wire_nllO1OO_dataout, ((~ (nlO101i ^ nllOOOl)) & nl0O1Ol), ~(wire_nliliil_dout));
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and(wire_nllOilO_dataout, wire_nllOliO_dataout, ~(wire_nlill1i_dout));
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and(wire_nllOi0O_dataout, wire_nllOili_dataout, ~(wire_nliliil_dout));
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and(wire_nllOiOi_dataout, wire_nllOlli_dataout, ~(wire_nlill1i_dout));
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and(wire_nllOiii_dataout, wire_nllOill_dataout, ~(wire_nliliil_dout));
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assign wire_nllOiOl_dataout = (nlOO11i === 1'b1) ? wire_nllOl1O_dataout : wire_nllOl1i_dataout;
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and(wire_nllOiil_dataout, wire_nllOl0l_dataout, ~(wire_nliliil_dout));
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assign wire_nllOiOO_dataout = (nlOO11i === 1'b1) ? wire_nllOl0i_dataout : wire_nllOl1l_dataout;
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and(wire_nllOiiO_dataout, wire_nllOl0O_dataout, ~(wire_nliliil_dout));
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and(wire_nllOl0i_dataout, wire_nllOl0O_dataout, nl0O0Ol);
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assign wire_nllOili_dataout = (nlOlOlO === 1'b1) ? wire_nllOiOl_dataout : wire_nllOilO_dataout;
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assign wire_nllOl0l_dataout = ((~ nl0O0Oi) === 1'b1) ? wire_nllOlii_o[0] : nllO01O;
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assign wire_nllOill_dataout = (nlOlOlO === 1'b1) ? wire_nllOiOO_dataout : wire_nllOiOi_dataout;
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assign wire_nllOl0O_dataout = ((~ nl0O0Oi) === 1'b1) ? wire_nllOlii_o[1] : nllOi0O;
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and(wire_nllOilO_dataout, nllO1Ol, ~(nlOl10i));
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and(wire_nllOl1i_dataout, nllO01O, ~(nlOl1il));
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and(wire_nllOiOi_dataout, nllOi1l, ~(nlOl10i));
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and(wire_nllOl1l_dataout, nllOi0O, ~(nlOl1il));
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and(wire_nllOiOl_dataout, wire_nllOl1i_dataout, nl0O01l);
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and(wire_nllOl1O_dataout, wire_nllOl0l_dataout, nl0O0Ol);
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and(wire_nllOiOO_dataout, wire_nllOl1l_dataout, nl0O01l);
|
assign wire_nllOliO_dataout = (nlOO11i === 1'b1) ? wire_nllOlOi_dataout : wire_nllOlll_dataout;
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assign wire_nllOl0l_dataout = (nlOlOlO === 1'b1) ? wire_nllOliO_dataout : wire_nllOlii_dataout;
|
assign wire_nllOlli_dataout = (nlOO11i === 1'b1) ? wire_nllOlOl_dataout : wire_nllOllO_dataout;
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assign wire_nllOl0O_dataout = (nlOlOlO === 1'b1) ? wire_nllOlli_dataout : wire_nllOlil_dataout;
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and(wire_nllOlll_dataout, nllOiii, ~(nlOl1il));
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assign wire_nllOl1i_dataout = ((~ nl0O01i) === 1'b1) ? wire_nllOl1O_o[0] : nllO1Ol;
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and(wire_nllOllO_dataout, nllOiil, ~(nlOl1il));
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assign wire_nllOl1l_dataout = ((~ nl0O01i) === 1'b1) ? wire_nllOl1O_o[1] : nllOi1l;
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and(wire_nllOlOi_dataout, wire_nllOlOO_dataout, nl0Oi1l);
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and(wire_nllOlii_dataout, nllOi1O, ~(nlOl10i));
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and(wire_nllOlOl_dataout, wire_nllOO1i_dataout, nl0Oi1l);
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and(wire_nllOlil_dataout, nllOi0i, ~(nlOl10i));
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assign wire_nllOlOO_dataout = ((~ nl0Oi1i) === 1'b1) ? wire_nllOO1l_o[0] : nllOiii;
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and(wire_nllOliO_dataout, wire_nllOlll_dataout, nl0O00l);
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assign wire_nllOO1i_dataout = ((~ nl0Oi1i) === 1'b1) ? wire_nllOO1l_o[1] : nllOiil;
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and(wire_nllOlli_dataout, wire_nllOllO_dataout, nl0O00l);
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assign wire_nlO000i_dataout = (nl0Oi0l === 1'b1) ? nlO11Oi : nllOOlO;
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assign wire_nllOlll_dataout = ((~ nl0O00i) === 1'b1) ? wire_nllOlOi_o[0] : nllOi1O;
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assign wire_nlO000l_dataout = (nl0Oi0l === 1'b1) ? nlO11Ol : nllOOOi;
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assign wire_nllOllO_dataout = ((~ nl0O00i) === 1'b1) ? wire_nllOlOi_o[1] : nllOi0i;
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assign wire_nlO000O_dataout = (nl0Oi0l === 1'b1) ? nlO11OO : nllOOOl;
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assign wire_nlO000i_dataout = (nl0O0il === 1'b1) ? nlO11Oi : nllOOlO;
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assign wire_nlO001i_dataout = (nl0Oi0l === 1'b1) ? nlO11li : nllOOiO;
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assign wire_nlO000l_dataout = (nl0O0il === 1'b1) ? nlO11Ol : nllOOOi;
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assign wire_nlO001l_dataout = (nl0Oi0l === 1'b1) ? nlO11ll : nllOOli;
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assign wire_nlO000O_dataout = (nl0O0il === 1'b1) ? nlO101i : nllOOOl;
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assign wire_nlO001O_dataout = (nl0Oi0l === 1'b1) ? nlO11lO : nllOOll;
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assign wire_nlO001i_dataout = (nl0O0il === 1'b1) ? nlO11li : nllOOiO;
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assign wire_nlO00ii_dataout = (nl0Oi0l === 1'b1) ? nlO101i : nllOOOO;
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assign wire_nlO001l_dataout = (nl0O0il === 1'b1) ? nlO11ll : nllOOli;
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assign wire_nlO00il_dataout = (nl0Oi0l === 1'b1) ? nlO101l : nlO111i;
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assign wire_nlO001O_dataout = (nl0O0il === 1'b1) ? nlO11lO : nllOOll;
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assign wire_nlO00iO_dataout = (nl0Oi0l === 1'b1) ? nlO101O : nlO111l;
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and(wire_nlO00il_dataout, wire_nlO0iiO_dataout, ~(nlOl10i));
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assign wire_nlO00li_dataout = (nl0Oi0l === 1'b1) ? nlO100l : nlO111O;
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and(wire_nlO00iO_dataout, wire_nlO0ili_dataout, ~(nlOl10i));
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and(wire_nlO00lO_dataout, wire_nlO0iOi_dataout, ~(nlOl1il));
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and(wire_nlO00li_dataout, wire_nlO0ill_dataout, ~(nlOl10i));
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and(wire_nlO00Oi_dataout, wire_nlO0iOl_dataout, ~(nlOl1il));
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and(wire_nlO00ll_dataout, wire_nlO0ilO_dataout, ~(nlOl10i));
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and(wire_nlO00Ol_dataout, wire_nlO0iOO_dataout, ~(nlOl1il));
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and(wire_nlO00lO_dataout, wire_nlO0iOi_dataout, ~(nlOl10i));
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and(wire_nlO00OO_dataout, wire_nlO0l1i_dataout, ~(nlOl1il));
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and(wire_nlO00Oi_dataout, wire_nlO0iOl_dataout, ~(nlOl10i));
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and(wire_nlO010i_dataout, wire_nlO0i0O_dataout, ~(nlOi00O));
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and(wire_nlO00Ol_dataout, wire_nlO0iOO_dataout, ~(nlOl10i));
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and(wire_nlO010l_dataout, wire_nlO0iii_dataout, ~(nlOi00O));
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and(wire_nlO00OO_dataout, wire_nlO0l1i_dataout, ~(nlOl10i));
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and(wire_nlO010O_dataout, wire_nlO0iil_dataout, ~(nlOi00O));
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and(wire_nlO010i_dataout, wire_nlO0i0O_dataout, ~(nlOi01l));
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and(wire_nlO011i_dataout, wire_nlO0i1O_dataout, ~(nlOi00O));
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and(wire_nlO010l_dataout, wire_nlO0iii_dataout, ~(nlOi01l));
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and(wire_nlO011l_dataout, wire_nlO0i0i_dataout, ~(nlOi00O));
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and(wire_nlO010O_dataout, wire_nlO0iil_dataout, ~(nlOi01l));
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and(wire_nlO011O_dataout, wire_nlO0i0l_dataout, ~(nlOi00O));
|
and(wire_nlO011i_dataout, wire_nlO0i1O_dataout, ~(nlOi01l));
|
and(wire_nlO01ii_dataout, wire_nlO0iiO_dataout, ~(nlOi00O));
|
and(wire_nlO011l_dataout, wire_nlO0i0i_dataout, ~(nlOi01l));
|
and(wire_nlO01il_dataout, wire_nlO0ili_dataout, ~(nlOi00O));
|
and(wire_nlO011O_dataout, wire_nlO0i0l_dataout, ~(nlOi01l));
|
and(wire_nlO01iO_dataout, wire_nlO0ill_dataout, ~(nlOi00O));
|
assign wire_nlO01ii_dataout = (nl0O0il === 1'b1) ? nlO111i : nllOi0l;
|
and(wire_nlO01li_dataout, wire_nlO0ilO_dataout, ~(nlOi00O));
|
assign wire_nlO01il_dataout = (nl0O0il === 1'b1) ? nlO111l : nllOO1i;
|
assign wire_nlO01ll_dataout = (nl0Oi0l === 1'b1) ? nlO110l : nllOiiO;
|
assign wire_nlO01iO_dataout = (nl0O0il === 1'b1) ? nlO111O : nllOO1l;
|
assign wire_nlO01lO_dataout = (nl0Oi0l === 1'b1) ? nlO110O : nllOO0l;
|
assign wire_nlO01li_dataout = (nl0O0il === 1'b1) ? nlO110i : nllOO1O;
|
assign wire_nlO01Oi_dataout = (nl0Oi0l === 1'b1) ? nlO11ii : nllOO0O;
|
assign wire_nlO01ll_dataout = (nl0O0il === 1'b1) ? nlO110l : nllOO0i;
|
assign wire_nlO01Ol_dataout = (nl0Oi0l === 1'b1) ? nlO11il : nllOOii;
|
assign wire_nlO01lO_dataout = (nl0O0il === 1'b1) ? nlO110O : nllOO0l;
|
assign wire_nlO01OO_dataout = (nl0Oi0l === 1'b1) ? nlO11iO : nllOOil;
|
assign wire_nlO01Oi_dataout = (nl0O0il === 1'b1) ? nlO11ii : nllOO0O;
|
and(wire_nlO0i0i_dataout, wire_nlO0l0l_dataout, ~(nlOl1il));
|
assign wire_nlO01Ol_dataout = (nl0O0il === 1'b1) ? nlO11il : nllOOii;
|
and(wire_nlO0i0l_dataout, wire_nlO0l0O_dataout, ~(nlOl1il));
|
assign wire_nlO01OO_dataout = (nl0O0il === 1'b1) ? nlO11iO : nllOOil;
|
and(wire_nlO0i0O_dataout, wire_nlO0lii_dataout, ~(nlOl1il));
|
and(wire_nlO0i0i_dataout, wire_nlO0l0l_dataout, ~(nlOl10i));
|
and(wire_nlO0i1i_dataout, wire_nlO0l1l_dataout, ~(nlOl1il));
|
and(wire_nlO0i0l_dataout, wire_nlO0l0O_dataout, ~(nlOl10i));
|
and(wire_nlO0i1l_dataout, wire_nlO0l1O_dataout, ~(nlOl1il));
|
and(wire_nlO0i0O_dataout, wire_nlO0lii_dataout, ~(nlOl10i));
|
and(wire_nlO0i1O_dataout, wire_nlO0l0i_dataout, ~(nlOl1il));
|
and(wire_nlO0i1i_dataout, wire_nlO0l1l_dataout, ~(nlOl10i));
|
and(wire_nlO0iii_dataout, wire_nlO0lil_dataout, ~(nlOl1il));
|
and(wire_nlO0i1l_dataout, wire_nlO0l1O_dataout, ~(nlOl10i));
|
and(wire_nlO0iil_dataout, wire_nlO0liO_dataout, ~(nlOl1il));
|
and(wire_nlO0i1O_dataout, wire_nlO0l0i_dataout, ~(nlOl10i));
|
and(wire_nlO0iiO_dataout, wire_nlO0lli_dataout, ~(nlOl1il));
|
and(wire_nlO0iii_dataout, wire_nlO0lil_dataout, ~(nlOl10i));
|
and(wire_nlO0ili_dataout, wire_nlO0lll_dataout, ~(nlOl1il));
|
and(wire_nlO0iil_dataout, wire_nlO0liO_dataout, ~(nlOl10i));
|
and(wire_nlO0ill_dataout, wire_nlO0llO_dataout, ~(nlOl1il));
|
assign wire_nlO0iiO_dataout = (nlOlOlO === 1'b1) ? nlOO11l : nlO111i;
|
and(wire_nlO0ilO_dataout, wire_nlO0lOi_dataout, ~(nlOl1il));
|
assign wire_nlO0ili_dataout = (nlOlOlO === 1'b1) ? nlOO10i : nlO111l;
|
assign wire_nlO0iOi_dataout = (nlOO11i === 1'b1) ? nlOO10O : nlO110l;
|
assign wire_nlO0ill_dataout = (nlOlOlO === 1'b1) ? nlOO10l : nlO111O;
|
assign wire_nlO0iOl_dataout = (nlOO11i === 1'b1) ? nlOO1il : nlO110O;
|
assign wire_nlO0ilO_dataout = (nlOlOlO === 1'b1) ? nlOO10O : nlO110i;
|
assign wire_nlO0iOO_dataout = (nlOO11i === 1'b1) ? nlOO1iO : nlO11ii;
|
assign wire_nlO0iOi_dataout = (nlOlOlO === 1'b1) ? nlOO1ii : nlO110l;
|
assign wire_nlO0l0i_dataout = (nlOO11i === 1'b1) ? nlOO1Oi : nlO11ll;
|
assign wire_nlO0iOl_dataout = (nlOlOlO === 1'b1) ? nlOO1il : nlO110O;
|
assign wire_nlO0l0l_dataout = (nlOO11i === 1'b1) ? nlOO1Ol : nlO11lO;
|
assign wire_nlO0iOO_dataout = (nlOlOlO === 1'b1) ? nlOO1iO : nlO11ii;
|
assign wire_nlO0l0O_dataout = (nlOO11i === 1'b1) ? nlOO1OO : nlO11Oi;
|
assign wire_nlO0l0i_dataout = (nlOlOlO === 1'b1) ? nlOO1Oi : nlO11ll;
|
assign wire_nlO0l1i_dataout = (nlOO11i === 1'b1) ? nlOO1li : nlO11il;
|
assign wire_nlO0l0l_dataout = (nlOlOlO === 1'b1) ? nlOO1Ol : nlO11lO;
|
assign wire_nlO0l1l_dataout = (nlOO11i === 1'b1) ? nlOO1ll : nlO11iO;
|
assign wire_nlO0l0O_dataout = (nlOlOlO === 1'b1) ? nlOO1OO : nlO11Oi;
|
assign wire_nlO0l1O_dataout = (nlOO11i === 1'b1) ? nlOO1lO : nlO11li;
|
assign wire_nlO0l1i_dataout = (nlOlOlO === 1'b1) ? nlOO1li : nlO11il;
|
assign wire_nlO0lii_dataout = (nlOO11i === 1'b1) ? nlOO01i : nlO11Ol;
|
assign wire_nlO0l1l_dataout = (nlOlOlO === 1'b1) ? nlOO1ll : nlO11iO;
|
assign wire_nlO0lil_dataout = (nlOO11i === 1'b1) ? nlOO01l : nlO11OO;
|
assign wire_nlO0l1O_dataout = (nlOlOlO === 1'b1) ? nlOO1lO : nlO11li;
|
assign wire_nlO0liO_dataout = (nlOO11i === 1'b1) ? nlOO01O : nlO101i;
|
assign wire_nlO0lii_dataout = (nlOlOlO === 1'b1) ? nlOO01i : nlO11Ol;
|
and(wire_nlO0ll_dataout, write, wire_nlOi1O_o);
|
assign wire_nlO0lil_dataout = (nlOlOlO === 1'b1) ? nlOO01l : nlO11OO;
|
assign wire_nlO0lli_dataout = (nlOO11i === 1'b1) ? nlOO00i : nlO101l;
|
assign wire_nlO0liO_dataout = (nlOlOlO === 1'b1) ? nlOO01O : nlO101i;
|
assign wire_nlO0lll_dataout = (nlOO11i === 1'b1) ? nlOO00l : nlO101O;
|
and(wire_nlO0Oll_dataout, (~ nl0Oi0i), ~(nl0Oi1i));
|
assign wire_nlO0llO_dataout = (nlOO11i === 1'b1) ? nlOO00O : nlO100i;
|
and(wire_nlO0OlO_dataout, nl0Oi0i, ~(nl0Oi1i));
|
assign wire_nlO0lOi_dataout = (nlOO11i === 1'b1) ? nlOO0ii : nlO100l;
|
and(wire_nlO0OOl_dataout, (~ nl0Oi0i), ~(nl0Oi1l));
|
and(wire_nlO0OOO_dataout, (~ nl0Ol1i), ~(nl0OiOi));
|
and(wire_nlO0OOO_dataout, nl0Oi0i, ~(nl0Oi1l));
|
and(wire_nlO10ii_dataout, wire_nlO1liO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO100i_dataout, wire_nlO1l0O_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10il_dataout, wire_nlO1lli_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO100l_dataout, wire_nlO1lii_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10iO_dataout, wire_nlO1lll_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO100O_dataout, wire_nlO1lil_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10li_dataout, wire_nlO1llO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO101O_dataout, wire_nlO1l0l_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10ll_dataout, wire_nlO1lOi_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10ii_dataout, wire_nlO1liO_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10lO_dataout, wire_nlO1lOl_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10il_dataout, wire_nlO1lli_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10Oi_dataout, wire_nlO1lOO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10iO_dataout, wire_nlO1lll_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10Ol_dataout, wire_nlO1O1i_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO10li_dataout, wire_nlO1llO_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO10OO_dataout, wire_nlO1O1l_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10ll_dataout, wire_nlO1lOi_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1i0i_dataout, wire_nlO1O0O_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO10lO_dataout, wire_nlO1lOl_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1i0l_dataout, wire_nlO1Oii_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10Oi_dataout, wire_nlO1lOO_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1i0O_dataout, wire_nlO1Oil_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO10Ol_dataout, wire_nlO1O1i_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1i1i_dataout, wire_nlO1O1O_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO10OO_dataout, wire_nlO1O1l_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1i1l_dataout, wire_nlO1O0i_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1i0i_dataout, wire_nlO1O0O_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1i1O_dataout, wire_nlO1O0l_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1i0l_dataout, wire_nlO1Oii_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1iii_dataout, wire_nlO1OiO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1i0O_dataout, wire_nlO1Oil_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1iil_dataout, wire_nlO1Oli_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1i1i_dataout, wire_nlO1O1O_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1iiO_dataout, wire_nlO1Oll_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1i1l_dataout, wire_nlO1O0i_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1ili_dataout, wire_nlO1OlO_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1i1O_dataout, wire_nlO1O0l_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1ill_dataout, wire_nlO1OOi_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1iii_dataout, wire_nlO1OiO_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1ilO_dataout, wire_nlO1OOl_dataout, ~(wire_nlill1i_dout));
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and(wire_nlO1iil_dataout, wire_nlO1Oli_dataout, ~(wire_nliliil_dout));
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and(wire_nlO1iOi_dataout, wire_nlO1OOO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1iiO_dataout, wire_nlO1Oll_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1iOl_dataout, wire_nlO011i_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1ili_dataout, wire_nlO1OlO_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1iOO_dataout, wire_nlO011l_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1ill_dataout, wire_nlO1OOi_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l0i_dataout, wire_nlO010O_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1ilO_dataout, wire_nlO1OOl_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l0l_dataout, wire_nlO01ii_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1iOi_dataout, wire_nlO1OOO_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l0O_dataout, wire_nlO01il_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1iOl_dataout, wire_nlO011i_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l1i_dataout, wire_nlO011O_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1iOO_dataout, wire_nlO011l_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l1l_dataout, wire_nlO010i_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1l0i_dataout, wire_nlO010O_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1l1O_dataout, wire_nlO010l_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1l0l_dataout, wire_nlO01ii_dataout, ~(nlOi01l));
|
and(wire_nlO1lii_dataout, wire_nlO01iO_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1l0O_dataout, wire_nlO01il_dataout, ~(nlOi01l));
|
and(wire_nlO1lil_dataout, wire_nlO01li_dataout, ~(wire_nlill1i_dout));
|
and(wire_nlO1l1i_dataout, wire_nlO011O_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1liO_dataout, wire_nlO01ll_dataout, ~(nlOi00O));
|
and(wire_nlO1l1l_dataout, wire_nlO010i_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1lli_dataout, wire_nlO01lO_dataout, ~(nlOi00O));
|
and(wire_nlO1l1O_dataout, wire_nlO010l_dataout, ~(wire_nliliil_dout));
|
and(wire_nlO1lll_dataout, wire_nlO01Oi_dataout, ~(nlOi00O));
|
and(wire_nlO1lii_dataout, wire_nlO01iO_dataout, ~(nlOi01l));
|
and(wire_nlO1llO_dataout, wire_nlO01Ol_dataout, ~(nlOi00O));
|
and(wire_nlO1lil_dataout, wire_nlO01li_dataout, ~(nlOi01l));
|
and(wire_nlO1lOi_dataout, wire_nlO01OO_dataout, ~(nlOi00O));
|
and(wire_nlO1liO_dataout, wire_nlO01ll_dataout, ~(nlOi01l));
|
and(wire_nlO1lOl_dataout, wire_nlO001i_dataout, ~(nlOi00O));
|
and(wire_nlO1lli_dataout, wire_nlO01lO_dataout, ~(nlOi01l));
|
and(wire_nlO1lOO_dataout, wire_nlO001l_dataout, ~(nlOi00O));
|
and(wire_nlO1lll_dataout, wire_nlO01Oi_dataout, ~(nlOi01l));
|
and(wire_nlO1O0i_dataout, wire_nlO000O_dataout, ~(nlOi00O));
|
and(wire_nlO1llO_dataout, wire_nlO01Ol_dataout, ~(nlOi01l));
|
and(wire_nlO1O0l_dataout, wire_nlO00ii_dataout, ~(nlOi00O));
|
and(wire_nlO1lOi_dataout, wire_nlO01OO_dataout, ~(nlOi01l));
|
and(wire_nlO1O0O_dataout, wire_nlO00il_dataout, ~(nlOi00O));
|
and(wire_nlO1lOl_dataout, wire_nlO001i_dataout, ~(nlOi01l));
|
and(wire_nlO1O1i_dataout, wire_nlO001O_dataout, ~(nlOi00O));
|
and(wire_nlO1lOO_dataout, wire_nlO001l_dataout, ~(nlOi01l));
|
and(wire_nlO1O1l_dataout, wire_nlO000i_dataout, ~(nlOi00O));
|
and(wire_nlO1O0i_dataout, wire_nlO000O_dataout, ~(nlOi01l));
|
and(wire_nlO1O1O_dataout, wire_nlO000l_dataout, ~(nlOi00O));
|
and(wire_nlO1O0l_dataout, nl0O0ii, ~(nlOi01l));
|
and(wire_nlO1Oii_dataout, wire_nlO00iO_dataout, ~(nlOi00O));
|
and(wire_nlO1O0O_dataout, wire_nlO00il_dataout, ~(nlOi01l));
|
and(wire_nlO1Oil_dataout, wire_nlO00li_dataout, ~(nlOi00O));
|
and(wire_nlO1O1i_dataout, wire_nlO001O_dataout, ~(nlOi01l));
|
and(wire_nlO1OiO_dataout, nl0Oi0i, ~(nlOi00O));
|
and(wire_nlO1O1l_dataout, wire_nlO000i_dataout, ~(nlOi01l));
|
and(wire_nlO1Oli_dataout, wire_nlO00lO_dataout, ~(nlOi00O));
|
and(wire_nlO1O1O_dataout, wire_nlO000l_dataout, ~(nlOi01l));
|
and(wire_nlO1Oll_dataout, wire_nlO00Oi_dataout, ~(nlOi00O));
|
and(wire_nlO1Oii_dataout, wire_nlO00iO_dataout, ~(nlOi01l));
|
and(wire_nlO1OlO_dataout, wire_nlO00Ol_dataout, ~(nlOi00O));
|
and(wire_nlO1Oil_dataout, wire_nlO00li_dataout, ~(nlOi01l));
|
and(wire_nlO1OOi_dataout, wire_nlO00OO_dataout, ~(nlOi00O));
|
and(wire_nlO1OiO_dataout, wire_nlO00ll_dataout, ~(nlOi01l));
|
and(wire_nlO1OOl_dataout, wire_nlO0i1i_dataout, ~(nlOi00O));
|
and(wire_nlO1Oli_dataout, wire_nlO00lO_dataout, ~(nlOi01l));
|
and(wire_nlO1OOO_dataout, wire_nlO0i1l_dataout, ~(nlOi00O));
|
and(wire_nlO1Oll_dataout, wire_nlO00Oi_dataout, ~(nlOi01l));
|
and(wire_nlOi0il_dataout, wire_nlO0lOl_o, ~(nl0Ol0i));
|
and(wire_nlO1OlO_dataout, wire_nlO00Ol_dataout, ~(nlOi01l));
|
and(wire_nlOi0iO_dataout, wire_nlO0O1i_o, ~(nl0Ol0i));
|
and(wire_nlO1OOi_dataout, wire_nlO00OO_dataout, ~(nlOi01l));
|
and(wire_nlOi0li_dataout, wire_nlO0O1O_o, ~(nl0Ol0i));
|
and(wire_nlO1OOl_dataout, wire_nlO0i1i_dataout, ~(nlOi01l));
|
and(wire_nlOi0ll_dataout, wire_nlO0O0l_o, ~(nl0Ol0i));
|
and(wire_nlO1OOO_dataout, wire_nlO0i1l_dataout, ~(nlOi01l));
|
and(wire_nlOi0lO_dataout, wire_nlO0Oii_o, ~(nl0Ol0i));
|
and(wire_nlOi00i_dataout, wire_nlO0lli_o, ~(nl0Oiii));
|
and(wire_nlOi0Oi_dataout, wire_nlO0OiO_o, ~(nl0Ol0i));
|
and(wire_nlOi00l_dataout, wire_nlO0llO_o, ~(nl0Oiii));
|
and(wire_nlOi0Ol_dataout, wire_nlO0Oll_o, ~(nl0Ol0i));
|
and(wire_nlOi00O_dataout, wire_nlO0lOl_o, ~(nl0Oiii));
|
or(wire_nlOi0OO_dataout, wire_nlO0OOi_o, nl0Ol0i);
|
and(wire_nlOi0ii_dataout, wire_nlO0O1i_o, ~(nl0Oiii));
|
and(wire_nlOi10i_dataout, nl0Ol1i, ~(nl0OiOl));
|
and(wire_nlOi0il_dataout, wire_nlO0O1O_o, ~(nl0Oiii));
|
and(wire_nlOi11i_dataout, nl0Ol1i, ~(nl0OiOi));
|
and(wire_nlOi0iO_dataout, wire_nlO0O0l_o, ~(nl0Oiii));
|
and(wire_nlOi11O_dataout, (~ nl0Ol1i), ~(nl0OiOl));
|
and(wire_nlOi0li_dataout, wire_nlO0Oii_o, ~(nl0Oiii));
|
and(wire_nlOi1ii_dataout, wire_nlOi1iO_dataout, ~(nl0Ol1l));
|
or(wire_nlOi0ll_dataout, wire_nlO0OiO_o, nl0Oiii);
|
and(wire_nlOi1il_dataout, wire_nlOi1li_dataout, ~(nl0Ol1l));
|
and(wire_nlOi10i_dataout, wire_nlOi10O_dataout, ~(nl0Oi0l));
|
and(wire_nlOi1iO_dataout, (~ nl0OiOO), ~(nl0Ol1i));
|
and(wire_nlOi10l_dataout, (~ nl0Oi1O), ~(nl0Oi0i));
|
or(wire_nlOi1li_dataout, nl0OiOO, nl0Ol1i);
|
or(wire_nlOi10O_dataout, nl0Oi1O, nl0Oi0i);
|
and(wire_nlOiiO_dataout, nli00li, ~((~ nlOOii)));
|
and(wire_nlOi11O_dataout, wire_nlOi10l_dataout, ~(nl0Oi0l));
|
or(wire_nlOil0i_dataout, wire_nlOil0l_dataout, wire_n111Ol_o);
|
and(wire_nlOi1O_dataout, write, wire_nlOili_o);
|
and(wire_nlOil0l_dataout, nlOil1i, ~((wire_nlOOOll_dataout | (wire_n111ii_dataout | (wire_n111ll_dataout | wire_nlOOOOl_o)))));
|
and(wire_nlOiiOl_dataout, wire_nlOiiOO_dataout, ~(n10OOi));
|
and(wire_nlOil1O_dataout, wire_nlOil0i_dataout, ~(n1i11l));
|
or(wire_nlOiiOO_dataout, wire_nlOil1i_dataout, wire_n111li_o);
|
and(wire_nlOili_dataout, wire_nlOiOl_dataout, ~((~ nlOOii)));
|
and(wire_nlOil1i_dataout, nlOiilO, ~((wire_nlOOOii_dataout | (wire_n1111O_dataout | (wire_n111ii_dataout | wire_nlOOOli_o)))));
|
and(wire_nlOill_dataout, wire_nlOiOO_dataout, ~((~ nlOOii)));
|
and(wire_nlOl00i_dataout, nlOiOll, ~(n10OOi));
|
and(wire_nlOilO_dataout, wire_nlOl1i_dataout, ~((~ nlOOii)));
|
and(wire_nlOl00l_dataout, nlOiOlO, ~(n10OOi));
|
or(wire_nlOiOi_dataout, wire_nlOl1l_dataout, (~ nlOOii));
|
and(wire_nlOl00O_dataout, wire_nlOlliO_dataout, ~(n10OOi));
|
and(wire_nlOiOl_dataout, nli00ii, ~(nli00li));
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and(wire_nlOl01i_dataout, nlOiOil, ~(n10OOi));
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and(wire_nlOiOO_dataout, wire_nlOl1O_dataout, ~(nli00li));
|
and(wire_nlOl01l_dataout, nlOiOiO, ~(n10OOi));
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and(wire_nlOl00i_dataout, nlOiOll, ~(n1i11l));
|
and(wire_nlOl01O_dataout, nlOiOli, ~(n10OOi));
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and(wire_nlOl00l_dataout, nlOiOlO, ~(n1i11l));
|
and(wire_nlOl0i_dataout, wire_nlOlil_dataout, ~((~ nlOOOi)));
|
and(wire_nlOl00O_dataout, nlOiOOi, ~(n1i11l));
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and(wire_nlOl0ii_dataout, wire_nlOllli_dataout, ~(n10OOi));
|
and(wire_nlOl01i_dataout, nlOiOil, ~(n1i11l));
|
and(wire_nlOl0il_dataout, wire_nlOllll_dataout, ~(n10OOi));
|
and(wire_nlOl01l_dataout, nlOiOiO, ~(n1i11l));
|
and(wire_nlOl0iO_dataout, wire_nlOlllO_dataout, ~(n10OOi));
|
and(wire_nlOl01O_dataout, nlOiOli, ~(n1i11l));
|
or(wire_nlOl0l_dataout, wire_nlOliO_dataout, (~ nlOOOi));
|
and(wire_nlOl0i_dataout, nli000O, ~(nli00ii));
|
and(wire_nlOl0li_dataout, wire_nlOllOi_dataout, ~(n10OOi));
|
and(wire_nlOl0ii_dataout, nlOiOOl, ~(n1i11l));
|
and(wire_nlOl0ll_dataout, wire_nlOllOl_dataout, ~(n10OOi));
|
and(wire_nlOl0il_dataout, nlOiOOO, ~(n1i11l));
|
and(wire_nlOl0lO_dataout, wire_nlOllOO_dataout, ~(n10OOi));
|
and(wire_nlOl0iO_dataout, nlOl11i, ~(n1i11l));
|
and(wire_nlOl0O_dataout, nli01lO, ~(nli01OO));
|
and(wire_nlOl0l_dataout, wire_nlOlii_dataout, ~(nli00ii));
|
and(wire_nlOl0Oi_dataout, wire_nlOlO1i_dataout, ~(n10OOi));
|
and(wire_nlOl0li_dataout, wire_nlOllOi_dataout, ~(n1i11l));
|
and(wire_nlOl0Ol_dataout, wire_nlOli0l_dataout, ~(n10OOi));
|
and(wire_nlOl0ll_dataout, wire_nlOllOl_dataout, ~(n1i11l));
|
and(wire_nlOl0OO_dataout, wire_nlOliii_dataout, ~(n10OOi));
|
and(wire_nlOl0lO_dataout, wire_nlOllOO_dataout, ~(n1i11l));
|
and(wire_nlOl10l_dataout, nlOillO, ~(n10OOi));
|
and(wire_nlOl0O_dataout, nli000l, ~(nli000O));
|
and(wire_nlOl10O_dataout, nlOilOi, ~(n10OOi));
|
and(wire_nlOl0Oi_dataout, wire_nlOlO1i_dataout, ~(n1i11l));
|
and(wire_nlOl1i_dataout, nli01OO, ~((~ nlOOOi)));
|
and(wire_nlOl0Ol_dataout, wire_nlOlO1l_dataout, ~(n1i11l));
|
and(wire_nlOl1ii_dataout, nlOilOl, ~(n10OOi));
|
and(wire_nlOl0OO_dataout, wire_nlOlO1O_dataout, ~(n1i11l));
|
and(wire_nlOl1il_dataout, nlOilOO, ~(n10OOi));
|
and(wire_nlOl1i_dataout, wire_nlOl0i_dataout, ~(nli00li));
|
and(wire_nlOl1iO_dataout, nlOiO1i, ~(n10OOi));
|
and(wire_nlOl1iO_dataout, nlOiO1i, ~(n1i11l));
|
and(wire_nlOl1l_dataout, wire_nlOl0O_dataout, ~((~ nlOOOi)));
|
and(wire_nlOl1l_dataout, wire_nlOl0l_dataout, ~(nli00li));
|
and(wire_nlOl1li_dataout, nlOiO1l, ~(n10OOi));
|
and(wire_nlOl1li_dataout, nlOiO1l, ~(n1i11l));
|
and(wire_nlOl1ll_dataout, nlOiO1O, ~(n10OOi));
|
and(wire_nlOl1ll_dataout, nlOiO1O, ~(n1i11l));
|
and(wire_nlOl1lO_dataout, nlOiO0i, ~(n10OOi));
|
and(wire_nlOl1lO_dataout, nlOiO0i, ~(n1i11l));
|
and(wire_nlOl1O_dataout, wire_nlOlii_dataout, ~((~ nlOOOi)));
|
and(wire_nlOl1O_dataout, wire_nlOl0O_dataout, ~(nli00ii));
|
and(wire_nlOl1Oi_dataout, nlOiO0l, ~(n10OOi));
|
and(wire_nlOl1Oi_dataout, nlOiO0l, ~(n1i11l));
|
and(wire_nlOl1Ol_dataout, nlOiO0O, ~(n10OOi));
|
and(wire_nlOl1Ol_dataout, nlOiO0O, ~(n1i11l));
|
and(wire_nlOl1OO_dataout, nlOiOii, ~(n10OOi));
|
and(wire_nlOl1OO_dataout, nlOiOii, ~(n1i11l));
|
and(wire_nlOli0i_dataout, wire_nlOlO1l_dataout, ~(n10OOi));
|
and(wire_nlOli0i_dataout, wire_nlOlill_dataout, ~(n1i11l));
|
or(wire_nlOli0l_dataout, wire_nlOli0O_dataout, wire_nlOOOii_dataout);
|
and(wire_nlOli0l_dataout, wire_nlOlilO_dataout, ~(n1i11l));
|
or(wire_nlOli0O_dataout, nlOiOOl, nl0Oili);
|
and(wire_nlOli0O_dataout, wire_nlOll1i_dataout, ~(n1i11l));
|
and(wire_nlOli1i_dataout, wire_nlOliil_dataout, ~(n10OOi));
|
and(wire_nlOli1i_dataout, wire_nlOlO0i_dataout, ~(n1i11l));
|
and(wire_nlOli1l_dataout, wire_nlOlilO_dataout, ~(n10OOi));
|
and(wire_nlOli1l_dataout, wire_nlOlO0l_dataout, ~(n1i11l));
|
and(wire_nlOli1O_dataout, wire_nlOllii_dataout, ~(n10OOi));
|
and(wire_nlOli1O_dataout, wire_nlOliiO_dataout, ~(n1i11l));
|
and(wire_nlOlii_dataout, wire_nlOlli_dataout, ~(nli01OO));
|
and(wire_nlOlii_dataout, (~ nli000l), ~(nli000O));
|
or(wire_nlOliii_dataout, nlOiOOO, nl0Oili);
|
and(wire_nlOliii_dataout, wire_nlOllll_dataout, ~(n1i11l));
|
or(wire_nlOliil_dataout, (wire_n1110i_o | wire_n1111O_dataout), ((n10lOl & wire_n111il_o) & nl0Oiil));
|
and(wire_nlOliil_dataout, wire_nlOlO0O_dataout, ~(n1i11l));
|
and(wire_nlOlil_dataout, wire_nlOlll_dataout, ~(nli01OO));
|
or(wire_nlOliiO_dataout, wire_nlOlili_dataout, wire_nlOOOll_dataout);
|
or(wire_nlOlilO_dataout, wire_nlOliOi_dataout, nl0Oili);
|
or(wire_nlOlili_dataout, nlOl11O, nl0Olii);
|
and(wire_nlOliO_dataout, wire_nlOllO_dataout, ~(nli01OO));
|
or(wire_nlOlill_dataout, nlOl10i, nl0Olii);
|
or(wire_nlOliOi_dataout, nlOl11l, nl0Oill);
|
or(wire_nlOlilO_dataout, (wire_n111il_o | wire_n111ii_dataout), ((n10O1O & wire_n111lO_o) & nl0Ol0l));
|
and(wire_nlOlli_dataout, wire_nlOlOi_dataout, ~(nli01lO));
|
or(wire_nlOll1i_dataout, wire_nlOll1l_dataout, nl0Olii);
|
or(wire_nlOllii_dataout, wire_nlOllil_dataout, nl0Oili);
|
or(wire_nlOll1l_dataout, nlOl10O, nl0Olil);
|
assign wire_nlOllil_dataout = (nl0Oill === 1'b1) ? nlOl11l : nlOl11O;
|
or(wire_nlOllll_dataout, wire_nlOlllO_dataout, nl0Olii);
|
or(wire_nlOlliO_dataout, wire_nlOlO1O_dataout, wire_n111li_o);
|
assign wire_nlOlllO_dataout = (nl0Olil === 1'b1) ? nlOl10O : nlOl1ii;
|
and(wire_nlOlll_dataout, nli01ll, ~(nli01lO));
|
or(wire_nlOllOi_dataout, wire_nlOlOii_dataout, wire_n111Ol_o);
|
and(wire_nlOllli_dataout, wire_nlOlO0i_dataout, ~(wire_n111li_o));
|
and(wire_nlOllOl_dataout, wire_nlOlOil_dataout, ~(wire_n111Ol_o));
|
or(wire_nlOllll_dataout, wire_nlOlO0l_dataout, wire_n111li_o);
|
or(wire_nlOllOO_dataout, wire_nlOlOiO_dataout, wire_n111Ol_o);
|
and(wire_nlOlllO_dataout, wire_nlOlO0O_dataout, ~(wire_n111li_o));
|
or(wire_nlOlO0i_dataout, wire_nlOlOOi_dataout, wire_n111Ol_o);
|
and(wire_nlOllO_dataout, wire_nlOlOl_dataout, ~(nli01lO));
|
and(wire_nlOlO0l_dataout, wire_nlOlOOl_dataout, ~(wire_n111Ol_o));
|
or(wire_nlOllOi_dataout, wire_nlOlOii_dataout, wire_n111li_o);
|
or(wire_nlOlO0O_dataout, nl0OliO, wire_n111Ol_o);
|
and(wire_nlOllOl_dataout, wire_nlOlOil_dataout, ~(wire_n111li_o));
|
and(wire_nlOlO1i_dataout, wire_nlOlOli_dataout, ~(wire_n111Ol_o));
|
or(wire_nlOllOO_dataout, wire_nlOlOiO_dataout, wire_n111li_o);
|
or(wire_nlOlO1l_dataout, wire_nlOlOll_dataout, wire_n111Ol_o);
|
assign wire_nlOlO0i_dataout = (nl0OilO === 1'b1) ? n10lii : wire_n1110i_o;
|
and(wire_nlOlO1O_dataout, wire_nlOlOlO_dataout, ~(wire_n111Ol_o));
|
assign wire_nlOlO0l_dataout = (nl0OilO === 1'b1) ? n10lil : wire_n1110i_o;
|
and(wire_nlOlOii_dataout, n10lli, nl0OliO);
|
assign wire_nlOlO0O_dataout = (nl0OilO === 1'b1) ? n10liO : wire_n1110i_o;
|
assign wire_nlOlOil_dataout = (nl0OliO === 1'b1) ? n10lll : wire_n111il_o;
|
and(wire_nlOlO1i_dataout, wire_nlOlOli_dataout, ~(wire_n111li_o));
|
assign wire_nlOlOiO_dataout = (nl0OliO === 1'b1) ? n10llO : wire_n111il_o;
|
or(wire_nlOlO1l_dataout, nl0OilO, wire_n111li_o);
|
assign wire_nlOlOli_dataout = (nl0OliO === 1'b1) ? n10lOi : wire_n111il_o;
|
and(wire_nlOlO1O_dataout, n10l0O, nl0OilO);
|
and(wire_nlOlOll_dataout, n10lOl, nl0OliO);
|
and(wire_nlOlOi_dataout, nli01li, ~(nli01ll));
|
and(wire_nlOlOlO_dataout, n10lOO, nl0OliO);
|
and(wire_nlOlOii_dataout, n10lli, nl0OilO);
|
and(wire_nlOlOOi_dataout, n10O1i, nl0OliO);
|
and(wire_nlOlOil_dataout, n10lll, nl0OilO);
|
and(wire_nlOlOOl_dataout, n10O1l, nl0OliO);
|
and(wire_nlOlOiO_dataout, n10llO, nl0OilO);
|
and(wire_nlOO0iO_dataout, wire_nlOOili_dataout, ~(n1i11l));
|
and(wire_nlOlOl_dataout, (~ nli01li), ~(nli01ll));
|
and(wire_nlOO0li_dataout, wire_nlOOill_dataout, ~(n1i11l));
|
and(wire_nlOlOli_dataout, n10lOi, nl0OilO);
|
and(wire_nlOO0ll_dataout, wire_nlOOilO_dataout, ~(n1i11l));
|
and(wire_nlOlOOi_dataout, ((n101li & wire_n111lO_o) | (n101iO & wire_n111Ol_o)), ~(n10OOi));
|
and(wire_nlOO0lO_dataout, wire_nlOOiOi_dataout, ~(n1i11l));
|
and(wire_nlOO00l_dataout, wire_nlOOi0O_dataout, ~(n10OOi));
|
and(wire_nlOO0Oi_dataout, wire_nlOOiOl_dataout, ~(n1i11l));
|
and(wire_nlOO00O_dataout, wire_nlOOiii_dataout, ~(n10OOi));
|
and(wire_nlOO0Ol_dataout, wire_nlOOiOO_dataout, ~(n1i11l));
|
and(wire_nlOO0ii_dataout, wire_nlOOiil_dataout, ~(n10OOi));
|
and(wire_nlOO0OO_dataout, wire_nlOOl1i_dataout, ~(n1i11l));
|
and(wire_nlOO0il_dataout, wire_nlOOiiO_dataout, ~(n10OOi));
|
and(wire_nlOO11l_dataout, ((n101Ol & wire_n1101i_o) | (n101Oi & wire_n1101O_o)), ~(n1i11l));
|
and(wire_nlOO0iO_dataout, wire_nlOOili_dataout, ~(n10OOi));
|
and(wire_nlOO1ii_dataout, wire_n1111O_dataout, ~(n1i11l));
|
and(wire_nlOO0li_dataout, wire_nlOOill_dataout, ~(n10OOi));
|
and(wire_nlOOi0i_dataout, wire_nlOOl0l_dataout, ~(n1i11l));
|
and(wire_nlOO0ll_dataout, wire_nlOOilO_dataout, ~(n10OOi));
|
and(wire_nlOOi0l_dataout, wire_nlOOl0O_dataout, ~(n1i11l));
|
and(wire_nlOO0lO_dataout, wire_nlOOiOi_dataout, ~(n10OOi));
|
and(wire_nlOOi0O_dataout, wire_nlOOlii_dataout, ~(n1i11l));
|
and(wire_nlOO0Oi_dataout, wire_nlOOiOl_dataout, ~(n10OOi));
|
and(wire_nlOOi1i_dataout, wire_nlOOl1l_dataout, ~(n1i11l));
|
and(wire_nlOO0Ol_dataout, wire_nlOOiOO_dataout, ~(n10OOi));
|
and(wire_nlOOi1l_dataout, wire_nlOOl1O_dataout, ~(n1i11l));
|
and(wire_nlOO0OO_dataout, wire_nlOOl1i_dataout, ~(n10OOi));
|
and(wire_nlOOi1O_dataout, wire_nlOOl0i_dataout, ~(n1i11l));
|
and(wire_nlOO11O_dataout, wire_nlOOOOl_dataout, ~(n10OOi));
|
and(wire_nlOOiii_dataout, wire_nlOOlil_dataout, ~(n1i11l));
|
and(wire_nlOOi0i_dataout, wire_nlOOl0l_dataout, ~(n10OOi));
|
and(wire_nlOOiil_dataout, wire_nlOOliO_dataout, ~(n1i11l));
|
and(wire_nlOOi0l_dataout, wire_nlOOl0O_dataout, ~(n10OOi));
|
and(wire_nlOOiiO_dataout, wire_nlOOlli_dataout, ~(n1i11l));
|
assign wire_nlOOi0O_dataout = (wire_nlOOOOO_o === 1'b1) ? n10l0O : nlOO11l;
|
and(wire_nlOOil_dataout, wire_nlOOiO_dataout, nlOO0l);
|
and(wire_nlOOi1i_dataout, wire_nlOOl1l_dataout, ~(n10OOi));
|
assign wire_nlOOili_dataout = (wire_n1110i_o === 1'b1) ? n10lli : nlOO10O;
|
and(wire_nlOOi1l_dataout, wire_nlOOl1O_dataout, ~(n10OOi));
|
assign wire_nlOOill_dataout = (wire_n1110i_o === 1'b1) ? n10lll : nlOO1il;
|
and(wire_nlOOi1O_dataout, wire_nlOOl0i_dataout, ~(n10OOi));
|
assign wire_nlOOilO_dataout = (wire_n1110i_o === 1'b1) ? n10llO : nlOO1iO;
|
assign wire_nlOOiii_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lii : nlOO10i;
|
or(wire_nlOOiO_dataout, wire_nlOOli_o[0], nlOOii);
|
assign wire_nlOOiil_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lil : nlOO10l;
|
assign wire_nlOOiOi_dataout = (wire_n1110i_o === 1'b1) ? n10lOi : nlOO1li;
|
assign wire_nlOOiiO_dataout = (wire_nlOOOOO_o === 1'b1) ? n10liO : nlOO10O;
|
assign wire_nlOOiOl_dataout = (wire_n1110i_o === 1'b1) ? n10lOl : nlOO1ll;
|
assign wire_nlOOili_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lli : nlOO1ii;
|
assign wire_nlOOiOO_dataout = (wire_n1110i_o === 1'b1) ? n10lOO : nlOO1lO;
|
assign wire_nlOOill_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lll : nlOO1il;
|
assign wire_nlOOl0i_dataout = (wire_n1110i_o === 1'b1) ? nlOO01i : wire_nlOOllO_dataout;
|
assign wire_nlOOilO_dataout = (wire_nlOOOOO_o === 1'b1) ? n10llO : nlOO1iO;
|
assign wire_nlOOl0l_dataout = (wire_n1110i_o === 1'b1) ? nlOO01l : wire_nlOOlOi_dataout;
|
assign wire_nlOOiOi_dataout = (wire_nlOOOOO_o === 1'b1) ? n10lOi : nlOO1li;
|
assign wire_nlOOl0O_dataout = (wire_n1110i_o === 1'b1) ? nlOO01O : wire_nlOOlOl_dataout;
|
assign wire_nlOOiOl_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1ll : wire_nlOOlii_dataout;
|
assign wire_nlOOl1i_dataout = (wire_n1110i_o === 1'b1) ? n10O1i : nlOO1Oi;
|
assign wire_nlOOiOO_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1lO : wire_nlOOlil_dataout;
|
assign wire_nlOOl1l_dataout = (wire_n1110i_o === 1'b1) ? n10O1l : nlOO1Ol;
|
assign wire_nlOOl0i_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01i : wire_nlOOllO_dataout;
|
assign wire_nlOOl1O_dataout = (wire_n1110i_o === 1'b1) ? nlOO1OO : wire_nlOOlll_dataout;
|
assign wire_nlOOl0l_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01l : wire_nlOOlOi_dataout;
|
assign wire_nlOOlii_dataout = (wire_n1110i_o === 1'b1) ? nlOO00i : wire_nlOOlOO_dataout;
|
assign wire_nlOOl0O_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO01O : wire_nlOOlOl_dataout;
|
assign wire_nlOOlil_dataout = (wire_n1110i_o === 1'b1) ? nlOO00l : wire_nlOOO1i_dataout;
|
assign wire_nlOOl1i_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1Oi : wire_nlOOliO_dataout;
|
assign wire_nlOOliO_dataout = (wire_n1110i_o === 1'b1) ? nlOO00O : wire_nlOOO1l_dataout;
|
assign wire_nlOOl1l_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1Ol : wire_nlOOlli_dataout;
|
assign wire_nlOOlli_dataout = (wire_n1110i_o === 1'b1) ? nlOO0ii : wire_nlOOO1O_dataout;
|
assign wire_nlOOl1O_dataout = (wire_nlOOOOO_o === 1'b1) ? nlOO1OO : wire_nlOOlll_dataout;
|
assign wire_nlOOlll_dataout = (wire_n1111O_dataout === 1'b1) ? n10lli : nlOO1OO;
|
assign wire_nlOOlii_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10l0O : nlOO1ll;
|
assign wire_nlOOllO_dataout = (wire_n1111O_dataout === 1'b1) ? n10lll : nlOO01i;
|
assign wire_nlOOlil_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lii : nlOO1lO;
|
assign wire_nlOOlOi_dataout = (wire_n1111O_dataout === 1'b1) ? n10llO : nlOO01l;
|
assign wire_nlOOliO_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lil : nlOO1Oi;
|
assign wire_nlOOlOl_dataout = (wire_n1111O_dataout === 1'b1) ? n10lOi : nlOO01O;
|
assign wire_nlOOlli_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10liO : nlOO1Ol;
|
assign wire_nlOOlOO_dataout = (wire_n1111O_dataout === 1'b1) ? n10lOl : nlOO00i;
|
assign wire_nlOOlll_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lli : nlOO1OO;
|
or(wire_nlOOO0l_dataout, wire_nlOOO0O_dataout, n1011O);
|
assign wire_nlOOllO_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lll : nlOO01i;
|
and(wire_nlOOO0O_dataout, nlOO0il, ~((wire_n1101i_o | wire_n1111O_dataout)));
|
assign wire_nlOOlOi_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10llO : nlOO01l;
|
assign wire_nlOOO1i_dataout = (wire_n1111O_dataout === 1'b1) ? n10lOO : nlOO00l;
|
assign wire_nlOOlOl_dataout = (wire_nlOOOOl_dataout === 1'b1) ? n10lOi : nlOO01O;
|
assign wire_nlOOO1l_dataout = (wire_n1111O_dataout === 1'b1) ? n10O1i : nlOO00O;
|
and(wire_nlOOO0O_dataout, nl0OliO, n11Oli);
|
assign wire_nlOOO1O_dataout = (wire_n1111O_dataout === 1'b1) ? n10O1l : nlOO0ii;
|
or(wire_nlOOO1i_dataout, wire_nlOOO1l_dataout, n11OOl);
|
and(wire_nlOOOli_dataout, nl0OO0O, n11OOl);
|
and(wire_nlOOO1l_dataout, nlOO00i, ~((wire_n111lO_o | wire_nlOOOOl_dataout)));
|
and(wire_nlOOOll_dataout, wire_n110OO_dataout, n101ll);
|
and(wire_nlOOOii_dataout, wire_n110ll_dataout, n101ii);
|
|
and(wire_nlOOOl_dataout, wire_nlOOOO_dataout, nlOOll);
|
|
or(wire_nlOOOO_dataout, wire_n111i_o[0], nlOOOi);
|
|
and(wire_nlOOOOl_dataout, (~ nl0OO1O), n1011i);
|
oper_add n00i1l
|
oper_add n00i1l
|
(
|
(
|
.a({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n01OOO}),
|
.a({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n0011i}),
|
.b({{6{1'b0}}, 1'b1}),
|
.b({{6{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n00i1l_o));
|
.o(wire_n00i1l_o));
|
defparam
|
defparam
|
n00i1l.sgate_representation = 0,
|
n00i1l.sgate_representation = 0,
|
n00i1l.width_a = 7,
|
n00i1l.width_a = 7,
|
n00i1l.width_b = 7,
|
n00i1l.width_b = 7,
|
n00i1l.width_o = 7;
|
n00i1l.width_o = 7;
|
|
oper_add n00ii
|
|
(
|
|
.a({n01OO, n01Ol, n00iO, 1'b1}),
|
|
.b({{2{1'b1}}, 1'b0, 1'b1}),
|
|
.cin(1'b0),
|
|
.cout(),
|
|
.o(wire_n00ii_o));
|
|
defparam
|
|
n00ii.sgate_representation = 0,
|
|
n00ii.width_a = 4,
|
|
n00ii.width_b = 4,
|
|
n00ii.width_o = 4;
|
oper_add n00O0i
|
oper_add n00O0i
|
(
|
(
|
.a({n00lOO, n001li}),
|
.a({n00lOO, n001li}),
|
.b({1'b0, 1'b1}),
|
.b({1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
| Line 9142... |
Line 9309... |
defparam
|
defparam
|
n00O0i.sgate_representation = 0,
|
n00O0i.sgate_representation = 0,
|
n00O0i.width_a = 2,
|
n00O0i.width_a = 2,
|
n00O0i.width_b = 2,
|
n00O0i.width_b = 2,
|
n00O0i.width_o = 2;
|
n00O0i.width_o = 2;
|
oper_add n01il
|
oper_add n01li
|
(
|
(
|
.a({n011i, n1OOO, n01iO, 1'b1}),
|
.a({n011O, n011l, n01ll, 1'b1}),
|
.b({{2{1'b1}}, 1'b0, 1'b1}),
|
.b({{2{1'b1}}, 1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n01il_o));
|
.o(wire_n01li_o));
|
defparam
|
defparam
|
n01il.sgate_representation = 0,
|
n01li.sgate_representation = 0,
|
n01il.width_a = 4,
|
n01li.width_a = 4,
|
n01il.width_b = 4,
|
n01li.width_b = 4,
|
n01il.width_o = 4;
|
n01li.width_o = 4;
|
oper_add n0i0ii
|
oper_add n0i0ii
|
(
|
(
|
.a({n0i01l, n0i1OO, n0i1Ol, n0i1Oi}),
|
.a({n0i01l, n0i1OO, n0i1Ol, n0i1Oi}),
|
.b({{3{1'b0}}, 1'b1}),
|
.b({{3{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
| Line 9202... |
Line 9369... |
defparam
|
defparam
|
n0iO0l.sgate_representation = 0,
|
n0iO0l.sgate_representation = 0,
|
n0iO0l.width_a = 5,
|
n0iO0l.width_a = 5,
|
n0iO0l.width_b = 5,
|
n0iO0l.width_b = 5,
|
n0iO0l.width_o = 5;
|
n0iO0l.width_o = 5;
|
oper_add n11ll
|
oper_add n100O
|
(
|
(
|
.a({n110l, n11lO, 1'b1}),
|
.a({n11OO, n10ii, 1'b1}),
|
.b({1'b1, 1'b0, 1'b1}),
|
.b({1'b1, 1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n11ll_o));
|
.o(wire_n100O_o));
|
defparam
|
defparam
|
n11ll.sgate_representation = 0,
|
n100O.sgate_representation = 0,
|
n11ll.width_a = 3,
|
n100O.width_a = 3,
|
n11ll.width_b = 3,
|
n100O.width_b = 3,
|
n11ll.width_o = 3;
|
n100O.width_o = 3;
|
oper_add n1iiO
|
oper_add n111i
|
(
|
(
|
.a({n1i0l, n1i1i, 1'b1}),
|
.a({nlOOOi}),
|
.b({1'b1, 1'b0, 1'b1}),
|
.b({1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n1iiO_o));
|
.o(wire_n111i_o));
|
defparam
|
defparam
|
n1iiO.sgate_representation = 0,
|
n111i.sgate_representation = 0,
|
n1iiO.width_a = 3,
|
n111i.width_a = 1,
|
n1iiO.width_b = 3,
|
n111i.width_b = 1,
|
n1iiO.width_o = 3;
|
n111i.width_o = 1;
|
oper_add n1lll
|
oper_add n1l0i
|
(
|
(
|
.a({n1l0l, n1l0i, n1l1O, n1l1l, 1'b1}),
|
.a({n1iOO, n1ill, 1'b1}),
|
.b({{3{1'b1}}, 1'b0, 1'b1}),
|
.b({1'b1, 1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n1lll_o));
|
.o(wire_n1l0i_o));
|
defparam
|
defparam
|
n1lll.sgate_representation = 0,
|
n1l0i.sgate_representation = 0,
|
n1lll.width_a = 5,
|
n1l0i.width_a = 3,
|
n1lll.width_b = 5,
|
n1l0i.width_b = 3,
|
n1lll.width_o = 5;
|
n1l0i.width_o = 3;
|
oper_add n1Oll
|
oper_add n1OiO
|
(
|
(
|
.a({n1O0i, n1O1O, n1OlO, 1'b1}),
|
.a({n1O1O, n1O1l, n1O1i, n1llO, 1'b1}),
|
.b({{2{1'b1}}, 1'b0, 1'b1}),
|
.b({{3{1'b1}}, 1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_n1Oll_o));
|
.o(wire_n1OiO_o));
|
defparam
|
defparam
|
n1Oll.sgate_representation = 0,
|
n1OiO.sgate_representation = 0,
|
n1Oll.width_a = 4,
|
n1OiO.width_a = 5,
|
n1Oll.width_b = 4,
|
n1OiO.width_b = 5,
|
n1Oll.width_o = 4;
|
n1OiO.width_o = 5;
|
oper_add ni01lO
|
oper_add ni01lO
|
(
|
(
|
.a({ni01ii, ni010l, ni010i, ni011l}),
|
.a({ni01ii, ni010l, ni010i, ni011l}),
|
.b({{3{1'b0}}, 1'b1}),
|
.b({{3{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
| Line 9310... |
Line 9477... |
defparam
|
defparam
|
niiO0i.sgate_representation = 0,
|
niiO0i.sgate_representation = 0,
|
niiO0i.width_a = 7,
|
niiO0i.width_a = 7,
|
niiO0i.width_b = 7,
|
niiO0i.width_b = 7,
|
niiO0i.width_o = 7;
|
niiO0i.width_o = 7;
|
oper_add nliiOOO
|
oper_add nliiOii
|
(
|
(
|
.a({nliiO0i, nliiO1O, nliiO1l, nliiO1i, nliilOO, nliiliO}),
|
.a({nliilll, nliilli, nliiliO, nliilil, nliilii, nliil1i}),
|
.b({{5{1'b0}}, 1'b1}),
|
.b({{5{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nliiOOO_o));
|
.o(wire_nliiOii_o));
|
defparam
|
defparam
|
nliiOOO.sgate_representation = 0,
|
nliiOii.sgate_representation = 0,
|
nliiOOO.width_a = 6,
|
nliiOii.width_a = 6,
|
nliiOOO.width_b = 6,
|
nliiOii.width_b = 6,
|
nliiOOO.width_o = 6;
|
nliiOii.width_o = 6;
|
oper_add nlil10i
|
oper_add nliiOll
|
(
|
(
|
.a({nliiOii, nliiO0O, nliiO0l}),
|
.a({nliilOl, nliilOi, nliillO}),
|
.b({{2{1'b0}}, 1'b1}),
|
.b({{2{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nlil10i_o));
|
.o(wire_nliiOll_o));
|
defparam
|
defparam
|
nlil10i.sgate_representation = 0,
|
nliiOll.sgate_representation = 0,
|
nlil10i.width_a = 3,
|
nliiOll.width_a = 3,
|
nlil10i.width_b = 3,
|
nliiOll.width_b = 3,
|
nlil10i.width_o = 3;
|
nliiOll.width_o = 3;
|
oper_add nlili1O
|
oper_add nlil0li
|
(
|
(
|
.a({nlil0ii, nlil00O, nlil00l, nlil00i, nlil01O, nlil1lO}),
|
.a({nlil1Ol, nlil1Oi, nlil1lO, nlil1ll, nlil1li, nlil10i}),
|
.b({{5{1'b0}}, 1'b1}),
|
.b({{5{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nlili1O_o));
|
.o(wire_nlil0li_o));
|
defparam
|
defparam
|
nlili1O.sgate_representation = 0,
|
nlil0li.sgate_representation = 0,
|
nlili1O.width_a = 6,
|
nlil0li.width_a = 6,
|
nlili1O.width_b = 6,
|
nlil0li.width_b = 6,
|
nlili1O.width_o = 6;
|
nlil0li.width_o = 6;
|
oper_add nliliii
|
oper_add nlil0Ol
|
(
|
(
|
.a({nlil0li, nlil0iO, nlil0il}),
|
.a({nlil01l, nlil01i, nlil1OO}),
|
.b({{2{1'b0}}, 1'b1}),
|
.b({{2{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nliliii_o));
|
.o(wire_nlil0Ol_o));
|
defparam
|
defparam
|
nliliii.sgate_representation = 0,
|
nlil0Ol.sgate_representation = 0,
|
nliliii.width_a = 3,
|
nlil0Ol.width_a = 3,
|
nliliii.width_b = 3,
|
nlil0Ol.width_b = 3,
|
nliliii.width_o = 3;
|
nlil0Ol.width_o = 3;
|
oper_add nll01ll
|
oper_add nll00OO
|
(
|
(
|
.a({nll100O, nll100l, nll100i, nll101O, nll101l, nll101i, nll11OO, nll11Ol, nll11Oi, nll11lO, nll11ll, nll11li, nll11iO, nll11il, nll11ii, nll110O, nll110l, nll110i, nll111O, nll111l, nliOOlO}),
|
.a({nll001i, nll01OO, nll01lO}),
|
.b({{20{1'b0}}, 1'b1}),
|
.b({{2{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nll01ll_o));
|
.o(wire_nll00OO_o));
|
defparam
|
defparam
|
nll01ll.sgate_representation = 0,
|
nll00OO.sgate_representation = 0,
|
nll01ll.width_a = 21,
|
nll00OO.width_a = 3,
|
nll01ll.width_b = 21,
|
nll00OO.width_b = 3,
|
nll01ll.width_o = 21;
|
nll00OO.width_o = 3;
|
oper_add nll0iii
|
oper_add nll010i
|
(
|
(
|
.a({nll00il, nll00ii, nll000i}),
|
.a({nll11Ol, nll11Oi, nll11lO, nll11ll, nll11li, nll11iO, nll11il, nll11ii, nll110O, nll110l, nll110i, nll111O, nll111l, nll111i, nliOOOO, nliOOOl, nliOOOi, nliOOlO, nliOOll, nliOOli, nliOO0l}),
|
.b({{2{1'b0}}, 1'b1}),
|
.b({{20{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nll0iii_o));
|
.o(wire_nll010i_o));
|
defparam
|
defparam
|
nll0iii.sgate_representation = 0,
|
nll010i.sgate_representation = 0,
|
nll0iii.width_a = 3,
|
nll010i.width_a = 21,
|
nll0iii.width_b = 3,
|
nll010i.width_b = 21,
|
nll0iii.width_o = 3;
|
nll010i.width_o = 21;
|
oper_add nlllOl
|
oper_add nllO0O
|
(
|
(
|
.a({nlll0i, nlll1O, nlll1l, nlll1i, nlliOO, nlliOl, nlliOi, nllilO}),
|
.a({nlllll, nlllli, nllliO, nlllil, nlllii, nlll0O, nlll0l, nlll0i}),
|
.b({{7{1'b0}}, 1'b1}),
|
.b({{7{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nlllOl_o));
|
.o(wire_nllO0O_o));
|
defparam
|
defparam
|
nlllOl.sgate_representation = 0,
|
nllO0O.sgate_representation = 0,
|
nlllOl.width_a = 8,
|
nllO0O.width_a = 8,
|
nlllOl.width_b = 8,
|
nllO0O.width_b = 8,
|
nlllOl.width_o = 8;
|
nllO0O.width_o = 8;
|
oper_add nllO1iO
|
oper_add nllO10l
|
(
|
(
|
.a({nlliOOi, nlliOlO, nlliOll, nlliOli, nlliOiO, nlliOil, nlliOii, nlliO0O, nlliO0l, nlliO0i, nlliO1O, nlliO1l, nlliO1i, nllilOO, nllilOl, nllilOi, nllillO, nllilll, nllilli, nlliliO, nllil0l}),
|
.a({nlliOiO, nlliOil, nlliOii, nlliO0O, nlliO0l, nlliO0i, nlliO1O, nlliO1l, nlliO1i, nllilOO, nllilOl, nllilOi, nllillO, nllilll, nllilli, nlliliO, nllilil, nllilii, nllil0O, nllil0l, nllil1i}),
|
.b({{20{1'b0}}, 1'b1}),
|
.b({{20{1'b0}}, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nllO1iO_o));
|
.o(wire_nllO10l_o));
|
defparam
|
defparam
|
nllO1iO.sgate_representation = 0,
|
nllO10l.sgate_representation = 0,
|
nllO1iO.width_a = 21,
|
nllO10l.width_a = 21,
|
nllO1iO.width_b = 21,
|
nllO10l.width_b = 21,
|
nllO1iO.width_o = 21;
|
nllO10l.width_o = 21;
|
oper_add nllOlii
|
oper_add nllOl1O
|
(
|
(
|
.a({nllOi0O, nllO01O}),
|
.a({nllOi1l, nllO1Ol}),
|
.b({1'b0, 1'b1}),
|
.b({1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nllOlii_o));
|
.o(wire_nllOl1O_o));
|
defparam
|
defparam
|
nllOlii.sgate_representation = 0,
|
nllOl1O.sgate_representation = 0,
|
nllOlii.width_a = 2,
|
nllOl1O.width_a = 2,
|
nllOlii.width_b = 2,
|
nllOl1O.width_b = 2,
|
nllOlii.width_o = 2;
|
nllOl1O.width_o = 2;
|
oper_add nllOO1l
|
oper_add nllOlOi
|
(
|
(
|
.a({nllOiil, nllOiii}),
|
.a({nllOi0i, nllOi1O}),
|
.b({1'b0, 1'b1}),
|
.b({1'b0, 1'b1}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.cout(),
|
.cout(),
|
.o(wire_nllOO1l_o));
|
.o(wire_nllOlOi_o));
|
defparam
|
defparam
|
nllOO1l.sgate_representation = 0,
|
nllOlOi.sgate_representation = 0,
|
nllOO1l.width_a = 2,
|
nllOlOi.width_a = 2,
|
nllOO1l.width_b = 2,
|
nllOlOi.width_b = 2,
|
nllOO1l.width_o = 2;
|
nllOlOi.width_o = 2;
|
oper_add nlOOli
|
oper_decoder n010Oi
|
(
|
(
|
.a({nlOOii}),
|
.i({n010li}),
|
.b({1'b1}),
|
.o(wire_n010Oi_o));
|
.cin(1'b0),
|
|
.cout(),
|
|
.o(wire_nlOOli_o));
|
|
defparam
|
defparam
|
nlOOli.sgate_representation = 0,
|
n010Oi.width_i = 1,
|
nlOOli.width_a = 1,
|
n010Oi.width_o = 2;
|
nlOOli.width_b = 1,
|
|
nlOOli.width_o = 1;
|
|
oper_decoder n01iil
|
|
(
|
|
.i({n01i0l}),
|
|
.o(wire_n01iil_o));
|
|
defparam
|
|
n01iil.width_i = 1,
|
|
n01iil.width_o = 2;
|
|
oper_decoder n0lilO
|
oper_decoder n0lilO
|
(
|
(
|
.i({n0lili}),
|
.i({n0lili}),
|
.o(wire_n0lilO_o));
|
.o(wire_n0lilO_o));
|
defparam
|
defparam
|
| Line 9473... |
Line 9628... |
niOi0O.width_i = 1,
|
niOi0O.width_i = 1,
|
niOi0O.width_o = 2;
|
niOi0O.width_o = 2;
|
oper_less_than n00i1O
|
oper_less_than n00i1O
|
(
|
(
|
.a({{3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1}),
|
.a({{3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1}),
|
.b({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n01OOO}),
|
.b({n001iO, n001il, n001ii, n0010O, n0010l, n0010i, n0011i}),
|
.cin(1'b1),
|
.cin(1'b1),
|
.o(wire_n00i1O_o));
|
.o(wire_n00i1O_o));
|
defparam
|
defparam
|
n00i1O.sgate_representation = 0,
|
n00i1O.sgate_representation = 0,
|
n00i1O.width_a = 7,
|
n00i1O.width_a = 7,
|
| Line 9570... |
Line 9725... |
.o(wire_niiO0l_o));
|
.o(wire_niiO0l_o));
|
defparam
|
defparam
|
niiO0l.sgate_representation = 0,
|
niiO0l.sgate_representation = 0,
|
niiO0l.width_a = 7,
|
niiO0l.width_a = 7,
|
niiO0l.width_b = 7;
|
niiO0l.width_b = 7;
|
oper_less_than nllill
|
oper_less_than nlll1O
|
(
|
(
|
.a({{5{1'b0}}, 1'b1, {2{1'b0}}}),
|
.a({{5{1'b0}}, 1'b1, {2{1'b0}}}),
|
.b({nlll0i, nlll1O, nlll1l, nlll1i, nlliOO, nlliOl, nlliOi, nllilO}),
|
.b({nlllll, nlllli, nllliO, nlllil, nlllii, nlll0O, nlll0l, nlll0i}),
|
.cin(1'b0),
|
.cin(1'b0),
|
.o(wire_nllill_o));
|
.o(wire_nlll1O_o));
|
defparam
|
defparam
|
nllill.sgate_representation = 0,
|
nlll1O.sgate_representation = 0,
|
nllill.width_a = 8,
|
nlll1O.width_a = 8,
|
nllill.width_b = 8;
|
nlll1O.width_b = 8;
|
oper_mux nl100i
|
oper_mux nl100i
|
(
|
(
|
.data({{11{1'b0}}, nl00Oi, nl0lil, nl0i0i, 1'b0, nl0O1l, {9{1'b0}}, nli10l, nl1i0l, {5{1'b0}}}),
|
.data({{11{1'b0}}, nl00Oi, nl0lil, nl0i0i, 1'b0, nl0O1l, {9{1'b0}}, nli10l, nl1i0l, {5{1'b0}}}),
|
.o(wire_nl100i_o),
|
.o(wire_nl100i_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl100i.width_data = 32,
|
nl100i.width_data = 32,
|
nl100i.width_sel = 5;
|
nl100i.width_sel = 5;
|
oper_mux nl100l
|
oper_mux nl100l
|
(
|
(
|
.data({{11{1'b0}}, nl00Ol, nl0liO, nl0i0O, 1'b0, nl0O1O, {10{1'b0}}, nl1i0O, {3{1'b0}}, nlil0i, 1'b0}),
|
.data({{11{1'b0}}, nl00Ol, nl0liO, nl0i0O, 1'b0, nl0O1O, {10{1'b0}}, nl1i0O, {3{1'b0}}, nlil0i, 1'b0}),
|
.o(wire_nl100l_o),
|
.o(wire_nl100l_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl100l.width_data = 32,
|
nl100l.width_data = 32,
|
nl100l.width_sel = 5;
|
nl100l.width_sel = 5;
|
oper_mux nl100O
|
oper_mux nl100O
|
(
|
(
|
.data({{11{1'b0}}, nl00OO, nl0lll, nl0iii, 1'b0, nl0O0i, {10{1'b0}}, nl1iii, {3{1'b0}}, 1'b1, 1'b0}),
|
.data({{11{1'b0}}, nl00OO, nl0lll, nl0iii, 1'b0, nl0O0i, {10{1'b0}}, nl1iii, {3{1'b0}}, 1'b1, 1'b0}),
|
.o(wire_nl100O_o),
|
.o(wire_nl100O_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl100O.width_data = 32,
|
nl100O.width_data = 32,
|
nl100O.width_sel = 5;
|
nl100O.width_sel = 5;
|
oper_mux nl101O
|
oper_mux nl101O
|
(
|
(
|
.data({{9{1'b0}}, nl010l, nl00ii, nl00ll, nl0lii, 1'b0, 1'b1, nl0lOl, {9{1'b0}}, nli11O, nl111i, {3{1'b0}}, 1'b1, 1'b0}),
|
.data({{9{1'b0}}, nl010l, nl00ii, nl00ll, nl0lii, {2{1'b0}}, nl0lOl, {9{1'b0}}, nli11O, nl111i, {3{1'b0}}, 1'b1, 1'b0}),
|
.o(wire_nl101O_o),
|
.o(wire_nl101O_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl101O.width_data = 32,
|
nl101O.width_data = 32,
|
nl101O.width_sel = 5;
|
nl101O.width_sel = 5;
|
oper_mux nl10ii
|
oper_mux nl10ii
|
(
|
(
|
.data({{11{1'b0}}, nl0i1i, nl0lOi, nl0iil, 1'b0, nl0O0l, {10{1'b0}}, nl1iil, {5{1'b0}}}),
|
.data({{11{1'b0}}, nl0i1i, nl0lOi, nl0iil, 1'b0, nl0O0l, {10{1'b0}}, nl1iil, {5{1'b0}}}),
|
.o(wire_nl10ii_o),
|
.o(wire_nl10ii_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10ii.width_data = 32,
|
nl10ii.width_data = 32,
|
nl10ii.width_sel = 5;
|
nl10ii.width_sel = 5;
|
oper_mux nl10il
|
oper_mux nl10il
|
(
|
(
|
.data({{11{1'b0}}, nl0i1O, 1'b0, nl0iiO, 1'b0, nl0O0O, {10{1'b0}}, nl1iiO, nlii0i, {2{1'b0}}, nlil0O, 1'b0}),
|
.data({{11{1'b0}}, nl0i1O, 1'b0, nl0iiO, 1'b0, nl0O0O, {10{1'b0}}, nl1iiO, nlii0i, {2{1'b0}}, nlil0O, nliOiO}),
|
.o(wire_nl10il_o),
|
.o(wire_nl10il_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10il.width_data = 32,
|
nl10il.width_data = 32,
|
nl10il.width_sel = 5;
|
nl10il.width_sel = 5;
|
oper_mux nl10iO
|
oper_mux nl10iO
|
(
|
(
|
.data({{13{1'b0}}, nl0ili, 1'b0, nl0Oii, {10{1'b0}}, nl1ili, nliill, {3{1'b0}}, 1'b1}),
|
.data({{13{1'b0}}, nl0ili, 1'b0, nl0Oii, {10{1'b0}}, nl1ili, nliill, {3{1'b0}}, 1'b1}),
|
.o(wire_nl10iO_o),
|
.o(wire_nl10iO_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10iO.width_data = 32,
|
nl10iO.width_data = 32,
|
nl10iO.width_sel = 5;
|
nl10iO.width_sel = 5;
|
oper_mux nl10li
|
oper_mux nl10li
|
(
|
(
|
.data({{13{1'b0}}, nl0ill, 1'b0, nl0Oil, {10{1'b0}}, nl1ill, nliilO, {4{1'b0}}}),
|
.data({{13{1'b0}}, nl0ill, 1'b0, nl0Oil, {10{1'b0}}, nl1ill, nliilO, {2{1'b0}}, 1'b1, 1'b0}),
|
.o(wire_nl10li_o),
|
.o(wire_nl10li_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10li.width_data = 32,
|
nl10li.width_data = 32,
|
nl10li.width_sel = 5;
|
nl10li.width_sel = 5;
|
oper_mux nl10ll
|
oper_mux nl10ll
|
(
|
(
|
.data({{13{1'b0}}, nl0ilO, 1'b1, nl0OiO, {10{1'b0}}, nl1ilO, nliiOl, {3{1'b0}}, 1'b1}),
|
.data({{13{1'b0}}, nl0ilO, 1'b0, nl0OiO, {10{1'b0}}, nl1ilO, nliiOl, {3{1'b0}}, 1'b1}),
|
.o(wire_nl10ll_o),
|
.o(wire_nl10ll_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10ll.width_data = 32,
|
nl10ll.width_data = 32,
|
nl10ll.width_sel = 5;
|
nl10ll.width_sel = 5;
|
oper_mux nl10lO
|
oper_mux nl10lO
|
(
|
(
|
.data({{13{1'b0}}, nl0iOi, 1'b1, nl0Oli, {10{1'b0}}, nl1iOi, {4{1'b0}}, nliOil}),
|
.data({{13{1'b0}}, nl0iOi, 1'b0, nl0Oli, {10{1'b0}}, nl1iOi, {4{1'b0}}, nll11i}),
|
.o(wire_nl10lO_o),
|
.o(wire_nl10lO_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10lO.width_data = 32,
|
nl10lO.width_data = 32,
|
nl10lO.width_sel = 5;
|
nl10lO.width_sel = 5;
|
oper_mux nl10Oi
|
oper_mux nl10Oi
|
(
|
(
|
.data({{13{1'b0}}, nl0iOl, 1'b0, nl0Oll, {10{1'b0}}, nl1iOl, {4{1'b0}}, nliOli}),
|
.data({{13{1'b0}}, nl0iOl, 1'b1, nl0Oll, {10{1'b0}}, nl1iOl, {4{1'b0}}, nll11l}),
|
.o(wire_nl10Oi_o),
|
.o(wire_nl10Oi_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10Oi.width_data = 32,
|
nl10Oi.width_data = 32,
|
nl10Oi.width_sel = 5;
|
nl10Oi.width_sel = 5;
|
oper_mux nl10Ol
|
oper_mux nl10Ol
|
(
|
(
|
.data({{13{1'b0}}, nl0iOO, 1'b1, nl0OlO, {10{1'b0}}, nl1iOO, {4{1'b0}}, nliOll}),
|
.data({{13{1'b0}}, nl0iOO, 1'b1, nl0OlO, {10{1'b0}}, nl1iOO, {4{1'b0}}, nll11O}),
|
.o(wire_nl10Ol_o),
|
.o(wire_nl10Ol_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10Ol.width_data = 32,
|
nl10Ol.width_data = 32,
|
nl10Ol.width_sel = 5;
|
nl10Ol.width_sel = 5;
|
oper_mux nl10OO
|
oper_mux nl10OO
|
(
|
(
|
.data({{13{1'b0}}, nl0l1l, 1'b0, nl0OOi, {10{1'b0}}, nl1l1i, nliiOO, {3{1'b0}}, nliOOi}),
|
.data({{13{1'b0}}, nl0l1l, 1'b0, nl0OOi, {10{1'b0}}, nl1l1i, nliiOO, {3{1'b0}}, nll10l}),
|
.o(wire_nl10OO_o),
|
.o(wire_nl10OO_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl10OO.width_data = 32,
|
nl10OO.width_data = 32,
|
nl10OO.width_sel = 5;
|
nl10OO.width_sel = 5;
|
oper_mux nl1i1i
|
oper_mux nl1i1i
|
(
|
(
|
.data({{13{1'b0}}, nl0l1O, 1'b0, nl0OOl, {10{1'b0}}, nl1l1l, nlil1l, {4{1'b0}}}),
|
.data({{13{1'b0}}, nl0l1O, 1'b0, nl0OOl, {10{1'b0}}, nl1l1l, nlil1l, {4{1'b0}}}),
|
.o(wire_nl1i1i_o),
|
.o(wire_nl1i1i_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl1i1i.width_data = 32,
|
nl1i1i.width_data = 32,
|
nl1i1i.width_sel = 5;
|
nl1i1i.width_sel = 5;
|
oper_mux nl1i1l
|
oper_mux nl1i1l
|
(
|
(
|
.data({{13{1'b0}}, nl0l0i, 1'b0, nl0OOO, {10{1'b0}}, nl1l1O, nlil1O, {3{1'b0}}, nliOOO}),
|
.data({{13{1'b0}}, nl0l0i, 1'b0, nl0OOO, {10{1'b0}}, nl1l1O, nlil1O, {3{1'b0}}, nll1ii}),
|
.o(wire_nl1i1l_o),
|
.o(wire_nl1i1l_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl1i1l.width_data = 32,
|
nl1i1l.width_data = 32,
|
nl1i1l.width_sel = 5;
|
nl1i1l.width_sel = 5;
|
oper_mux nl1i1O
|
oper_mux nl1i1O
|
(
|
(
|
.data({{13{1'b0}}, nl0l0O, 1'b0, nli11l, {10{1'b0}}, nl1l0l, {4{1'b0}}, nll11i}),
|
.data({{13{1'b0}}, nl0l0O, 1'b0, nli11l, {10{1'b0}}, nl1l0l, {4{1'b0}}, nll1il}),
|
.o(wire_nl1i1O_o),
|
.o(wire_nl1i1O_o),
|
.sel({nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O}));
|
.sel({nlO1Ol, nlO1Oi, nlO1lO, nlO1ll, nlO1li}));
|
defparam
|
defparam
|
nl1i1O.width_data = 32,
|
nl1i1O.width_data = 32,
|
nl1i1O.width_sel = 5;
|
nl1i1O.width_sel = 5;
|
oper_selector n00ill
|
oper_selector n00ill
|
(
|
(
|
| Line 9726... |
Line 9881... |
defparam
|
defparam
|
n00iOi.width_data = 3,
|
n00iOi.width_data = 3,
|
n00iOi.width_sel = 3;
|
n00iOi.width_sel = 3;
|
oper_selector n00iOO
|
oper_selector n00iOO
|
(
|
(
|
.data({wire_n00lil_dataout, (~ nli1i0l), 1'b0}),
|
.data({wire_n00lil_dataout, (~ nli10il), 1'b0}),
|
.o(wire_n00iOO_o),
|
.o(wire_n00iOO_o),
|
.sel({n00Oii, n00O0O, (n00O0l | n00O1i)}));
|
.sel({n00Oii, n00O0O, (n00O0l | n00O1i)}));
|
defparam
|
defparam
|
n00iOO.width_data = 3,
|
n00iOO.width_data = 3,
|
n00iOO.width_sel = 3;
|
n00iOO.width_sel = 3;
|
oper_selector n00l1l
|
oper_selector n00l1l
|
(
|
(
|
.data({wire_n00liO_dataout, nli1i0l, 1'b0, nli1i0i}),
|
.data({wire_n00liO_dataout, nli10il, 1'b0, nli10ii}),
|
.o(wire_n00l1l_o),
|
.o(wire_n00l1l_o),
|
.sel({n00Oii, n00O0O, n00O1i, n00O0l}));
|
.sel({n00Oii, n00O0O, n00O1i, n00O0l}));
|
defparam
|
defparam
|
n00l1l.width_data = 4,
|
n00l1l.width_data = 4,
|
n00l1l.width_sel = 4;
|
n00l1l.width_sel = 4;
|
oper_selector n1100l
|
|
(
|
|
.data({(~ nl0OOOl), 1'b0, wire_n11l1i_dataout, 1'b1}),
|
|
.o(wire_n1100l_o),
|
|
.sel({n101OO, nl0OO0l, n1011O, n1011l}));
|
|
defparam
|
|
n1100l.width_data = 4,
|
|
n1100l.width_sel = 4;
|
|
oper_selector n1101i
|
oper_selector n1101i
|
(
|
(
|
.data({nl0OOOl, 1'b0, wire_n11lil_dataout, wire_n11l0i_dataout, {2{nl0OOOl}}, nli111l, {2{nl0OOOl}}}),
|
.data({(~ nl0OO1l), 1'b0, wire_n11ilO_dataout, 1'b1}),
|
.o(wire_n1101i_o),
|
.o(wire_n1101i_o),
|
.sel({n101OO, nl0OO1O, n101Ol, n1010i, n101il, n1011O, n101iO, n11OOO, nlOOO0i}));
|
.sel({n101ll, nl0Olil, n11OOl, n11OOi}));
|
defparam
|
|
n1101i.width_data = 9,
|
|
n1101i.width_sel = 9;
|
|
oper_selector n1101O
|
|
(
|
|
.data({1'b0, wire_n11OiO_dataout, 1'b0, (~ nli11li)}),
|
|
.o(wire_n1101O_o),
|
|
.sel({nl0OO0i, n101Oi, n101Ol, n101ii}));
|
|
defparam
|
defparam
|
n1101O.width_data = 4,
|
n1101i.width_data = 4,
|
n1101O.width_sel = 4;
|
n1101i.width_sel = 4;
|
oper_selector n1110i
|
oper_selector n1110i
|
(
|
(
|
.data({(~ nl0OOOO), 1'b0}),
|
.data({1'b0, wire_n11l1O_dataout, (~ nl0OO1l)}),
|
.o(wire_n1110i_o),
|
.o(wire_n1110i_o),
|
.sel({n1010O, (~ n1010O)}));
|
.sel({nl0Ol1O, n101li, n1010i}));
|
defparam
|
defparam
|
n1110i.width_data = 2,
|
n1110i.width_data = 3,
|
n1110i.width_sel = 2;
|
n1110i.width_sel = 3;
|
oper_selector n1110l
|
|
(
|
|
.data({1'b0, nli11li, 1'b0, nli11li}),
|
|
.o(wire_n1110l_o),
|
|
.sel({nl0OlOl, n101Oi, n1010O, n101ii}));
|
|
defparam
|
|
n1110l.width_data = 4,
|
|
n1110l.width_sel = 4;
|
|
oper_selector n1111i
|
oper_selector n1111i
|
(
|
(
|
.data({1'b0, wire_n11Oil_dataout, wire_n11l0O_dataout, {2{nl0OOOO}}, wire_n11l1O_dataout, wire_n11iOO_dataout}),
|
.data({1'b0, nl0OOOi, 1'b0, nl0OOOi}),
|
.o(wire_n1111i_o),
|
.o(wire_n1111i_o),
|
.sel({nl0OlOi, n101Oi, n101Ol, n1010O, n1010l, n1010i, n1011O}));
|
.sel({nl0Ol1l, n101iO, n1011l, n1011O}));
|
defparam
|
defparam
|
n1111i.width_data = 7,
|
n1111i.width_data = 4,
|
n1111i.width_sel = 7;
|
n1111i.width_sel = 4;
|
oper_selector n111il
|
oper_selector n111il
|
(
|
(
|
.data({1'b0, wire_n11lii_dataout, (~ nl0OOOl)}),
|
.data({1'b0, 1'b1, wire_n110Ol_dataout, (~ nl0OliO), wire_n110li_dataout, (~ nl0OliO), wire_n1100i_dataout, {2{(~ nl0OliO)}}}),
|
.o(wire_n111il_o),
|
.o(wire_n111il_o),
|
.sel({nl0OlOO, n101Ol, n101il}));
|
.sel({nl0Ol0i, n101il, n101ii, n1010O, n1010l, n11OlO, n11Oll, n11Oli, n11OiO}));
|
|
defparam
|
|
n111il.width_data = 9,
|
|
n111il.width_sel = 9;
|
|
oper_selector n111li
|
|
(
|
|
.data({1'b0, nl0OOiO, wire_n1100l_dataout}),
|
|
.o(wire_n111li_o),
|
|
.sel({nl0Ol0l, n101li, n11Oll}));
|
defparam
|
defparam
|
n111il.width_data = 3,
|
n111li.width_data = 3,
|
n111il.width_sel = 3;
|
n111li.width_sel = 3;
|
oper_selector n111lO
|
oper_selector n111lO
|
(
|
(
|
.data({1'b0, 1'b1, wire_n11i1O_dataout, (~ nl0OO0O), wire_n110Ol_dataout, (~ nl0OO0O), wire_n110il_dataout, {2{(~ nl0OO0O)}}}),
|
.data({nl0OO1l, 1'b0, wire_n11l0i_dataout, wire_n11iOO_dataout, {2{nl0OO1l}}, nl0OO0l, {2{nl0OO1l}}}),
|
.o(wire_n111lO_o),
|
.o(wire_n111lO_o),
|
.sel({nl0OO1i, n101lO, n101ll, n101li, n101iO, n1011i, n11OOO, n11OOl, n11OOi}));
|
.sel({n101ll, nl0Ol0O, n101li, n11OOO, n1010i, n11OOl, n1010l, n11Oll, nlOOlOO}));
|
defparam
|
defparam
|
n111lO.width_data = 9,
|
n111lO.width_data = 9,
|
n111lO.width_sel = 9;
|
n111lO.width_sel = 9;
|
oper_selector n111Ol
|
oper_selector n111Ol
|
(
|
(
|
.data({1'b0, nli110O, wire_n110iO_dataout}),
|
.data({1'b0, wire_n11O0l_dataout, 1'b0, (~ nl0OOOi)}),
|
.o(wire_n111Ol_o),
|
.o(wire_n111Ol_o),
|
.sel({nl0OO1l, n101Ol, n11OOO}));
|
.sel({nl0Olii, n101iO, n101li, n1011O}));
|
defparam
|
defparam
|
n111Ol.width_data = 3,
|
n111Ol.width_data = 4,
|
n111Ol.width_sel = 3;
|
n111Ol.width_sel = 4;
|
oper_selector n1Oili
|
oper_selector n1Oi0O
|
(
|
(
|
.data({nli10lO, 1'b0, nli10ii}),
|
.data({nli11Oi, 1'b0, nli11iO}),
|
.o(wire_n1Oili_o),
|
.o(wire_n1Oi0O_o),
|
.sel({n0101O, nli101i, n1i0Ol}));
|
.sel({n011il, nli110i, n1i0li}));
|
defparam
|
defparam
|
n1Oili.width_data = 3,
|
n1Oi0O.width_data = 3,
|
n1Oili.width_sel = 3;
|
n1Oi0O.width_sel = 3;
|
oper_selector n1OiOi
|
oper_selector n1OiiO
|
(
|
(
|
.data({wire_n1OO0O_dataout, 1'b0, wire_n1OlOi_dataout, wire_n1Olii_dataout}),
|
.data({wire_n1Olll_dataout, 1'b0, {2{wire_n1Ol1O_dataout}}}),
|
.o(wire_n1OiOi_o),
|
.o(wire_n1OiiO_o),
|
.sel({n0101O, nli101O, n011ii, n1i0Ol}));
|
.sel({n011il, nli110O, n1OOlO, n1i0li}));
|
defparam
|
defparam
|
n1OiOi.width_data = 4,
|
n1OiiO.width_data = 4,
|
n1OiOi.width_sel = 4;
|
n1OiiO.width_sel = 4;
|
oper_selector n1OiOO
|
oper_selector n1Oill
|
(
|
(
|
.data({1'b0, 1'b1, (~ nli10il)}),
|
.data({1'b0, 1'b1, (~ nli11li)}),
|
.o(wire_n1OiOO_o),
|
.o(wire_n1Oill_o),
|
.sel({nli101l, (n0101l | n011lO), n0101i}));
|
.sel({nli110l, (n011ii | n0111l), n0110O}));
|
defparam
|
defparam
|
n1OiOO.width_data = 3,
|
n1Oill.width_data = 3,
|
n1OiOO.width_sel = 3;
|
n1Oill.width_sel = 3;
|
oper_selector n1Ol0l
|
oper_selector n1OiOl
|
(
|
(
|
.data({wire_n1OOil_dataout, 1'b0, (~ n1i1lO), 1'b1, wire_n1OlOO_dataout, wire_n1OliO_dataout}),
|
.data({wire_n1OllO_dataout, 1'b0, {2{wire_n1Ol0i_dataout}}}),
|
.o(wire_n1Ol0l_o),
|
.o(wire_n1OiOl_o),
|
.sel({n0101O, nli100i, n011Ol, n011ll, n011ii, n1i0Ol}));
|
.sel({n011il, nli110O, n1OOlO, n1i0li}));
|
defparam
|
defparam
|
n1Ol0l.width_data = 6,
|
n1OiOl.width_data = 4,
|
n1Ol0l.width_sel = 6;
|
n1OiOl.width_sel = 4;
|
oper_selector n1Ol1O
|
oper_selector n1Ol1i
|
(
|
(
|
.data({wire_n1OOii_dataout, 1'b0, wire_n1OlOl_dataout, wire_n1Olil_dataout}),
|
.data({wire_n1OlOi_dataout, 1'b0, (~ n1i1il), 1'b1, {2{wire_n1Ol0l_dataout}}}),
|
.o(wire_n1Ol1O_o),
|
.o(wire_n1Ol1i_o),
|
.sel({n0101O, nli101O, n011ii, n1i0Ol}));
|
.sel({n011il, nli11ii, n0110i, n0111i, n1OOlO, n1i0li}));
|
defparam
|
defparam
|
n1Ol1O.width_data = 4,
|
n1Ol1i.width_data = 6,
|
n1Ol1O.width_sel = 4;
|
n1Ol1i.width_sel = 6;
|
oper_selector ni101l
|
oper_selector ni101l
|
(
|
(
|
.data({wire_ni10iO_dataout, 1'b0, nliilOi}),
|
.data({wire_ni10iO_dataout, 1'b0, nliil0l}),
|
.o(wire_ni101l_o),
|
.o(wire_ni101l_o),
|
.sel({ni1i1l, nli1iOl, n0OOli}));
|
.sel({ni1i1l, nli1i1l, n0OOli}));
|
defparam
|
defparam
|
ni101l.width_data = 3,
|
ni101l.width_data = 3,
|
ni101l.width_sel = 3;
|
ni101l.width_sel = 3;
|
oper_selector ni11lO
|
oper_selector ni11lO
|
(
|
(
|
.data({1'b0, nli1l1i, nli1iOO, (~ nliilOi)}),
|
.data({1'b0, nli1i0i, nli1i1O, (~ nliil0l)}),
|
.o(wire_ni11lO_o),
|
.o(wire_ni11lO_o),
|
.sel({ni1i1l, ni10OO, ni10Ol, n0OOli}));
|
.sel({ni1i1l, ni10OO, ni10Ol, n0OOli}));
|
defparam
|
defparam
|
ni11lO.width_data = 4,
|
ni11lO.width_data = 4,
|
ni11lO.width_sel = 4;
|
ni11lO.width_sel = 4;
|
oper_selector ni11Oi
|
oper_selector ni11Oi
|
(
|
(
|
.data({wire_ni10il_dataout, 1'b0, (~ nli1iOO)}),
|
.data({wire_ni10il_dataout, 1'b0, (~ nli1i1O)}),
|
.o(wire_ni11Oi_o),
|
.o(wire_ni11Oi_o),
|
.sel({ni1i1l, nli1iOi, ni10Ol}));
|
.sel({ni1i1l, nli1i1i, ni10Ol}));
|
defparam
|
defparam
|
ni11Oi.width_data = 3,
|
ni11Oi.width_data = 3,
|
ni11Oi.width_sel = 3;
|
ni11Oi.width_sel = 3;
|
oper_selector ni11OO
|
oper_selector ni11OO
|
(
|
(
|
.data({nli1l1O, (~ nli1l1i), 1'b0}),
|
.data({nli1i0O, (~ nli1i0i), 1'b0}),
|
.o(wire_ni11OO_o),
|
.o(wire_ni11OO_o),
|
.sel({ni1i1l, ni10OO, (ni10Ol | n0OOli)}));
|
.sel({ni1i1l, ni10OO, (ni10Ol | n0OOli)}));
|
defparam
|
defparam
|
ni11OO.width_data = 3,
|
ni11OO.width_data = 3,
|
ni11OO.width_sel = 3;
|
ni11OO.width_sel = 3;
|
| Line 9902... |
Line 10041... |
defparam
|
defparam
|
niiOOO.width_data = 3,
|
niiOOO.width_data = 3,
|
niiOOO.width_sel = 3;
|
niiOOO.width_sel = 3;
|
oper_selector nil10i
|
oper_selector nil10i
|
(
|
(
|
.data({wire_nil1li_dataout, nli1lll, 1'b0, nli1lli}),
|
.data({wire_nil1li_dataout, nli1iOl, 1'b0, nli1iOi}),
|
.o(wire_nil10i_o),
|
.o(wire_nil10i_o),
|
.sel({nil01i, nil1OO, niiilO, nil1Ol}));
|
.sel({nil01i, nil1OO, niiilO, nil1Ol}));
|
defparam
|
defparam
|
nil10i.width_data = 4,
|
nil10i.width_data = 4,
|
nil10i.width_sel = 4;
|
nil10i.width_sel = 4;
|
oper_selector nil11l
|
oper_selector nil11l
|
(
|
(
|
.data({nli1lOi, (~ nli1lll), 1'b0}),
|
.data({nli1l1i, (~ nli1iOl), 1'b0}),
|
.o(wire_nil11l_o),
|
.o(wire_nil11l_o),
|
.sel({nil01i, nil1OO, (nil1Ol | niiilO)}));
|
.sel({nil01i, nil1OO, (nil1Ol | niiilO)}));
|
defparam
|
defparam
|
nil11l.width_data = 3,
|
nil11l.width_data = 3,
|
nil11l.width_sel = 3;
|
nil11l.width_sel = 3;
|
oper_selector nlO0lO
|
oper_selector nlO0lli
|
(
|
(
|
.data({wire_nlOiiO_dataout, (~ nli000i), 1'b0}),
|
.data({1'b0, (~ wire_nlili0O_dout)}),
|
.o(wire_nlO0lO_o),
|
.o(wire_nlO0lli_o),
|
.sel({nlOO0l, nlO0li, (((nlOO1O | nlOO1l) | nlOO1i) | nlOlOO)}));
|
.sel({nl0O0iO, (~ nl0O0iO)}));
|
|
defparam
|
|
nlO0lli.width_data = 2,
|
|
nlO0lli.width_sel = 2;
|
|
oper_selector nlO0llO
|
|
(
|
|
.data({1'b0, nl0Oi1i, (~ nllO1Oi)}),
|
|
.o(wire_nlO0llO_o),
|
|
.sel({nl0O0li, nlOi1lO, nlOi1ll}));
|
defparam
|
defparam
|
nlO0lO.width_data = 3,
|
nlO0llO.width_data = 3,
|
nlO0lO.width_sel = 3;
|
nlO0llO.width_sel = 3;
|
oper_selector nlO0lOl
|
oper_selector nlO0lOl
|
(
|
(
|
.data({1'b0, (~ wire_nliliOl_dout)}),
|
.data({1'b0, nl0Oi1l, wire_nlO0Oll_dataout}),
|
.o(wire_nlO0lOl_o),
|
.o(wire_nlO0lOl_o),
|
.sel({nl0Oi0O, (~ nl0Oi0O)}));
|
.sel({nl0O0ll, nlOi1Oi, nlOi1lO}));
|
defparam
|
defparam
|
nlO0lOl.width_data = 2,
|
nlO0lOl.width_data = 3,
|
nlO0lOl.width_sel = 2;
|
nlO0lOl.width_sel = 3;
|
oper_selector nlO0O0l
|
oper_selector nlO0O0l
|
(
|
(
|
.data({1'b0, nl0Ol1l, wire_nlOi11O_dataout}),
|
.data({1'b0, nll0lll, (~ nl0Oi0O)}),
|
.o(wire_nlO0O0l_o),
|
.o(wire_nlO0O0l_o),
|
.sel({nl0OiiO, nlOi01O, nlOi01l}));
|
.sel({nl0O0Ol, nlOi01i, nlOi1OO}));
|
defparam
|
defparam
|
nlO0O0l.width_data = 3,
|
nlO0O0l.width_data = 3,
|
nlO0O0l.width_sel = 3;
|
nlO0O0l.width_sel = 3;
|
oper_selector nlO0O1i
|
oper_selector nlO0O1i
|
(
|
(
|
.data({1'b0, nl0OiOi, (~ nllO01l)}),
|
.data({1'b0, nl0Oi0l, wire_nlO0OOl_dataout}),
|
.o(wire_nlO0O1i_o),
|
.o(wire_nlO0O1i_o),
|
.sel({nl0Oiii, nlOi01i, nlOi1OO}));
|
.sel({nl0O0lO, nlOi1Ol, nlOi1Oi}));
|
defparam
|
defparam
|
nlO0O1i.width_data = 3,
|
nlO0O1i.width_data = 3,
|
nlO0O1i.width_sel = 3;
|
nlO0O1i.width_sel = 3;
|
oper_selector nlO0O1O
|
oper_selector nlO0O1O
|
(
|
(
|
.data({1'b0, nl0OiOl, wire_nlO0OOO_dataout}),
|
.data({1'b0, nl0Oi0O, wire_nlOi11O_dataout}),
|
.o(wire_nlO0O1O_o),
|
.o(wire_nlO0O1O_o),
|
.sel({nl0Oiil, nlOi01l, nlOi01i}));
|
.sel({nl0O0Oi, nlOi1OO, nlOi1Ol}));
|
defparam
|
defparam
|
nlO0O1O.width_data = 3,
|
nlO0O1O.width_data = 3,
|
nlO0O1O.width_sel = 3;
|
nlO0O1O.width_sel = 3;
|
oper_selector nlO0Oii
|
oper_selector nlO0Oii
|
(
|
(
|
.data({1'b0, nl0Ol1O, wire_nlOi1ii_dataout}),
|
.data({wire_nlili0O_dout, (~ nll0lll), 1'b0}),
|
.o(wire_nlO0Oii_o),
|
.o(wire_nlO0Oii_o),
|
.sel({nl0Oili, nlOi00i, nlOi01O}));
|
.sel({nlOi01l, nlOi01i, nl0O0OO}));
|
defparam
|
defparam
|
nlO0Oii.width_data = 3,
|
nlO0Oii.width_data = 3,
|
nlO0Oii.width_sel = 3;
|
nlO0Oii.width_sel = 3;
|
oper_selector nlO0OiO
|
oper_selector nlO0OiO
|
(
|
(
|
.data({1'b0, nll0lOO, (~ nl0Ol1O)}),
|
.data({1'b0, wire_nlOi10i_dataout, wire_nlO0OOO_dataout, wire_nlO0OlO_dataout, nllO1Oi, wire_nlili0O_dout}),
|
.o(wire_nlO0OiO_o),
|
.o(wire_nlO0OiO_o),
|
.sel({nl0Oill, nlOi00l, nlOi00i}));
|
.sel({((nlOi01l | nlOi01i) | nlOi1OO), nlOi1Ol, nlOi1Oi, nlOi1lO, nlOi1ll, nlO101l}));
|
defparam
|
defparam
|
nlO0OiO.width_data = 3,
|
nlO0OiO.width_data = 6,
|
nlO0OiO.width_sel = 3;
|
nlO0OiO.width_sel = 6;
|
oper_selector nlO0Ol
|
oper_selector nlOi0i
|
(
|
(
|
.data({wire_nlOili_dataout, 1'b0, (~ nli001O)}),
|
.data({wire_nlOl1i_dataout, (~ nli01iO), 1'b0}),
|
.o(wire_nlO0Ol_o),
|
.o(wire_nlOi0i_o),
|
.sel({nlOO0l, (((nlOO1O | nlOO1l) | nlOO1i) | nlO0li), nlOlOO}));
|
.sel({nlOOll, nlOi1l, (((nlOOli | nlOOiO) | nlOOil) | nlOOii)}));
|
defparam
|
defparam
|
nlO0Ol.width_data = 3,
|
nlOi0i.width_data = 3,
|
nlO0Ol.width_sel = 3;
|
nlOi0i.width_sel = 3;
|
oper_selector nlO0Oll
|
oper_selector nlOi0O
|
(
|
(
|
.data({wire_nliliOl_dout, (~ nll0lOO), 1'b0}),
|
.data({wire_nlOl1l_dataout, 1'b0, (~ nli01il)}),
|
.o(wire_nlO0Oll_o),
|
.o(wire_nlOi0O_o),
|
.sel({nlOi00O, nlOi00l, nl0OilO}));
|
.sel({nlOOll, (((nlOOli | nlOOiO) | nlOOil) | nlOi1l), nlOOii}));
|
defparam
|
defparam
|
nlO0Oll.width_data = 3,
|
nlOi0O.width_data = 3,
|
nlO0Oll.width_sel = 3;
|
nlOi0O.width_sel = 3;
|
oper_selector nlO0OOi
|
oper_selector nlOiil
|
(
|
(
|
.data({1'b0, wire_nlOi1il_dataout, wire_nlOi10i_dataout, wire_nlOi11i_dataout, nllO01l, wire_nliliOl_dout}),
|
.data({wire_nlOl1O_dataout, nli01iO, nli01il, 1'b0}),
|
.o(wire_nlO0OOi_o),
|
.o(wire_nlOiil_o),
|
.sel({((nlOi00O | nlOi00l) | nlOi00i), nlOi01O, nlOi01l, nlOi01i, nlOi1OO, nlO100O}));
|
.sel({nlOOll, nlOi1l, nlOOii, ((nlOOli | nlOOiO) | nlOOil)}));
|
defparam
|
defparam
|
nlO0OOi.width_data = 6,
|
nlOiil.width_data = 4,
|
nlO0OOi.width_sel = 6;
|
nlOiil.width_sel = 4;
|
oper_selector nlOi0l
|
oper_selector nlOili
|
(
|
(
|
.data({wire_nlOiOi_dataout, 1'b0, 1'b1}),
|
.data({wire_nlOl0i_dataout, 1'b0, 1'b1}),
|
.o(wire_nlOi0l_o),
|
.o(wire_nlOili_o),
|
.sel({nlOO0l, (((nlOO1O | nlOO1l) | nlOlOO) | nlO0li), nlOO1i}));
|
.sel({nlOOll, (((nlOOli | nlOOil) | nlOOii) | nlOi1l), nlOOiO}));
|
defparam
|
defparam
|
nlOi0l.width_data = 3,
|
nlOili.width_data = 3,
|
nlOi0l.width_sel = 3;
|
nlOili.width_sel = 3;
|
oper_selector nlOi1i
|
oper_selector nlOilO
|
(
|
(
|
.data({wire_nlOill_dataout, nli000i, nli001O, 1'b0}),
|
.data({wire_nlOl0l_dataout, 1'b0, 1'b1}),
|
.o(wire_nlOi1i_o),
|
.o(wire_nlOilO_o),
|
.sel({nlOO0l, nlO0li, nlOlOO, ((nlOO1O | nlOO1l) | nlOO1i)}));
|
.sel({nlOOll, (((nlOOli | nlOOiO) | nlOOii) | nlOi1l), nlOOil}));
|
defparam
|
defparam
|
nlOi1i.width_data = 4,
|
nlOilO.width_data = 3,
|
nlOi1i.width_sel = 4;
|
nlOilO.width_sel = 3;
|
oper_selector nlOi1O
|
oper_selector nlOOO0i
|
(
|
(
|
.data({wire_nlOilO_dataout, 1'b0, 1'b1}),
|
.data({1'b0, nl0OliO, (~ nl0OO1l)}),
|
.o(wire_nlOi1O_o),
|
.o(wire_nlOOO0i_o),
|
.sel({nlOO0l, (((nlOO1O | nlOO1i) | nlOlOO) | nlO0li), nlOO1l}));
|
.sel({nl0OiOi, n11OiO, nlOOlOO}));
|
defparam
|
defparam
|
nlOi1O.width_data = 3,
|
nlOOO0i.width_data = 3,
|
nlOi1O.width_sel = 3;
|
nlOOO0i.width_sel = 3;
|
oper_selector nlOOOil
|
oper_selector nlOOOil
|
(
|
(
|
.data({1'b0, nl0OO0O, (~ nl0OOOl)}),
|
.data({1'b0, nl0OliO, wire_n1101O_dataout}),
|
.o(wire_nlOOOil_o),
|
.o(wire_nlOOOil_o),
|
.sel({nl0Olli, n11OOi, nlOOO0i}));
|
.sel({nl0OiOl, n11OlO, n11Oll}));
|
defparam
|
defparam
|
nlOOOil.width_data = 3,
|
nlOOOil.width_data = 3,
|
nlOOOil.width_sel = 3;
|
nlOOOil.width_sel = 3;
|
|
oper_selector nlOOOli
|
|
(
|
|
.data({1'b0, wire_n110lO_dataout, wire_n110iO_dataout}),
|
|
.o(wire_nlOOOli_o),
|
|
.sel({nl0OiOO, n101ii, n1010l}));
|
|
defparam
|
|
nlOOOli.width_data = 3,
|
|
nlOOOli.width_sel = 3;
|
oper_selector nlOOOlO
|
oper_selector nlOOOlO
|
(
|
(
|
.data({1'b0, nl0OO0O, wire_n110ii_dataout}),
|
.data({1'b0, wire_n11O0i_dataout, wire_n11l1l_dataout, {2{nl0OO1O}}, wire_n11iOl_dataout, wire_n11ill_dataout}),
|
.o(wire_nlOOOlO_o),
|
.o(wire_nlOOOlO_o),
|
.sel({nl0Olll, n1011i, n11OOO}));
|
.sel({nl0Ol1i, n101iO, n101li, n1011l, n1011i, n11OOO, n11OOl}));
|
defparam
|
defparam
|
nlOOOlO.width_data = 3,
|
nlOOOlO.width_data = 7,
|
nlOOOlO.width_sel = 3;
|
nlOOOlO.width_sel = 7;
|
oper_selector nlOOOOl
|
oper_selector nlOOOOO
|
(
|
(
|
.data({1'b0, wire_n11i1i_dataout, wire_n110Oi_dataout}),
|
.data({(~ nl0OO1O), 1'b0}),
|
.o(wire_nlOOOOl_o),
|
.o(wire_nlOOOOO_o),
|
.sel({nl0OllO, n101ll, n101iO}));
|
.sel({n1011l, (~ n1011l)}));
|
defparam
|
defparam
|
nlOOOOl.width_data = 3,
|
nlOOOOO.width_data = 2,
|
nlOOOOl.width_sel = 3;
|
nlOOOOO.width_sel = 2;
|
assign
|
assign
|
gmii_rx_d = {n0O1li, n0O1iO, n0O1il, n0O1ii, n0O10O, n0O10l, n0O10i, n0O11O},
|
gmii_rx_d = {n0O1li, n0O1iO, n0O1il, n0O1ii, n0O10O, n0O10l, n0O10i, n0O11O},
|
gmii_rx_dv = n0O1ll,
|
gmii_rx_dv = n0O1ll,
|
gmii_rx_err = n0O1Oi,
|
gmii_rx_err = n0O1Oi,
|
hd_ena = nl011l,
|
hd_ena = nl011l,
|
led_an = nll111i,
|
led_an = nliOOiO,
|
led_char_err = nil0O,
|
led_char_err = niO0O,
|
led_col = niOiiO,
|
led_col = niOiiO,
|
led_crs = n01i0O,
|
led_crs = n010ll,
|
led_disp_err = niliO,
|
led_disp_err = niOiO,
|
led_link = nil1i,
|
led_link = niO1i,
|
mii_col = niOiiO,
|
mii_col = niOiiO,
|
mii_crs = niO0li,
|
mii_crs = niO0li,
|
mii_rx_d = {n0ll1l, n0ll1i, n0liOO, n0liOl},
|
mii_rx_d = {n0ll1l, n0ll1i, n0liOO, n0liOl},
|
mii_rx_dv = n0liOi,
|
mii_rx_dv = n0liOi,
|
mii_rx_err = n0llli,
|
mii_rx_err = n0llli,
|
nl0O00i = ((((((((((((((((((((~ (nll111l ^ nl0i0i)) & (~ (nll111O ^ nl0i0O))) & (~ (nll110i ^ nl0iii))) & (~ (nll110l ^ nl0iil))) & (~ (nll110O ^ nl0iiO))) & (~ (nll11ii ^ nl0ili))) & (~ (nll11il ^ nl0ill))) & (~ (nll11iO ^ nl0ilO))) & (~ (nll11li ^ nl0iOi))) & (~ (nll11ll ^ nl0iOl))) & (~ (nll11lO ^ nl0iOO))) & (~ (nll11Oi ^ nl0l1l))) & (~ (nll11Ol ^ nl0l1O))) & (~ (nll11OO ^ nl0l0i))) & (~ (nll101i ^ nl0l0O))) & (~ (nll101l ^ nl0lii))) & (~ (nll101O ^ nl0lil))) & (~ (nll100i ^ nl0liO))) & (~ (nll100l ^ nl0lll))) & (~ (nll100O ^ nl0lOi))),
|
nl0O00i = (nllOi0i & (~ nllOi1O)),
|
nl0O00l = ((~ nl0O00O) & nlOl1il),
|
nl0O00l = ((~ (nlO101i ^ nlOO01O)) & nl0O00O),
|
nl0O00O = ((nll00il & nll00ii) & (~ nll000i)),
|
nl0O00O = ((((((((((((((~ (nlO111i ^ nlOO11l)) & (~ (nlO111l ^ nlOO10i))) & (~ (nlO111O ^ nlOO10l))) & (~ (nlO110i ^ nlOO10O))) & (~ (nlO110l ^ nlOO1ii))) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))),
|
nl0O01i = ((nliiOii & (~ nliiO0O)) & (~ nliiO0l)),
|
nl0O01i = (nllOi1l & (~ nllO1Ol)),
|
nl0O01l = (((((nlil0ii & nlil00O) & (~ nlil00l)) & (~ nlil00i)) & (~ nlil01O)) & nlil1lO),
|
nl0O01l = (nlO11OO & nl0O01O),
|
nl0O01O = ((nlil0li & (~ nlil0iO)) & (~ nlil0il)),
|
nl0O01O = ((((((((((((((((~ (nlO111i ^ nlOO11l)) & (~ (nlO111l ^ nlOO10i))) & (~ (nlO111O ^ nlOO10l))) & (~ (nlO110i ^ nlOO10O))) & (~ (nlO110l ^ nlOO1ii))) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))) & (~ (nlO11OO ^ nlOO01l))) & (~ (nlO101i ^ nlOO01O))),
|
nl0O0ii = ((((((((((((((((((((~ (nlliliO ^ nl0i0i)) & (~ (nllilli ^ nl0i0O))) & (~ (nllilll ^ nl0iii))) & (~ (nllillO ^ nl0iil))) & (~ (nllilOi ^ nl0iiO))) & (~ (nllilOl ^ nl0ili))) & (~ (nllilOO ^ nl0ill))) & (~ (nlliO1i ^ nl0ilO))) & (~ (nlliO1l ^ nl0iOi))) & (~ (nlliO1O ^ nl0iOl))) & (~ (nlliO0i ^ nl0iOO))) & (~ (nlliO0l ^ nl0l1l))) & (~ (nlliO0O ^ nl0l1O))) & (~ (nlliOii ^ nl0l0i))) & (~ (nlliOil ^ nl0l0O))) & (~ (nlliOiO ^ nl0lii))) & (~ (nlliOli ^ nl0lil))) & (~ (nlliOll ^ nl0liO))) & (~ (nlliOlO ^ nl0lll))) & (~ (nlliOOi ^ nl0lOi))),
|
nl0O0ii = ((((((((((((((((~ nlO101i) & (~ nlO11OO)) & (~ nlO11Ol)) & (~ nlO11Oi)) & (~ nlO11lO)) & (~ nlO11ll)) & (~ nlO11li)) & (~ nlO11iO)) & (~ nlO11il)) & (~ nlO11ii)) & (~ nlO110O)) & (~ nlO110l)) & (~ nlO110i)) & (~ nlO111O)) & (~ nlO111l)) & (~ nlO111i)),
|
nl0O0il = (wire_nlO0O0l_o | (wire_nlO0O1O_o | (wire_nlO0Oll_o | wire_nlO0Oii_o))),
|
nl0O0il = (nlOi1OO & nllO1Oi),
|
nl0O0iO = ((nlOi00O | wire_nlO0Oii_o) | nl0O0li),
|
nl0O0iO = (((((nlOi01i | nlOi1OO) | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll),
|
nl0O0li = (nlOi01l & wire_nlO0O1O_o),
|
nl0O0li = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1Ol) | nlOi1Oi) | nlO101l),
|
nl0O0ll = ((((((((((((((~ (nlO110l ^ nllOiiO)) & (~ (nlO110O ^ nllOO0l))) & (~ (nlO11ii ^ nllOO0O))) & (~ (nlO11il ^ nllOOii))) & (~ (nlO11iO ^ nllOOil))) & (~ (nlO11li ^ nllOOiO))) & (~ (nlO11ll ^ nllOOli))) & (~ (nlO11lO ^ nllOOll))) & (~ (nlO11Oi ^ nllOOlO))) & (~ (nlO11Ol ^ nllOOOi))) & (~ (nlO11OO ^ nllOOOl))) & (~ (nlO101i ^ nllOOOO))) & (~ (nlO101l ^ nlO111i))) & (~ (nlO101O ^ nlO111l))),
|
nl0O0ll = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1Ol) | nlOi1ll) | nlO101l),
|
nl0O0lO = ((((((((wire_nlO0lOl_o ^ nlO100O) | (nlOi1OO ^ wire_nlO0O1i_o)) | (nlOi01i ^ wire_nlO0O1O_o)) | (nlOi01l ^ wire_nlO0O0l_o)) | (nlOi01O ^ wire_nlO0Oii_o)) | (nlOi00i ^ wire_nlO0OiO_o)) | (nlOi00l ^ wire_nlO0Oll_o)) | (nlOi00O ^ wire_nlO0OOi_o)),
|
nl0O0lO = (((((nlOi01l | nlOi01i) | nlOi1OO) | nlOi1lO) | nlOi1ll) | nlO101l),
|
nl0O0Oi = (nllOi0O & (~ nllO01O)),
|
nl0O0Oi = (((((nlOi01l | nlOi01i) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
|
nl0O0Ol = (nlO100i & nl0O0OO),
|
nl0O0Ol = (((((nlOi01l | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
|
nl0O0OO = ((((((((((((((((~ (nlO110l ^ nlOO10O)) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))) & (~ (nlO11OO ^ nlOO01l))) & (~ (nlO101i ^ nlOO01O))) & (~ (nlO101l ^ nlOO00i))) & (~ (nlO101O ^ nlOO00l))) & (~ (nlO100i ^ nlOO00O))) & (~ (nlO100l ^ nlOO0ii))),
|
nl0O0OO = (((((nlOi1OO | nlOi1Ol) | nlOi1Oi) | nlOi1lO) | nlOi1ll) | nlO101l),
|
nl0O1OO = (((((nliiO0i & nliiO1O) & (~ nliiO1l)) & (~ nliiO1i)) & (~ nliilOO)) & nliiliO),
|
nl0O10i = ((nliilOl & (~ nliilOi)) & (~ nliillO)),
|
nl0Oi0i = ((((((((((((((((~ nlO100l) & (~ nlO100i)) & (~ nlO101O)) & (~ nlO101l)) & (~ nlO101i)) & (~ nlO11OO)) & (~ nlO11Ol)) & (~ nlO11Oi)) & (~ nlO11lO)) & (~ nlO11ll)) & (~ nlO11li)) & (~ nlO11iO)) & (~ nlO11il)) & (~ nlO11ii)) & (~ nlO110O)) & (~ nlO110l)),
|
nl0O10l = (((((nlil1Ol & nlil1Oi) & (~ nlil1lO)) & (~ nlil1ll)) & (~ nlil1li)) & nlil10i),
|
nl0Oi0l = (nlOi00i & nllO01l),
|
nl0O10O = ((nlil01l & (~ nlil01i)) & (~ nlil1OO)),
|
nl0Oi0O = (((((nlOi00l | nlOi00i) | nlOi01O) | nlOi01l) | nlOi01i) | nlOi1OO),
|
nl0O11O = (((((nliilll & nliilli) & (~ nliiliO)) & (~ nliilil)) & (~ nliilii)) & nliil1i),
|
nl0Oi1i = (nllOiil & (~ nllOiii)),
|
nl0O1ii = ((((((((((((((((((((~ (nliOOli ^ nl0i0i)) & (~ (nliOOll ^ nl0i0O))) & (~ (nliOOlO ^ nl0iii))) & (~ (nliOOOi ^ nl0iil))) & (~ (nliOOOl ^ nl0iiO))) & (~ (nliOOOO ^ nl0ili))) & (~ (nll111i ^ nl0ill))) & (~ (nll111l ^ nl0ilO))) & (~ (nll111O ^ nl0iOi))) & (~ (nll110i ^ nl0iOl))) & (~ (nll110l ^ nl0iOO))) & (~ (nll110O ^ nl0l1l))) & (~ (nll11ii ^ nl0l1O))) & (~ (nll11il ^ nl0l0i))) & (~ (nll11iO ^ nl0l0O))) & (~ (nll11li ^ nl0lii))) & (~ (nll11ll ^ nl0lil))) & (~ (nll11lO ^ nl0liO))) & (~ (nll11Oi ^ nl0lll))) & (~ (nll11Ol ^ nl0lOi))),
|
nl0Oi1l = ((~ (nlO100l ^ nlOO0ii)) & nl0Oi1O),
|
nl0O1il = ((~ nl0O1iO) & nlOl10i),
|
nl0Oi1O = ((((((((((((((~ (nlO110l ^ nlOO10O)) & (~ (nlO110O ^ nlOO1il))) & (~ (nlO11ii ^ nlOO1iO))) & (~ (nlO11il ^ nlOO1li))) & (~ (nlO11iO ^ nlOO1ll))) & (~ (nlO11li ^ nlOO1lO))) & (~ (nlO11ll ^ nlOO1Oi))) & (~ (nlO11lO ^ nlOO1Ol))) & (~ (nlO11Oi ^ nlOO1OO))) & (~ (nlO11Ol ^ nlOO01i))) & (~ (nlO11OO ^ nlOO01l))) & (~ (nlO101i ^ nlOO01O))) & (~ (nlO101l ^ nlOO00i))) & (~ (nlO101O ^ nlOO00l))),
|
nl0O1iO = ((nll001i & nll01OO) & (~ nll01lO)),
|
nl0Oiii = (((((nlOi00O | nlOi00l) | nlOi00i) | nlOi01O) | nlOi01l) | nlO100O),
|
nl0O1li = ((((((((((((((((((((~ (nllil0l ^ nl0i0i)) & (~ (nllil0O ^ nl0i0O))) & (~ (nllilii ^ nl0iii))) & (~ (nllilil ^ nl0iil))) & (~ (nlliliO ^ nl0iiO))) & (~ (nllilli ^ nl0ili))) & (~ (nllilll ^ nl0ill))) & (~ (nllillO ^ nl0ilO))) & (~ (nllilOi ^ nl0iOi))) & (~ (nllilOl ^ nl0iOl))) & (~ (nllilOO ^ nl0iOO))) & (~ (nlliO1i ^ nl0l1l))) & (~ (nlliO1l ^ nl0l1O))) & (~ (nlliO1O ^ nl0l0i))) & (~ (nlliO0i ^ nl0l0O))) & (~ (nlliO0l ^ nl0lii))) & (~ (nlliO0O ^ nl0lil))) & (~ (nlliOii ^ nl0liO))) & (~ (nlliOil ^ nl0lll))) & (~ (nlliOiO ^ nl0lOi))),
|
nl0Oiil = (((((nlOi00O | nlOi00l) | nlOi00i) | nlOi01O) | nlOi1OO) | nlO100O),
|
nl0O1ll = (wire_nlO0O1i_o | (wire_nlO0lOl_o | (wire_nlO0Oii_o | wire_nlO0O1O_o))),
|
nl0OiiO = (((((nlOi00O | nlOi00l) | nlOi00i) | nlOi01i) | nlOi1OO) | nlO100O),
|
nl0O1lO = ((nlOi01l | wire_nlO0O1O_o) | nl0O1Oi),
|
nl0Oili = (((((nlOi00O | nlOi00l) | nlOi01l) | nlOi01i) | nlOi1OO) | nlO100O),
|
nl0O1Oi = (nlOi1Oi & wire_nlO0lOl_o),
|
nl0Oill = (((((nlOi00O | nlOi01O) | nlOi01l) | nlOi01i) | nlOi1OO) | nlO100O),
|
nl0O1Ol = ((((((((((((((~ (nlO111i ^ nllOi0l)) & (~ (nlO111l ^ nllOO1i))) & (~ (nlO111O ^ nllOO1l))) & (~ (nlO110i ^ nllOO1O))) & (~ (nlO110l ^ nllOO0i))) & (~ (nlO110O ^ nllOO0l))) & (~ (nlO11ii ^ nllOO0O))) & (~ (nlO11il ^ nllOOii))) & (~ (nlO11iO ^ nllOOil))) & (~ (nlO11li ^ nllOOiO))) & (~ (nlO11ll ^ nllOOli))) & (~ (nlO11lO ^ nllOOll))) & (~ (nlO11Oi ^ nllOOlO))) & (~ (nlO11Ol ^ nllOOOi))),
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nl0OilO = (((((nlOi00i | nlOi01O) | nlOi01l) | nlOi01i) | nlOi1OO) | nlO100O),
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nl0O1OO = ((((((((wire_nlO0lli_o ^ nlO101l) | (nlOi1ll ^ wire_nlO0llO_o)) | (nlOi1lO ^ wire_nlO0lOl_o)) | (nlOi1Oi ^ wire_nlO0O1i_o)) | (nlOi1Ol ^ wire_nlO0O1O_o)) | (nlOi1OO ^ wire_nlO0O0l_o)) | (nlOi01i ^ wire_nlO0Oii_o)) | (nlOi01l ^ wire_nlO0OiO_o)),
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nl0OiOi = (nll0lOO & nll01OO),
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nl0Oi0i = (nllOOOO & nllO1Oi),
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nl0OiOl = (((~ nlO110i) | (~ nllO01l)) & nll0lOO),
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nl0Oi0l = (nllO1lO & nlliOli),
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nl0OiOO = (nllO01i & (~ nlliOOl)),
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nl0Oi0O = ((~ nllOOOO) & nllO1Oi),
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nl0Ol0i = ((((nll10ii | (~ nliOO0l)) | wire_nlill1i_dout) | ((((~ nlOi01i) & (~ nlOi1OO)) & (~ nlO100O)) & nlOO0il)) | (nlOi0ii ^ wire_nliliOl_dout)),
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nl0Oi1i = (nll0lll & nll01il),
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nl0Ol0l = (((((((n10O1l & n10O1i) & n10lOO) & n10lOl) & n10lOi) & n10llO) & n10lll) & (~ n10lli)),
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nl0Oi1l = (((~ nllOOOO) | (~ nllO1Oi)) & nll0lll),
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nl0Ol0O = (n101li | n101iO),
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nl0Oi1O = (nllO1lO & (~ nlliOli)),
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nl0Ol1i = (nlO110i & nllO01l),
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nl0Oiii = ((((nll11OO | (~ nliOlOi)) | wire_nliliil_dout) | ((((~ nlOi1lO) & (~ nlOi1ll)) & (~ nlO101l)) & nlOO00i)) | (nlOi01O ^ wire_nlili0O_dout)),
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nl0Ol1l = (nllO01i & nlliOOl),
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nl0Oiil = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & n10lil) & n10lii) & (~ n10l0O)),
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nl0Ol1O = ((~ nlO110i) & nllO01l),
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nl0OiiO = (n1010O | n1010l),
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nl0Olii = (wire_n111lO_o & (n11OOO | (n1011i | nl0Ol0O))),
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nl0Oili = (wire_n111il_o & (n11Oll | (n11OlO | nl0OiiO))),
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nl0Olil = (wire_n111lO_o & (nlOOO0i | (n11OOi | (n11OOl | nl0Ol0O)))),
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nl0Oill = (wire_n111il_o & (nlOOlOO | (n11OiO | (n11Oli | nl0OiiO)))),
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nl0OliO = (wire_n111lO_o | wire_n111ii_dataout),
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nl0OilO = (wire_n111il_o | wire_n1111O_dataout),
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nl0Olli = ((((((((((((((((n101OO | n101Ol) | n101Oi) | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl),
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nl0OiOi = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli),
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nl0Olll = ((((((((((((((((n101OO | n101Ol) | n101Oi) | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n11OOl) | n11OOi) | nlOOO0i),
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nl0OiOl = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OllO = ((((((((((((((((n101OO | n101Ol) | n101Oi) | n101lO) | n101li) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0OiOO = ((((((((((((((((n101ll | n101li) | n101iO) | n101il) | n1010O) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OlOi = ((((((((((((n101OO | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n101ii) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Ol0i = ((((((((((n101ll | n101li) | n101iO) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOlOO),
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nl0OlOl = (((((((((((((((n101OO | n101Ol) | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Ol0l = ((((((((((((((((n101ll | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OlOO = ((((((((((((((((n101OO | n101Oi) | n101lO) | n101ll) | n101li) | n101iO) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Ol0O = ((((((((((n101iO | n101il) | n101ii) | n1010O) | n1011O) | n1011l) | n1011i) | n11OOi) | n11OlO) | n11Oli) | n11OiO),
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nl0OO0i = (((((((((((((((n101OO | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Ol1i = ((((((((((((n101ll | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OO0l = (((((((((((((((n101Ol | n101Oi) | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011i) | n11OOO) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Ol1l = (((((((((((((((n101ll | n101li) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OO0O = (n10O1O & nl0OOii),
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nl0Ol1O = ((((((((((((((((n101ll | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OO1i = ((((((((((n101OO | n101Ol) | n101Oi) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | nlOOO0i),
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nl0Olii = (((((((((((((((n101ll | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011l) | n1011i) | n11OOO) | n11OOl) | n11OOi) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OO1l = ((((((((((((((((n101OO | n101Oi) | n101lO) | n101ll) | n101li) | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOl) | n11OOi) | nlOOO0i),
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nl0Olil = (((((((((((((((n101li | n101iO) | n101il) | n101ii) | n1010O) | n1010l) | n1010i) | n1011O) | n1011l) | n1011i) | n11OOO) | n11OlO) | n11Oll) | n11Oli) | n11OiO) | nlOOlOO),
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nl0OO1O = ((((((((((n101Oi | n101lO) | n101ll) | n101li) | n101ii) | n1010O) | n1010l) | n1011l) | n1011i) | n11OOl) | n11OOi),
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nl0OliO = (n10lOl & nl0Olli),
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nl0OOii = (((((((n10O1l & n10O1i) & n10lOO) & n10lOl) & (~ n10lOi)) & n10llO) & n10lll) & n10lli),
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nl0Olli = (((((((n10lOi & n10llO) & n10lll) & n10lli) & (~ n10liO)) & n10lil) & n10lii) & n10l0O),
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nl0OOil = (n1i11i & nli111l),
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nl0Olll = (n10OlO & nl0OO0l),
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nl0OOiO = ((~ n1i11i) & nl0OOlO),
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nl0OllO = ((~ n10OlO) & nl0OlOO),
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nl0OOli = (((((((n10O1l & n10O1i) & n10lOO) & n10lOl) & n10lOi) & n10llO) & (~ n10lll)) & n10lli),
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nl0OlOi = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & n10lil) & (~ n10lii)) & n10l0O),
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nl0OOll = (n1i11i & nl0OOlO),
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nl0OlOl = (n10OlO & nl0OlOO),
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nl0OOlO = (n10O1O & nl0OOli),
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nl0OlOO = (n10lOl & nl0OlOi),
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nl0OOOi = ((~ n1i11i) & (~ n10O1O)),
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nl0OO0i = ((~ nll0i0l) & (~ nl0OO0l)),
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nl0OOOl = (n1i11i & nli111l),
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nl0OO0l = (n10lOl & nl0OOil),
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nl0OOOO = (n10O1O | n10liO),
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nl0OO0O = (nll0i0l & ((~ n10lOl) & n10l0i)),
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nli000i = (nlliil | nll0iO),
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nl0OO1i = ((~ n10OlO) & (~ n10lOl)),
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nli000l = (nli00lO & (~ nlli0O)),
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nl0OO1l = (n10OlO & nl0OO0l),
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nli000O = ((~ read) & write),
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nl0OO1O = (n10lOl | n10l0l),
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nli001i = (nl00ii & wire_nllill_o),
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nl0OOii = (nll0i0l & (n10l0i & ((n10lOl & (~ nl0OOll)) & (~ nl0OOil)))),
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nli001l = (wire_nlO0Ol_o | wire_nlO0lO_o),
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nl0OOil = (((((((n10lOi & (~ n10llO)) & n10lll) & n10lli) & n10liO) & n10lil) & (~ n10lii)) & (~ n10l0O)),
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nli001O = (nlliil | nlli0O),
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nl0OOiO = (nll0i0l & nl0OOli),
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nli00ii = ((nli00iO & (~ nlli0O)) & nli00il),
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nl0OOli = (n10lOl & nl0OOll),
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nli00il = ((((address[0] & (~ address[1])) & address[2]) & (~ address[3])) & (~ address[4])),
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nl0OOll = (((((((n10lOi & n10llO) & n10lll) & n10lli) & n10liO) & (~ n10lil)) & n10lii) & n10l0O),
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nli00iO = (read & (~ write)),
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nl0OOlO = ((~ nll0i0l) & n10l0l),
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nli00li = (nli00lO & nli00ll),
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nl0OOOi = ((~ n10lOl) & (nl0OOOO | nl0OOOl)),
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nli00ll = (((((~ address[0]) & address[1]) & address[2]) & address[3]) & (~ address[4])),
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nl0OOOl = (((((((n10lOi & (~ n10llO)) & n10lll) & n10lli) & (~ n10liO)) & n10lil) & (~ n10lii)) & n10l0O),
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nli00lO = (nli00iO & (~ nll0iO)),
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nl0OOOO = ((((((((~ n10lOi) & n10llO) & (~ n10lll)) & (~ n10lli)) & (~ n10liO)) & (~ n10lil)) & n10lii) & (~ n10l0O)),
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nli010i = (((((~ nlO1ii) & (~ nlO10O)) & nlO10l) & nlO10i) & (~ nlO11O)),
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nli000l = ((nli000O | ((~ n11ll) & n10il)) | n11OO),
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nli011l = (nli011O & nlO1il),
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nli000O = (nlii00i & (~ n10lO)),
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nli011O = ((((nlO1ii & (~ nlO10O)) & (~ nlO10l)) & (~ nlO10i)) & (~ nlO11O)),
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nli001i = (((((~ address[0]) & address[1]) & address[2]) & address[3]) & (~ address[4])),
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nli01ii = (nli01il & nlO1il),
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nli001l = (nli01Ol & (~ nlli1i)),
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nli01il = (((((~ nlO1ii) & (~ nlO10O)) & nlO10l) & (~ nlO10i)) & (~ nlO11O)),
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nli00ii = (nli00il | ((~ n101i) & n1i1l)),
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nli01iO = (((((~ nlO1ii) & (~ nlO10O)) & (~ nlO10l)) & (~ nlO10i)) & nlO11O),
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nli00il = (nlii00i & (~ n1i0O)),
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nli01lO = (nli01Oi & nlO1il),
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nli00iO = (nli0iii & n1l1i),
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nli01Oi = (((((~ nlO1ii) & (~ nlO10O)) & (~ nlO10l)) & (~ nlO10i)) & (~ nlO11O)),
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nli00li = (nli00ll | (((~ nli0iii) | n1iOO) & n1l1i)),
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nli01OO = (((((((nlll0i & nlll1O) & nlll1l) & nlll1i) & nlliOO) & nlliOl) & nlliOi) & (~ nllilO)),
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nli00ll = (nlii00i & (~ n1l0O)),
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nli0i0i = (nlii0lO & (~ n10ll)),
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nli00lO = (nli0i0i & n1O0i),
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nli0i0l = (nli0iOl & n1i0O),
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nli00Oi = (nli00Ol | (((~ nli0i0i) | n1O1O) & n1O0i)),
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nli0i0O = (nli0iii | (((~ nli0iOl) | n1i0l) & n1i0O)),
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nli00Ol = (nli0i0l & (~ n1Oll)),
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nli0i1i = ((nli0i1l | ((~ n111l) & n11Oi)) | n110l),
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nli00OO = (nlii00i & (~ n01lO)),
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nli0i1l = (nlii0lO & (~ n101l)),
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nli010l = (((((((nlllll & nlllli) & nllliO) & nlllil) & nlllii) & nlll0O) & nlll0l) & (~ nlll0i)),
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nli0i1O = (nli0i0i | ((~ n110O) & n10ii)),
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nli010O = (nl00ii & wire_nlll1O_o),
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nli0iii = (nlii0lO & (~ n1ill)),
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nli011i = (((((~ nlO1Ol) & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & (~ nlO1li)),
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nli0iil = (nli0ilO & n1l0O),
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nli01ii = (wire_nlOi0O_o | wire_nlOi0i_o),
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nli0iiO = (nlii0lO & (~ n1OOi)),
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nli01il = (nlliOO | nlliOi),
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nli0ili = (nlii0lO & (~ n01ll)),
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nli01iO = (nlliOO | nlli1i),
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nli0ill = (n10ii | n1O0i),
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nli01li = (nli001l & (~ nlliOi)),
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nli0ilO = (n110i & n1ilO),
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nli01ll = ((~ read) & write),
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nli0iOi = ((nlii0lO & (~ n000i)) | (~ n110i)),
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nli01lO = ((nli01Ol & (~ nlliOi)) & nli01Oi),
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nli0iOl = ((~ n111O) & n10Ol),
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nli01Oi = ((((address[0] & (~ address[1])) & address[2]) & (~ address[3])) & (~ address[4])),
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nli0l0i = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & (~ niOOi)) & (~ niOlO)) & (~ niOll)) & (~ niOli)) & niOiO),
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nli01Ol = (read & (~ write)),
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nli0l0l = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & (~ niOOi)) & (~ niOlO)) & niOll) & niOli) & niOiO),
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nli01OO = (nli001l & nli001i),
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nli0l0O = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & (~ niOOi)) & niOlO) & (~ niOll)) & niOli) & niOiO),
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nli0i0i = (n11Ol & n1lii),
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nli0l1i = (n1l0O | n011i),
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nli0i0l = (nlii00i | nli0i0O),
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nli0l1l = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & (~ niOOi)) & (~ niOlO)) & (~ niOll)) & niOli) & (~ niOiO)),
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nli0i0O = ((~ n11Ol) & n1OlO),
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nli0l1O = (((~ niOii) & nli0lli) | (niOii & nli0liO)),
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nli0i1i = (nli0i1O & (~ n00ll)),
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nli0lii = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & niOOi) & (~ niOlO)) & (~ niOll)) & niOli) & niOiO),
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nli0i1l = (n1i1l | n011O),
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nli0lil = ((((((((~ nl11l) & niOOO) & (~ niOOl)) & (~ niOOi)) & (~ niOlO)) & (~ niOll)) & niOli) & niOiO),
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nli0i1O = (nlii00i | nli0i0O),
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nli0liO = (niO0l & (~ wire_nl1ii_runningdisp[0])),
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nli0iii = ((~ n11lO) & n1iiO),
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nli0lli = (niO0l & wire_nl1ii_runningdisp[0]),
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nli0iil = (n1O0i | n01OO),
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nli0lll = (((((((nl11l & (~ niOOO)) & niOOl) & (~ niOOi)) & (~ niOlO)) & (~ niOll)) & niOli) & (~ niOiO)),
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nli0iiO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & (~ nl1iO)),
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nli0lOl = (((((((nl11l & (~ niOOO)) & niOOl) & (~ niOOi)) & (~ niOlO)) & (~ niOll)) & (~ niOli)) & niOiO),
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nli0ili = (((~ nl1ii) & nli0l1l) | (nl1ii & nli0l1i)),
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nli0O0O = (((((((nl11l & (~ niOOO)) & niOOl) & (~ niOOi)) & (~ niOlO)) & niOll) & niOli) & niOiO),
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nli0ill = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & (~ nl1li)) & nl1iO),
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nli0OiO = (((((((nl11l & (~ niOOO)) & niOOl) & niOOi) & (~ niOlO)) & niOll) & (~ niOli)) & (~ niOiO)),
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nli0ilO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & nl1ll) & nl1li) & nl1iO),
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nli0OOl = (((((((nl11l & (~ niOOO)) & niOOl) & (~ niOOi)) & niOlO) & niOll) & (~ niOli)) & (~ niOiO)),
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nli0iOi = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & nl1lO) & (~ nl1ll)) & nl1li) & nl1iO),
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nli100i = ((((((((((n0101l | n0101i) | n011OO) | n011Oi) | n011lO) | n011li) | n011iO) | n011il) | n0110O) | n0110l) | n0110i),
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nli0iOl = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & nl1Oi) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & nl1iO),
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nli100l = (nli10ll & wire_n1i1ii_dout),
|
nli0iOO = ((((((((~ nl01l) & nl1OO) & (~ nl1Ol)) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & nl1iO),
|
nli100O = (nli10iO & wire_n1i1ii_dout),
|
nli0l0O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & (~ nl1li)) & nl1iO),
|
nli101i = (((((((((((((n0101l | n0101i) | n011OO) | n011Ol) | n011Oi) | n011lO) | n011ll) | n011li) | n011iO) | n011il) | n011ii) | n0110O) | n0110l) | n0110i),
|
nli0l1i = (nl10l & (~ wire_nl0ii_runningdisp[0])),
|
nli101l = ((((((((((((n0101O | n011OO) | n011Ol) | n011Oi) | n011ll) | n011li) | n011iO) | n011il) | n011ii) | n0110O) | n0110l) | n0110i) | n1i0Ol),
|
nli0l1l = (nl10l & wire_nl0ii_runningdisp[0]),
|
nli101O = ((((((((((((n0101l | n0101i) | n011OO) | n011Ol) | n011Oi) | n011lO) | n011ll) | n011li) | n011iO) | n011il) | n0110O) | n0110l) | n0110i),
|
nli0l1O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & (~ nl1ll)) & nl1li) & (~ nl1iO)),
|
nli10ii = ((~ wire_n1i1il_dout) & (~ wire_n1i1ii_dout)),
|
nli0lOO = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & (~ nl1lO)) & nl1ll) & nl1li) & nl1iO),
|
nli10il = ((~ nii00l) | (~ wire_n1i1ii_dout)),
|
nli0O0O = (((((((nl01l & (~ nl1OO)) & nl1Ol) & (~ nl1Oi)) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
nli10iO = ((niii0l & nii00l) & n1i1lO),
|
nli0O1i = (((((((nl01l & (~ nl1OO)) & nl1Ol) & nl1Oi) & (~ nl1lO)) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
nli10li = (nli10ll & wire_n1i1ii_dout),
|
nli0Oll = (((((((nl01l & (~ nl1OO)) & nl1Ol) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
nli10ll = (((~ niii0l) & nii00l) & (~ n1i1lO)),
|
nli100i = ((~ n00Oll) & (~ n00Oli)),
|
nli10lO = (((wire_n1i1ll_dout & (~ wire_n1i1il_dout)) & (~ n1i1lO)) & (~ wire_n1i1ii_dout)),
|
nli100l = ((~ n00Oll) & n00Oli),
|
nli10Oi = ((~ nlOl10l) & n0l11l),
|
nli100O = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & n0011i),
|
nli10Ol = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & (~ n01OOO)),
|
nli101i = (nlOl11i | n01l0l),
|
nli10OO = (((((((~ n001iO) & (~ n001il)) & (~ n001ii)) & n0010O) & (~ n0010l)) & (~ n0010i)) & (~ n01OOO)),
|
nli101l = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & (~ n0011i)),
|
nli110i = (nll0iiO & (n10lil & ((n10O1O & (~ nli11il)) & (~ nli110l)))),
|
nli101O = (((((((~ n001iO) & (~ n001il)) & (~ n001ii)) & n0010O) & (~ n0010l)) & (~ n0010i)) & (~ n0011i)),
|
nli110l = (((((((n10O1l & (~ n10O1i)) & n10lOO) & n10lOl) & n10lOi) & n10llO) & (~ n10lll)) & (~ n10lli)),
|
nli10ii = (n00Oil | nli10ll),
|
nli110O = (nll0iiO & nli11ii),
|
nli10il = (n00Oil | (~ nli10ll)),
|
nli111i = ((~ nll0iiO) & (~ nli111l)),
|
nli10iO = ((~ n00Oil) & (~ n0l11l)),
|
nli111l = (n10O1O & nli110l),
|
nli10li = ((~ n00Oil) & (nli10ll & (~ n0l11l))),
|
nli111O = (nll0iiO & ((~ n10O1O) & n10lil)),
|
nli10ll = (n00Oll & (~ n00Oli)),
|
nli11ii = (n10O1O & nli11il),
|
nli10lO = ((~ n00lOO) & n001li),
|
nli11il = (((((((n10O1l & n10O1i) & n10lOO) & n10lOl) & n10lOi) & (~ n10llO)) & n10lll) & n10lli),
|
nli10Oi = (nlil1il & n0li0O),
|
nli11iO = ((~ nll0iiO) & n10liO),
|
nli10Ol = (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])),
|
nli11li = ((~ n10O1O) & (nli11lO | nli11ll)),
|
nli10OO = (wire_n01ill_dout[1] & (~ wire_n01ill_dout[0])),
|
nli11ll = (((((((n10O1l & (~ n10O1i)) & n10lOO) & n10lOl) & (~ n10lOi)) & n10llO) & (~ n10lll)) & n10lli),
|
nli110i = (((((((((((((n011ii | n0110O) | n0110l) | n0110i) | n0111O) | n0111l) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOlO) | n1OOll) | n1OOli) | n1OOiO),
|
nli11lO = ((((((((~ n10O1l) & n10O1i) & (~ n10lOO)) & (~ n10lOl)) & (~ n10lOi)) & (~ n10llO)) & n10lll) & (~ n10lli)),
|
nli110l = ((((((((((((n011il | n0110l) | n0110i) | n0111O) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOlO) | n1OOll) | n1OOli) | n1OOiO) | n1i0li),
|
nli11Oi = (wire_n1Ol0l_o & n1i1lO),
|
nli110O = ((((((((((((n011ii | n0110O) | n0110l) | n0110i) | n0111O) | n0111l) | n0111i) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOll) | n1OOli) | n1OOiO),
|
nli11Ol = ((~ n0101O) & wire_n1Ol0l_o),
|
nli111i = (wire_n1Ol1i_o & n1i1il),
|
nli11OO = (wire_n1OiOO_o & niii0l),
|
nli111l = ((~ n011il) & wire_n1Ol1i_o),
|
nli1i0i = (n00Oil | nli1iil),
|
nli111O = (wire_n1Oill_o & niii0l),
|
nli1i0l = (n00Oil | (~ nli1iil)),
|
nli11ii = ((((((((((n011ii | n0110O) | n0110l) | n0111O) | n0111l) | n1OOOO) | n1OOOl) | n1OOOi) | n1OOll) | n1OOli) | n1OOiO),
|
nli1i0O = ((~ n00Oil) & (~ n0l11l)),
|
nli11il = (nli11ll & wire_n1i11O_dout),
|
nli1i1i = ((~ n00Oll) & (~ n00Oli)),
|
nli11iO = ((~ wire_n1i10i_dout) & (~ wire_n1i11O_dout)),
|
nli1i1l = ((~ n00Oll) & n00Oli),
|
nli11li = ((~ nii00l) | (~ wire_n1i11O_dout)),
|
nli1i1O = ((((((n001iO & n001il) & (~ n001ii)) & (~ n0010O)) & (~ n0010l)) & n0010i) & n01OOO),
|
nli11ll = ((niii0l & nii00l) & n1i1il),
|
nli1iii = ((~ n00Oil) & (nli1iil & (~ n0l11l))),
|
nli11lO = ((((~ niii0l) & nii00l) & (~ n1i1il)) & wire_n1i11O_dout),
|
nli1iil = (n00Oll & (~ n00Oli)),
|
nli11Oi = (((wire_n1i1ii_dout & (~ wire_n1i10i_dout)) & (~ n1i1il)) & (~ wire_n1i11O_dout)),
|
nli1iiO = ((~ n00lOO) & n001li),
|
nli11Ol = (nlOl11i & nlOiOOi),
|
nli1ili = (nlil01i & n0li0O),
|
nli11OO = ((~ nli101i) & n0l11l),
|
nli1ill = (wire_n01l0O_dout[1] & (~ wire_n01l0O_dout[0])),
|
nli1i0i = (nliil0l & (niO1ii & (~ ni1lOl))),
|
nli1ilO = (wire_n01l0O_dout[1] & (~ wire_n01l0O_dout[0])),
|
nli1i0l = (nliil0l & ((~ niO1ii) & ni1lOl)),
|
nli1iOi = (ni10OO | n0OOli),
|
nli1i0O = (nliil0l & (niO1ii & ni1lOl)),
|
nli1iOl = (ni10OO | ni10Ol),
|
nli1i1i = (ni10OO | n0OOli),
|
nli1iOO = (nliilOi & ((~ niO1ii) & (~ ni1lOl))),
|
nli1i1l = (ni10OO | ni10Ol),
|
nli1l0i = (nliilOi & nli1lOO),
|
nli1i1O = (nliil0l & ((~ niO1ii) & (~ ni1lOl))),
|
nli1l0l = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & (~ niii1l)),
|
nli1iii = (nliil0l & nli1l1O),
|
nli1l0O = (((((((~ niiill) & (~ niiili)) & (~ niiiiO)) & niiiil) & (~ niiiii)) & (~ niii0O)) & (~ niii1l)),
|
nli1iil = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & (~ niii1l)),
|
nli1l1i = (nliilOi & (niO1ii & (~ ni1lOl))),
|
nli1iiO = (((((((~ niiill) & (~ niiili)) & (~ niiiiO)) & niiiil) & (~ niiiii)) & (~ niii0O)) & (~ niii1l)),
|
nli1l1l = (nliilOi & ((~ niO1ii) & ni1lOl)),
|
nli1ili = ((~ nil00l) & (~ nil00i)),
|
nli1l1O = (nliilOi & (niO1ii & ni1lOl)),
|
nli1ill = ((~ nil00l) & nil00i),
|
nli1lii = ((~ nil00l) & (~ nil00i)),
|
nli1ilO = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & niii1l),
|
nli1lil = ((~ nil00l) & nil00i),
|
nli1iOi = (nil01l | nli1l1l),
|
nli1liO = ((((((niiill & niiili) & (~ niiiiO)) & (~ niiiil)) & (~ niiiii)) & niii0O) & niii1l),
|
nli1iOl = (nil01l | (~ nli1l1l)),
|
nli1lli = (nil01l | nli1lOl),
|
nli1iOO = ((~ ni0lii) & (~ nil01l)),
|
nli1lll = (nil01l | (~ nli1lOl)),
|
nli1l0i = (niO00i & (~ niO01O)),
|
nli1llO = ((~ ni0lii) & (~ nil01l)),
|
nli1l0l = (((((~ nl1Oll) & (~ nl1Oli)) & nl1OiO) & (~ nl1Oil)) & nl1l0O),
|
nli1lOi = ((~ nil01l) & ((~ ni0lii) & nli1lOl)),
|
nli1l0O = (nll00i & (nlii1O & (nl00Oi & nl00ll))),
|
nli1lOl = (nil00l & (~ nil00i)),
|
nli1l1i = ((~ nil01l) & ((~ ni0lii) & nli1l1l)),
|
nli1lOO = (nliilOi & (niO1ii & (~ ni0O0O))),
|
nli1l1l = (nil00l & (~ nil00i)),
|
nli1O0i = ((~ nl00Oi) & nl00ll),
|
nli1l1O = (nliil0l & (niO1ii & (~ ni0O0O))),
|
nli1O0l = ((((nlO1ii & (~ nlO10O)) & nlO10l) & (~ nlO10i)) & nlO11O),
|
nli1lii = ((~ nl00Oi) & nl00ll),
|
nli1O0O = ((((nlO1ii & (~ nlO10O)) & nlO10l) & nlO10i) & (~ nlO11O)),
|
nli1lil = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & nlO1li),
|
nli1O1i = (niO00i & (~ niO01O)),
|
nli1liO = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & nlO1ll) & (~ nlO1li)),
|
nli1O1l = (((((~ nl1Oll) & (~ nl1Oli)) & nl1OiO) & (~ nl1Oil)) & nl1l0O),
|
nli1lli = (nli1lll & nlO1OO),
|
nli1O1O = (nll1lO & (nlii1O & (nl00Oi & nl00ll))),
|
nli1lll = ((((nlO1Ol & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & (~ nlO1li)),
|
nli1Oii = (nli1Oil & nlO1il),
|
nli1lOl = (nli1lOO & nlO1OO),
|
nli1Oil = ((((nlO1ii & (~ nlO10O)) & nlO10l) & (~ nlO10i)) & (~ nlO11O)),
|
nli1lOO = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & nlO1ll) & nlO1li),
|
nli1Oll = (nli1OlO & nlO1il),
|
nli1O0i = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & (~ nlO1li)),
|
nli1OlO = ((((nlO1ii & (~ nlO10O)) & (~ nlO10l)) & nlO10i) & nlO11O),
|
nli1O0l = (((((~ nlO1Ol) & (~ nlO1Oi)) & nlO1lO) & nlO1ll) & (~ nlO1li)),
|
nli1OOi = (nli1OOl & nlO1il),
|
nli1O1i = (nli1O1l & nlO1OO),
|
nli1OOl = ((((nlO1ii & (~ nlO10O)) & (~ nlO10l)) & nlO10i) & (~ nlO11O)),
|
nli1O1l = ((((nlO1Ol & (~ nlO1Oi)) & (~ nlO1lO)) & nlO1ll) & (~ nlO1li)),
|
nlii00O = ((((((((~ nl11l) & (~ niOOO)) & (~ niOOl)) & niOOi) & niOlO) & niOll) & (~ niOli)) & (~ niOiO)),
|
nli1O1O = (nli1O0i & nlO1OO),
|
nlii0lO = (reset | nl0Oi),
|
nli1OiO = (nli1Oli & nlO1OO),
|
nlii0Oi = 1'b0,
|
nli1Oli = (((((~ nlO1Ol) & (~ nlO1Oi)) & nlO1lO) & (~ nlO1ll)) & (~ nlO1li)),
|
nlii11l = (((((((nl11l & (~ niOOO)) & niOOl) & niOOi) & niOlO) & niOll) & (~ niOli)) & (~ niOiO)),
|
nli1Oll = (((((~ nlO1Ol) & (~ nlO1Oi)) & (~ nlO1lO)) & (~ nlO1ll)) & nlO1li),
|
nlii1ii = (((((((nl11l & (~ niOOO)) & (~ niOOl)) & niOOi) & niOlO) & niOll) & (~ niOli)) & (~ niOiO)),
|
nli1OOO = (nli011i & nlO1OO),
|
nlii1Ol = (((((((nl11l & niOOO) & niOOl) & niOOi) & niOlO) & niOll) & (~ niOli)) & (~ niOiO)),
|
nlii00i = ((nlili | nli0O) | (~ (nlii00l14 ^ nlii00l13))),
|
nliii0i = (reset_rx_clk | nliiiOl),
|
nlii0iO = 1'b0,
|
nliii0l = 1'b1,
|
nlii0li = (reset_tx_clk | nliiiiO),
|
nliii1O = (reset_tx_clk | nliil1l),
|
nlii0ll = (reset_rx_clk | nliii0O),
|
|
nlii0lO = 1'b1,
|
|
nlii11i = (((((((nl01l & (~ nl1OO)) & (~ nl1Ol)) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
|
nlii1il = (((((((nl01l & nl1OO) & nl1Ol) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
|
nlii1Oi = ((((((((~ nl01l) & (~ nl1OO)) & (~ nl1Ol)) & nl1Oi) & nl1lO) & nl1ll) & (~ nl1li)) & (~ nl1iO)),
|
pcs_pwrdn_out = nliO0O,
|
pcs_pwrdn_out = nliO0O,
|
readdata = {nlO11i, nllOOO, nllOOl, nllOOi, nllOlO, nllOll, nllOli, nllOiO, nllOil, nllOii, nllO0O, nllO0l, nllO0i, nllO1O, nllO1l, nllO1i},
|
readdata = {nlO1il, nlO1ii, nlO10O, nlO10l, nlO10i, nlO11O, nlO11l, nlO11i, nllOOO, nllOOl, nllOOi, nllOlO, nllOll, nllOli, nllOiO, nllOil},
|
reconfig_fromgxb = {{16{1'b0}}, wire_nl1il_dprioout},
|
reconfig_fromgxb = {{4{1'b0}}, wire_nl0il_dprioout},
|
rx_clk = wire_nl10l_clkout,
|
rx_clk = wire_nl00l_clkout,
|
rx_clkena = nlil01i,
|
rx_clkena = nlil1il,
|
rx_recovclkout = wire_nl10O_clockout,
|
rx_recovclkout = wire_nl00O_clockout,
|
set_10 = (((~ nl010i) & (~ nl011O)) & (nliiili2 ^ nliiili1)),
|
set_10 = (((~ nl010i) & (~ nl011O)) & (nliii1l2 ^ nliii1l1)),
|
set_100 = ((~ nl010i) & nl011O),
|
set_100 = ((~ nl010i) & nl011O),
|
set_1000 = ((nl010i & (~ nl011O)) & (nliiiil4 ^ nliiiil3)),
|
set_1000 = ((nl010i & (~ nl011O)) & (nlii0OO4 ^ nlii0OO3)),
|
tx_clk = wire_nl10l_clkout,
|
tx_clk = wire_nl00l_clkout,
|
tx_clkena = nliilOi,
|
tx_clkena = nliil0l,
|
txp = wire_nl10i_dataout,
|
txp = wire_nl00i_dataout,
|
waitrequest = nlll0l;
|
waitrequest = nllllO;
|
endmodule //sgmii
|
endmodule //sgmii
|
//synopsys translate_on
|
//synopsys translate_on
|
//VALID FILE
|
//VALID FILE
|
