| Line 12... |
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// altera_mf;cycloneiv_hssi
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// altera_mf;cycloneiv_hssi
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// ============================================================
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// ============================================================
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// ************************************************************
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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//
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// 11.0 Internal Build 138 03/15/2011 PN Full Version
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// 12.0 Internal Build 147 03/05/2012 PN Full Version
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// ************************************************************
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// ************************************************************
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//Copyright (C) 1991-2011 Altera Corporation
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//Copyright (C) 1991-2012 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//associated documentation or information are expressly subject
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| Line 31... |
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//programming logic devices manufactured by Altera and sold by
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//applicable agreement for further details.
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//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altera_tse_altgx_civgx_gige_wo_rmfifo" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
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//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altera_tse_altgx_civgx_gige_wo_rmfifo" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
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//VERSION_BEGIN 11.0 cbx_alt_c3gxb 2011:03:15:21:10:44:PN cbx_altclkbuf 2011:03:15:21:10:45:PN cbx_altiobuf_bidir 2011:03:15:21:10:45:PN cbx_altiobuf_in 2011:03:15:21:10:45:PN cbx_altiobuf_out 2011:03:15:21:10:45:PN cbx_altpll 2011:03:15:21:10:45:PN cbx_cycloneii 2011:03:15:21:10:45:PN cbx_lpm_add_sub 2011:03:15:21:10:45:PN cbx_lpm_compare 2011:03:15:21:10:45:PN cbx_lpm_decode 2011:03:15:21:10:45:PN cbx_lpm_mux 2011:03:15:21:10:45:PN cbx_mgl 2011:03:15:21:50:29:PN cbx_stingray 2011:03:15:21:10:44:PN cbx_stratix 2011:03:15:21:10:45:PN cbx_stratixii 2011:03:15:21:10:45:PN cbx_stratixiii 2011:03:15:21:10:45:PN cbx_stratixv 2011:03:15:21:10:45:PN cbx_util_mgl 2011:03:15:21:10:45:PN VERSION_END
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//VERSION_BEGIN 12.0 cbx_alt_c3gxb 2012:03:05:21:09:17:PN cbx_altclkbuf 2012:03:05:21:09:17:PN cbx_altiobuf_bidir 2012:03:05:21:09:17:PN cbx_altiobuf_in 2012:03:05:21:09:17:PN cbx_altiobuf_out 2012:03:05:21:09:17:PN cbx_altpll 2012:03:05:21:09:17:PN cbx_cycloneii 2012:03:05:21:09:17:PN cbx_lpm_add_sub 2012:03:05:21:09:17:PN cbx_lpm_compare 2012:03:05:21:09:17:PN cbx_lpm_counter 2012:03:05:21:09:17:PN cbx_lpm_decode 2012:03:05:21:09:17:PN cbx_lpm_mux 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_stingray 2012:03:05:21:09:16:PN cbx_stratix 2012:03:05:21:09:18:PN cbx_stratixii 2012:03:05:21:09:18:PN cbx_stratixiii 2012:03:05:21:09:18:PN cbx_stratixv 2012:03:05:21:09:18:PN cbx_util_mgl 2012:03:05:21:09:17:PN VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// altera message_off 10463
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//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
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//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
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//synopsys translate_off
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
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(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
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module altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_p318
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module altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08
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(
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(
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cal_blk_clk,
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cal_blk_clk,
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fixedclk,
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fixedclk,
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fixedclk_fast,
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fixedclk_fast,
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gxb_powerdown,
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gxb_powerdown,
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| Line 570... |
Line 570... |
`ifndef FORMAL_VERIFICATION
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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);
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);
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defparam
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defparam
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receive_pcs0.align_pattern = "0101111100",
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receive_pcs0.align_pattern = "1111100",
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receive_pcs0.align_pattern_length = 10,
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receive_pcs0.align_pattern_length = 7,
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receive_pcs0.allow_align_polarity_inversion = "false",
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receive_pcs0.allow_align_polarity_inversion = "false",
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receive_pcs0.allow_pipe_polarity_inversion = "false",
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receive_pcs0.allow_pipe_polarity_inversion = "false",
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receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
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receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
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receive_pcs0.auto_spd_phystatus_notify_count = 0,
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receive_pcs0.auto_spd_phystatus_notify_count = 0,
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receive_pcs0.bit_slip_enable = "false",
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receive_pcs0.bit_slip_enable = "false",
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| Line 953... |
Line 953... |
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
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tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
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tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
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tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
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txdataout = {wire_transmit_pma0_dataout},
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txdataout = {wire_transmit_pma0_dataout},
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txdetectrxout = {wire_transmit_pcs0_txdetectrx},
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txdetectrxout = {wire_transmit_pcs0_txdetectrx},
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w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
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w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
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endmodule //altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_p318
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endmodule //altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08
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//VALID FILE
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//VALID FILE
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// synopsys translate_off
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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| Line 995... |
Line 995... |
tx_clkout,
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tx_clkout,
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tx_dataout)/* synthesis synthesis_clearbox = 2 */;
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tx_dataout)/* synthesis synthesis_clearbox = 2 */;
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input cal_blk_clk;
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input cal_blk_clk;
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input fixedclk;
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input fixedclk;
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input fixedclk_fast;
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input [5:0] fixedclk_fast;
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input [0:0] gxb_powerdown;
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input [0:0] gxb_powerdown;
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input [0:0] pll_areset;
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input [0:0] pll_areset;
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input [0:0] pll_inclk;
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input [0:0] pll_inclk;
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input reconfig_clk;
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input reconfig_clk;
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input [3:0] reconfig_togxb;
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input [3:0] reconfig_togxb;
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| Line 1063... |
Line 1063... |
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
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wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
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wire [0:0] tx_clkout = sub_wire14[0:0];
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wire [0:0] tx_clkout = sub_wire14[0:0];
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wire [0:0] tx_dataout = sub_wire15[0:0];
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wire [0:0] tx_dataout = sub_wire15[0:0];
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wire [0:0] rx_ctrldetect = sub_wire16[0:0];
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wire [0:0] rx_ctrldetect = sub_wire16[0:0];
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altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_p318 altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_p318_component (
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altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08 altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08_component (
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.pll_inclk (pll_inclk),
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.pll_inclk (pll_inclk),
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.reconfig_togxb (reconfig_togxb),
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.reconfig_togxb (reconfig_togxb),
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.cal_blk_clk (cal_blk_clk),
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.cal_blk_clk (cal_blk_clk),
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.fixedclk (fixedclk),
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.fixedclk (fixedclk),
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.rx_datain (rx_datain),
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.rx_datain (rx_datain),
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| Line 1096... |
Line 1096... |
.rx_rmfifodatadeleted (sub_wire13),
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.rx_rmfifodatadeleted (sub_wire13),
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.tx_clkout (sub_wire14),
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.tx_clkout (sub_wire14),
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.tx_dataout (sub_wire15),
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.tx_dataout (sub_wire15),
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.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
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.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
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clearbox_macroname = alt_c3gxb
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clearbox_macroname = alt_c3gxb
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clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=125.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=High;pll_control_width=1;pll_inclk_period=8000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=none;rx_rate_match_pattern1=10100010010101111100;rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=8;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;
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clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=125.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=High;pll_control_width=1;pll_inclk_period=8000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=1111100;rx_align_pattern_length=7;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=none;rx_rate_match_pattern1=10100010010101111100;rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=8;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;
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rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=1;pll_multiply_by=5;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altera_tse_altgx_civgx_gige_wo_rmfifo;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;" */;
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rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=1;pll_multiply_by=5;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altera_tse_altgx_civgx_gige_wo_rmfifo;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;" */;
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defparam
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defparam
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altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_p318_component.starting_channel_number = starting_channel_number;
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altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08_component.starting_channel_number = starting_channel_number;
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endmodule
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endmodule
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// ============================================================
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// ============================================================
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| Line 1176... |
Line 1176... |
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
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// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
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// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
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// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
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// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
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// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
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// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
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// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
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// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
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// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
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// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
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// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "1111100"
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// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
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// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "7"
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// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
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// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
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// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
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// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
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// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
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// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
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// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
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// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
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// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
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| Line 1255... |
Line 1255... |
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
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// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
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// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
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// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
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// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
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// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
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// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
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// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
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// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
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// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
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// Retrieval info: USED_PORT: fixedclk_fast 0 0 0 0 INPUT NODEFVAL "fixedclk_fast"
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// Retrieval info: USED_PORT: fixedclk_fast 0 0 6 0 INPUT NODEFVAL "fixedclk_fast[5..0]"
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// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
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// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
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// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
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// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
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// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
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// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
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// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
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// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
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// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
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// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
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| Line 1286... |
Line 1286... |
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
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// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
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// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
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// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
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// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
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// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
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// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
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// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
|
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
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// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
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// Retrieval info: CONNECT: @fixedclk_fast 0 0 0 0 fixedclk_fast 0 0 0 0
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// Retrieval info: CONNECT: @fixedclk_fast 0 0 6 0 fixedclk_fast 0 0 6 0
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// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
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// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
|
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
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// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
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// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
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// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
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// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
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// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
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// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
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// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
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