| Line 71... |
Line 71... |
reconfig_fromgxb
|
reconfig_fromgxb
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);
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);
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parameter DEVICE_FAMILY = "STRATIXV"; // The device family the the core is targetted for.
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parameter DEVICE_FAMILY = "STRATIXV"; // The device family the the core is targetted for.
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parameter ENABLE_ALT_RECONFIG = 0;
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parameter ENABLE_ALT_RECONFIG = 0;
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parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
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parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
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parameter ENABLE_DET_LATENCY = 0;
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input phy_mgmt_clk;
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input phy_mgmt_clk;
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input phy_mgmt_clk_reset;
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input phy_mgmt_clk_reset;
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input [8:0]phy_mgmt_address;
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input [8:0]phy_mgmt_address;
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input phy_mgmt_read;
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input phy_mgmt_read;
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| Line 151... |
Line 152... |
.rx_disperr(rx_disperr), // rx_disperr.export
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.rx_disperr(rx_disperr), // rx_disperr.export
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.rx_errdetect(rx_errdetect), // rx_errdetect.export
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.rx_errdetect(rx_errdetect), // rx_errdetect.export
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.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
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.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
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.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
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.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
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.tx_clkout(tx_clkout), // tx_clkout.clk
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.tx_clkout(tx_clkout), // tx_clkout.clk
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.rx_clkout(rx_clkout), // rx_clkout.clk
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.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
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.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
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.tx_datak(tx_datak), // tx_datak.data
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.tx_datak(tx_datak), // tx_datak.data
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.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
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.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
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.rx_datak(rx_datak), // rx_datak.data
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.rx_datak(rx_datak), // rx_datak.data
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.rx_rlv(rx_rlv),
|
.rx_rlv(rx_rlv),
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| Line 163... |
Line 163... |
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
|
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
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.rx_rmfifodatainserted(rx_rmfifodatainserted),
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.rx_rmfifodatainserted(rx_rmfifodatainserted),
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.reconfig_to_xcvr(wire_reconfig_togxb),
|
.reconfig_to_xcvr(wire_reconfig_togxb),
|
.reconfig_from_xcvr(wire_reconfig_fromgxb)
|
.reconfig_from_xcvr(wire_reconfig_fromgxb)
|
);
|
);
|
|
assign rx_clkout = tx_clkout;
|
|
|
end
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end
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endgenerate
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endgenerate
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|
|
generate if (ENABLE_SGMII == 1)
|
generate if ((ENABLE_SGMII == 1) && (ENABLE_DET_LATENCY == 0))
|
begin
|
begin
|
|
|
altera_tse_phyip_gxb_wo_rmfifo the_altera_tse_phyip_gxb_wo_rmfifo (
|
altera_tse_phyip_gxb_wo_rmfifo the_altera_tse_phyip_gxb_wo_rmfifo (
|
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
|
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
|
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
|
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
|
| Line 209... |
Line 210... |
assign rx_rmfifodatainserted = 1'b0;
|
assign rx_rmfifodatainserted = 1'b0;
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
generate if ((ENABLE_SGMII == 1) && (ENABLE_DET_LATENCY == 1))
|
|
begin
|
|
|
|
altera_tse_phyip_det_latency the_altera_tse_phyip_gxb_wo_rmfifo (
|
|
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
|
|
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
|
|
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
|
|
.phy_mgmt_read(phy_mgmt_read), // .read
|
|
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
|
|
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
|
|
.phy_mgmt_write(phy_mgmt_write), // .write
|
|
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
|
|
.tx_ready(tx_ready), // tx_ready.export
|
|
.rx_ready(rx_ready), // rx_ready.export
|
|
.pll_ref_clk(pll_ref_clk), // pll_ref_clk.clk
|
|
.pll_locked(pll_locked), // pll_locked.export
|
|
.tx_serial_data(tx_serial_data), // tx_serial_data.export
|
|
.rx_serial_data(rx_serial_data), // rx_serial_data.export
|
|
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
|
|
.rx_disperr(rx_disperr), // rx_disperr.export
|
|
.rx_errdetect(rx_errdetect), // rx_errdetect.export
|
|
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
|
|
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
|
|
.tx_clkout(tx_clkout), // tx_clkout.clk
|
|
.rx_clkout(rx_clkout), // rx_clkout.clk
|
|
.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
|
|
.tx_datak(tx_datak), // tx_datak.data
|
|
.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
|
|
.rx_datak(rx_datak), // rx_datak.data
|
|
.rx_rlv(rx_rlv),
|
|
.reconfig_to_xcvr(wire_reconfig_togxb),
|
|
.reconfig_from_xcvr(wire_reconfig_fromgxb),
|
|
.rx_bitslipboundaryselectout()
|
|
//.rx_recovered_clk(rx_recovclkout),
|
|
);
|
|
|
|
|
|
assign rx_rmfifodatadeleted = 1'b0;
|
|
assign rx_rmfifodatainserted = 1'b0;
|
|
assign rx_recovclkout = rx_clkout; // work around since this port is not available in Deterministic Latency PHY IP
|
|
|
|
end
|
|
endgenerate
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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