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//
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//
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// $RCSfile: altera_tse_multi_mac_pcs_pma.v,v $
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// $RCSfile: altera_tse_multi_mac_pcs_pma.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma.v,v $
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//
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//
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: max $
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// Check in by : $Author: swbranch $
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// Author : Arul Paniandi
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// Author : Arul Paniandi
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//
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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//
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// Description :
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// Description :
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wire tbi_tx_clk_20;
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wire tbi_tx_clk_20;
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wire tbi_tx_clk_21;
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wire tbi_tx_clk_21;
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wire tbi_tx_clk_22;
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wire tbi_tx_clk_22;
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wire tbi_tx_clk_23;
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wire tbi_tx_clk_23;
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wire reset_ref_clk_int;
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wire reset_tbi_rx_clk_0_int;
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wire reset_tbi_rx_clk_1_int;
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wire reset_tbi_rx_clk_2_int;
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wire reset_tbi_rx_clk_3_int;
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wire reset_tbi_rx_clk_4_int;
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wire reset_tbi_rx_clk_5_int;
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wire reset_tbi_rx_clk_6_int;
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wire reset_tbi_rx_clk_7_int;
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wire reset_tbi_rx_clk_8_int;
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wire reset_tbi_rx_clk_9_int;
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wire reset_tbi_rx_clk_10_int;
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wire reset_tbi_rx_clk_11_int;
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wire reset_tbi_rx_clk_12_int;
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wire reset_tbi_rx_clk_13_int;
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wire reset_tbi_rx_clk_14_int;
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wire reset_tbi_rx_clk_15_int;
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wire reset_tbi_rx_clk_16_int;
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wire reset_tbi_rx_clk_17_int;
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wire reset_tbi_rx_clk_18_int;
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wire reset_tbi_rx_clk_19_int;
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wire reset_tbi_rx_clk_20_int;
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wire reset_tbi_rx_clk_21_int;
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wire reset_tbi_rx_clk_22_int;
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wire reset_tbi_rx_clk_23_int;
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wire pll_areset_0,rx_cda_reset_0,rx_channel_data_align_0,rx_locked_0,rx_reset_0;
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wire pll_areset_0,rx_cda_reset_0,rx_channel_data_align_0,rx_locked_0,rx_reset_0;
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wire pll_areset_1,rx_cda_reset_1,rx_channel_data_align_1,rx_locked_1,rx_reset_1;
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wire pll_areset_1,rx_cda_reset_1,rx_channel_data_align_1,rx_locked_1,rx_reset_1;
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wire pll_areset_2,rx_cda_reset_2,rx_channel_data_align_2,rx_locked_2,rx_reset_2;
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wire pll_areset_2,rx_cda_reset_2,rx_channel_data_align_2,rx_locked_2,rx_reset_2;
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wire pll_areset_3,rx_cda_reset_3,rx_channel_data_align_3,rx_locked_3,rx_reset_3;
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wire pll_areset_3,rx_cda_reset_3,rx_channel_data_align_3,rx_locked_3,rx_reset_3;
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wire pll_areset_4,rx_cda_reset_4,rx_channel_data_align_4,rx_locked_4,rx_reset_4;
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wire pll_areset_4,rx_cda_reset_4,rx_channel_data_align_4,rx_locked_4,rx_reset_4;
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