| Line 1... |
Line 1... |
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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//
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// Revision Control Information
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// Revision Control Information
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//
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//
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// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
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// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $
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//
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//
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// $Revision: #3 $
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// $Revision: #1 $
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// $Date: 2011/12/15 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: perforce $
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// Check in by : $Author: swbranch $
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// Author : Arul Paniandi
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// Author : Arul Paniandi
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//
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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//
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// Description :
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// Description :
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| Line 76... |
Line 77... |
parameter STARTING_CHANNEL_NUMBER = 0,
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parameter STARTING_CHANNEL_NUMBER = 0,
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parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
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parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
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(MAX_CHANNELS > 8)? 12 :
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(MAX_CHANNELS > 8)? 12 :
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(MAX_CHANNELS > 4)? 11 :
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(MAX_CHANNELS > 4)? 11 :
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(MAX_CHANNELS > 2)? 10 :
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(MAX_CHANNELS > 2)? 10 :
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(MAX_CHANNELS > 1)? 9 : 8
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(MAX_CHANNELS > 1)? 9 : 8,
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//IEEE1588 code
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parameter ENABLE_TIMESTAMPING = 0, // To enable time stamping logic
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parameter ENABLE_PTP_1STEP = 0, // To enable time 1 step clock PTP
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parameter TSTAMP_FP_WIDTH = 4 // Finger print width associated to the timestamp request
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)
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)
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// Port List
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// Port List
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(
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(
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| Line 104... |
Line 110... |
input wire ref_clk, // Rference Clock
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input wire ref_clk, // Rference Clock
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// SHARED CLK SIGNALS
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// SHARED CLK SIGNALS
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output wire mac_rx_clk, // Av-ST Receive Clock
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output wire mac_rx_clk, // Av-ST Receive Clock
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output wire mac_tx_clk, // Av-ST Transmit Clock
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output wire mac_tx_clk, // Av-ST Transmit Clock
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input wire pcs_phase_measure_clk,
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// SHARED RX STATUS
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// SHARED RX STATUS
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input wire rx_afull_clk, // Almost full clk
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input wire rx_afull_clk, // Almost full clk
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input wire [1:0] rx_afull_data, // Almost full data
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input wire [1:0] rx_afull_data, // Almost full data
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input wire rx_afull_valid, // Almost full valid
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input wire rx_afull_valid, // Almost full valid
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| Line 153... |
Line 160... |
input wire xoff_gen_0, // Xoff Pause frame generate
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input wire xoff_gen_0, // Xoff Pause frame generate
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input wire xon_gen_0, // Xon Pause frame generate
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input wire xon_gen_0, // Xon Pause frame generate
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input wire magic_sleep_n_0, // Enable Sleep Mode
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input wire magic_sleep_n_0, // Enable Sleep Mode
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output wire magic_wakeup_0, // Wake Up Request
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output wire magic_wakeup_0, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_0, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_0, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_0, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_0, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_0, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_0, // Time of Day
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input wire tx_ingress_timestamp_valid_0, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_0, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_0, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_0, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_0, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_0, // Clock for reconfiguration block
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input wire reconfig_clk_0, // Clock for reconfiguration block
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input wire reconfig_busy_0, // Busy from reconfiguration block
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input wire reconfig_busy_0, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
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| Line 201... |
Line 221... |
input wire xoff_gen_1, // Xoff Pause frame generate
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input wire xoff_gen_1, // Xoff Pause frame generate
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input wire xon_gen_1, // Xon Pause frame generate
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input wire xon_gen_1, // Xon Pause frame generate
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input wire magic_sleep_n_1, // Enable Sleep Mode
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input wire magic_sleep_n_1, // Enable Sleep Mode
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output wire magic_wakeup_1, // Wake Up Request
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output wire magic_wakeup_1, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_1, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_1, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_1, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_1, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_1, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_1, // Time of Day
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input wire tx_ingress_timestamp_valid_1, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_1, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_1, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_1, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_1, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_1, // Clock for reconfiguration block
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input wire reconfig_clk_1, // Clock for reconfiguration block
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input wire reconfig_busy_1, // Busy from reconfiguration block
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input wire reconfig_busy_1, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
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| Line 249... |
Line 282... |
input wire xoff_gen_2, // Xoff Pause frame generate
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input wire xoff_gen_2, // Xoff Pause frame generate
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input wire xon_gen_2, // Xon Pause frame generate
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input wire xon_gen_2, // Xon Pause frame generate
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input wire magic_sleep_n_2, // Enable Sleep Mode
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input wire magic_sleep_n_2, // Enable Sleep Mode
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output wire magic_wakeup_2, // Wake Up Request
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output wire magic_wakeup_2, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_2, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_2, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_2, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_2, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_2, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_2, // Time of Day
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input wire tx_ingress_timestamp_valid_2, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_2, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_2, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_2, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_2, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_2, // Clock for reconfiguration block
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input wire reconfig_clk_2, // Clock for reconfiguration block
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input wire reconfig_busy_2, // Busy from reconfiguration block
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input wire reconfig_busy_2, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
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| Line 297... |
Line 343... |
input wire xoff_gen_3, // Xoff Pause frame generate
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input wire xoff_gen_3, // Xoff Pause frame generate
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input wire xon_gen_3, // Xon Pause frame generate
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input wire xon_gen_3, // Xon Pause frame generate
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input wire magic_sleep_n_3, // Enable Sleep Mode
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input wire magic_sleep_n_3, // Enable Sleep Mode
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output wire magic_wakeup_3, // Wake Up Request
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output wire magic_wakeup_3, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_3, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_3, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_3, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_3, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_3, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_3, // Time of Day
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input wire tx_ingress_timestamp_valid_3, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_3, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_3, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_3, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_3, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_3, // Clock for reconfiguration block
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input wire reconfig_clk_3, // Clock for reconfiguration block
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input wire reconfig_busy_3, // Busy from reconfiguration block
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input wire reconfig_busy_3, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
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| Line 345... |
Line 404... |
input wire xoff_gen_4, // Xoff Pause frame generate
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input wire xoff_gen_4, // Xoff Pause frame generate
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input wire xon_gen_4, // Xon Pause frame generate
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input wire xon_gen_4, // Xon Pause frame generate
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input wire magic_sleep_n_4, // Enable Sleep Mode
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input wire magic_sleep_n_4, // Enable Sleep Mode
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output wire magic_wakeup_4, // Wake Up Request
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output wire magic_wakeup_4, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_4, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_4, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_4, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_4, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_4, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_4, // Time of Day
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input wire tx_ingress_timestamp_valid_4, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_4, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_4, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_4, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_4, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_4, // Clock for reconfiguration block
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input wire reconfig_clk_4, // Clock for reconfiguration block
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input wire reconfig_busy_4, // Busy from reconfiguration block
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input wire reconfig_busy_4, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
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| Line 393... |
Line 465... |
input wire xoff_gen_5, // Xoff Pause frame generate
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input wire xoff_gen_5, // Xoff Pause frame generate
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input wire xon_gen_5, // Xon Pause frame generate
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input wire xon_gen_5, // Xon Pause frame generate
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input wire magic_sleep_n_5, // Enable Sleep Mode
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input wire magic_sleep_n_5, // Enable Sleep Mode
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output wire magic_wakeup_5, // Wake Up Request
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output wire magic_wakeup_5, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_5, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_5, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_5, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_5, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_5, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_5, // Time of Day
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input wire tx_ingress_timestamp_valid_5, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_5, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_5, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_5, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_5, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_5, // Clock for reconfiguration block
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input wire reconfig_clk_5, // Clock for reconfiguration block
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input wire reconfig_busy_5, // Busy from reconfiguration block
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input wire reconfig_busy_5, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
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| Line 441... |
Line 526... |
input wire xoff_gen_6, // Xoff Pause frame generate
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input wire xoff_gen_6, // Xoff Pause frame generate
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input wire xon_gen_6, // Xon Pause frame generate
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input wire xon_gen_6, // Xon Pause frame generate
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input wire magic_sleep_n_6, // Enable Sleep Mode
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input wire magic_sleep_n_6, // Enable Sleep Mode
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output wire magic_wakeup_6, // Wake Up Request
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output wire magic_wakeup_6, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_6, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_6, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_6, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_6, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_6, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_6, // Time of Day
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input wire tx_ingress_timestamp_valid_6, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_6, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_6, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_6, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_6, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_6, // Clock for reconfiguration block
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input wire reconfig_clk_6, // Clock for reconfiguration block
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input wire reconfig_busy_6, // Busy from reconfiguration block
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input wire reconfig_busy_6, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
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| Line 489... |
Line 587... |
input wire xoff_gen_7, // Xoff Pause frame generate
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input wire xoff_gen_7, // Xoff Pause frame generate
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input wire xon_gen_7, // Xon Pause frame generate
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input wire xon_gen_7, // Xon Pause frame generate
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input wire magic_sleep_n_7, // Enable Sleep Mode
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input wire magic_sleep_n_7, // Enable Sleep Mode
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output wire magic_wakeup_7, // Wake Up Request
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output wire magic_wakeup_7, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_7, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_7, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_7, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_7, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_7, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_7, // Time of Day
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input wire tx_ingress_timestamp_valid_7, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_7, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_7, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_7, // RX timestamp data
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input wire [96-1:0] rx_time_of_day_data_7, // Time of Day
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// RECONFIG BLOCK SIGNALS
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// RECONFIG BLOCK SIGNALS
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input wire reconfig_clk_7, // Clock for reconfiguration block
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input wire reconfig_clk_7, // Clock for reconfiguration block
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input wire reconfig_busy_7, // Busy from reconfiguration block
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input wire reconfig_busy_7, // Busy from reconfiguration block
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input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
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input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
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output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
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output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
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| Line 537... |
Line 648... |
input wire xoff_gen_8, // Xoff Pause frame generate
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input wire xoff_gen_8, // Xoff Pause frame generate
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input wire xon_gen_8, // Xon Pause frame generate
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input wire xon_gen_8, // Xon Pause frame generate
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input wire magic_sleep_n_8, // Enable Sleep Mode
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input wire magic_sleep_n_8, // Enable Sleep Mode
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output wire magic_wakeup_8, // Wake Up Request
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output wire magic_wakeup_8, // Wake Up Request
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// IEEE1588's code
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input wire tx_egress_timestamp_request_valid_8, // Timestamp request valid from user
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input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_8, // Fingerprint associated to the timestamp request
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input wire tx_egress_timestamp_insert_valid_8, // Timestamp insert in 1 step clock
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output wire tx_egress_timestamp_valid_8, // Timestamp + fingerprint from TSU
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output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_8, // Timestamp + fingerprint from TSU
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input wire [96-1:0] tx_time_of_day_data_8, // Time of Day
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input wire tx_ingress_timestamp_valid_8, // Timestamp to TSU
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input wire [(96)-1:0] tx_ingress_timestamp_data_8, // Timestamp to TSU
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output wire rx_ingress_timestamp_valid_8, // RX timestamp valid
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output wire [(96)-1:0] rx_ingress_timestamp_data_8, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_8, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_8, // Clock for reconfiguration block
|
input wire reconfig_clk_8, // Clock for reconfiguration block
|
input wire reconfig_busy_8, // Busy from reconfiguration block
|
input wire reconfig_busy_8, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
|
| Line 585... |
Line 709... |
input wire xoff_gen_9, // Xoff Pause frame generate
|
input wire xoff_gen_9, // Xoff Pause frame generate
|
input wire xon_gen_9, // Xon Pause frame generate
|
input wire xon_gen_9, // Xon Pause frame generate
|
input wire magic_sleep_n_9, // Enable Sleep Mode
|
input wire magic_sleep_n_9, // Enable Sleep Mode
|
output wire magic_wakeup_9, // Wake Up Request
|
output wire magic_wakeup_9, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_9, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_9, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_9, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_9, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_9, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_9, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_9, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_9, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_9, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_9, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_9, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_9, // Clock for reconfiguration block
|
input wire reconfig_clk_9, // Clock for reconfiguration block
|
input wire reconfig_busy_9, // Busy from reconfiguration block
|
input wire reconfig_busy_9, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
|
| Line 633... |
Line 770... |
input wire xoff_gen_10, // Xoff Pause frame generate
|
input wire xoff_gen_10, // Xoff Pause frame generate
|
input wire xon_gen_10, // Xon Pause frame generate
|
input wire xon_gen_10, // Xon Pause frame generate
|
input wire magic_sleep_n_10, // Enable Sleep Mode
|
input wire magic_sleep_n_10, // Enable Sleep Mode
|
output wire magic_wakeup_10, // Wake Up Request
|
output wire magic_wakeup_10, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_10, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_10, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_10, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_10, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_10, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_10, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_10, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_10, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_10, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_10, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_10, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_10, // Clock for reconfiguration block
|
input wire reconfig_clk_10, // Clock for reconfiguration block
|
input wire reconfig_busy_10, // Busy from reconfiguration block
|
input wire reconfig_busy_10, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
|
| Line 681... |
Line 831... |
input wire xoff_gen_11, // Xoff Pause frame generate
|
input wire xoff_gen_11, // Xoff Pause frame generate
|
input wire xon_gen_11, // Xon Pause frame generate
|
input wire xon_gen_11, // Xon Pause frame generate
|
input wire magic_sleep_n_11, // Enable Sleep Mode
|
input wire magic_sleep_n_11, // Enable Sleep Mode
|
output wire magic_wakeup_11, // Wake Up Request
|
output wire magic_wakeup_11, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_11, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_11, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_11, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_11, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_11, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_11, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_11, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_11, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_11, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_11, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_11, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_11, // Clock for reconfiguration block
|
input wire reconfig_clk_11, // Clock for reconfiguration block
|
input wire reconfig_busy_11, // Busy from reconfiguration block
|
input wire reconfig_busy_11, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
|
| Line 729... |
Line 892... |
input wire xoff_gen_12, // Xoff Pause frame generate
|
input wire xoff_gen_12, // Xoff Pause frame generate
|
input wire xon_gen_12, // Xon Pause frame generate
|
input wire xon_gen_12, // Xon Pause frame generate
|
input wire magic_sleep_n_12, // Enable Sleep Mode
|
input wire magic_sleep_n_12, // Enable Sleep Mode
|
output wire magic_wakeup_12, // Wake Up Request
|
output wire magic_wakeup_12, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_12, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_12, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_12, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_12, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_12, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_12, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_12, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_12, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_12, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_12, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_12, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_12, // Clock for reconfiguration block
|
input wire reconfig_clk_12, // Clock for reconfiguration block
|
input wire reconfig_busy_12, // Busy from reconfiguration block
|
input wire reconfig_busy_12, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
|
| Line 777... |
Line 953... |
input wire xoff_gen_13, // Xoff Pause frame generate
|
input wire xoff_gen_13, // Xoff Pause frame generate
|
input wire xon_gen_13, // Xon Pause frame generate
|
input wire xon_gen_13, // Xon Pause frame generate
|
input wire magic_sleep_n_13, // Enable Sleep Mode
|
input wire magic_sleep_n_13, // Enable Sleep Mode
|
output wire magic_wakeup_13, // Wake Up Request
|
output wire magic_wakeup_13, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_13, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_13, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_13, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_13, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_13, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_13, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_13, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_13, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_13, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_13, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_13, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_13, // Clock for reconfiguration block
|
input wire reconfig_clk_13, // Clock for reconfiguration block
|
input wire reconfig_busy_13, // Busy from reconfiguration block
|
input wire reconfig_busy_13, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
|
| Line 825... |
Line 1014... |
input wire xoff_gen_14, // Xoff Pause frame generate
|
input wire xoff_gen_14, // Xoff Pause frame generate
|
input wire xon_gen_14, // Xon Pause frame generate
|
input wire xon_gen_14, // Xon Pause frame generate
|
input wire magic_sleep_n_14, // Enable Sleep Mode
|
input wire magic_sleep_n_14, // Enable Sleep Mode
|
output wire magic_wakeup_14, // Wake Up Request
|
output wire magic_wakeup_14, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_14, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_14, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_14, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_14, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_14, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_14, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_14, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_14, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_14, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_14, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_14, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_14, // Clock for reconfiguration block
|
input wire reconfig_clk_14, // Clock for reconfiguration block
|
input wire reconfig_busy_14, // Busy from reconfiguration block
|
input wire reconfig_busy_14, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
|
| Line 873... |
Line 1075... |
input wire xoff_gen_15, // Xoff Pause frame generate
|
input wire xoff_gen_15, // Xoff Pause frame generate
|
input wire xon_gen_15, // Xon Pause frame generate
|
input wire xon_gen_15, // Xon Pause frame generate
|
input wire magic_sleep_n_15, // Enable Sleep Mode
|
input wire magic_sleep_n_15, // Enable Sleep Mode
|
output wire magic_wakeup_15, // Wake Up Request
|
output wire magic_wakeup_15, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_15, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_15, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_15, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_15, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_15, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_15, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_15, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_15, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_15, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_15, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_15, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_15, // Clock for reconfiguration block
|
input wire reconfig_clk_15, // Clock for reconfiguration block
|
input wire reconfig_busy_15, // Busy from reconfiguration block
|
input wire reconfig_busy_15, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
|
| Line 921... |
Line 1136... |
input wire xoff_gen_16, // Xoff Pause frame generate
|
input wire xoff_gen_16, // Xoff Pause frame generate
|
input wire xon_gen_16, // Xon Pause frame generate
|
input wire xon_gen_16, // Xon Pause frame generate
|
input wire magic_sleep_n_16, // Enable Sleep Mode
|
input wire magic_sleep_n_16, // Enable Sleep Mode
|
output wire magic_wakeup_16, // Wake Up Request
|
output wire magic_wakeup_16, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_16, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_16, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_16, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_16, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_16, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_16, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_16, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_16, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_16, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_16, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_16, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_16, // Clock for reconfiguration block
|
input wire reconfig_clk_16, // Clock for reconfiguration block
|
input wire reconfig_busy_16, // Busy from reconfiguration block
|
input wire reconfig_busy_16, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
|
| Line 969... |
Line 1197... |
input wire xoff_gen_17, // Xoff Pause frame generate
|
input wire xoff_gen_17, // Xoff Pause frame generate
|
input wire xon_gen_17, // Xon Pause frame generate
|
input wire xon_gen_17, // Xon Pause frame generate
|
input wire magic_sleep_n_17, // Enable Sleep Mode
|
input wire magic_sleep_n_17, // Enable Sleep Mode
|
output wire magic_wakeup_17, // Wake Up Request
|
output wire magic_wakeup_17, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_17, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_17, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_17, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_17, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_17, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_17, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_17, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_17, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_17, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_17, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_17, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_17, // Clock for reconfiguration block
|
input wire reconfig_clk_17, // Clock for reconfiguration block
|
input wire reconfig_busy_17, // Busy from reconfiguration block
|
input wire reconfig_busy_17, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
|
| Line 1017... |
Line 1258... |
input wire xoff_gen_18, // Xoff Pause frame generate
|
input wire xoff_gen_18, // Xoff Pause frame generate
|
input wire xon_gen_18, // Xon Pause frame generate
|
input wire xon_gen_18, // Xon Pause frame generate
|
input wire magic_sleep_n_18, // Enable Sleep Mode
|
input wire magic_sleep_n_18, // Enable Sleep Mode
|
output wire magic_wakeup_18, // Wake Up Request
|
output wire magic_wakeup_18, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_18, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_18, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_18, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_18, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_18, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_18, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_18, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_18, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_18, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_18, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_18, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_18, // Clock for reconfiguration block
|
input wire reconfig_clk_18, // Clock for reconfiguration block
|
input wire reconfig_busy_18, // Busy from reconfiguration block
|
input wire reconfig_busy_18, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
|
| Line 1065... |
Line 1319... |
input wire xoff_gen_19, // Xoff Pause frame generate
|
input wire xoff_gen_19, // Xoff Pause frame generate
|
input wire xon_gen_19, // Xon Pause frame generate
|
input wire xon_gen_19, // Xon Pause frame generate
|
input wire magic_sleep_n_19, // Enable Sleep Mode
|
input wire magic_sleep_n_19, // Enable Sleep Mode
|
output wire magic_wakeup_19, // Wake Up Request
|
output wire magic_wakeup_19, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_19, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_19, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_19, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_19, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_19, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_19, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_19, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_19, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_19, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_19, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_19, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_19, // Clock for reconfiguration block
|
input wire reconfig_clk_19, // Clock for reconfiguration block
|
input wire reconfig_busy_19, // Busy from reconfiguration block
|
input wire reconfig_busy_19, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
|
| Line 1113... |
Line 1380... |
input wire xoff_gen_20, // Xoff Pause frame generate
|
input wire xoff_gen_20, // Xoff Pause frame generate
|
input wire xon_gen_20, // Xon Pause frame generate
|
input wire xon_gen_20, // Xon Pause frame generate
|
input wire magic_sleep_n_20, // Enable Sleep Mode
|
input wire magic_sleep_n_20, // Enable Sleep Mode
|
output wire magic_wakeup_20, // Wake Up Request
|
output wire magic_wakeup_20, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_20, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_20, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_20, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_20, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_20, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_20, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_20, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_20, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_20, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_20, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_20, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_20, // Clock for reconfiguration block
|
input wire reconfig_clk_20, // Clock for reconfiguration block
|
input wire reconfig_busy_20, // Busy from reconfiguration block
|
input wire reconfig_busy_20, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
|
| Line 1161... |
Line 1441... |
input wire xoff_gen_21, // Xoff Pause frame generate
|
input wire xoff_gen_21, // Xoff Pause frame generate
|
input wire xon_gen_21, // Xon Pause frame generate
|
input wire xon_gen_21, // Xon Pause frame generate
|
input wire magic_sleep_n_21, // Enable Sleep Mode
|
input wire magic_sleep_n_21, // Enable Sleep Mode
|
output wire magic_wakeup_21, // Wake Up Request
|
output wire magic_wakeup_21, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_21, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_21, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_21, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_21, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_21, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_21, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_21, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_21, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_21, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_21, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_21, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_21, // Clock for reconfiguration block
|
input wire reconfig_clk_21, // Clock for reconfiguration block
|
input wire reconfig_busy_21, // Busy from reconfiguration block
|
input wire reconfig_busy_21, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
|
| Line 1209... |
Line 1502... |
input wire xoff_gen_22, // Xoff Pause frame generate
|
input wire xoff_gen_22, // Xoff Pause frame generate
|
input wire xon_gen_22, // Xon Pause frame generate
|
input wire xon_gen_22, // Xon Pause frame generate
|
input wire magic_sleep_n_22, // Enable Sleep Mode
|
input wire magic_sleep_n_22, // Enable Sleep Mode
|
output wire magic_wakeup_22, // Wake Up Request
|
output wire magic_wakeup_22, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_22, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_22, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_22, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_22, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_22, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_22, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_22, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_22, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_22, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_22, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_22, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_22, // Clock for reconfiguration block
|
input wire reconfig_clk_22, // Clock for reconfiguration block
|
input wire reconfig_busy_22, // Busy from reconfiguration block
|
input wire reconfig_busy_22, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
|
| Line 1257... |
Line 1563... |
input wire xoff_gen_23, // Xoff Pause frame generate
|
input wire xoff_gen_23, // Xoff Pause frame generate
|
input wire xon_gen_23, // Xon Pause frame generate
|
input wire xon_gen_23, // Xon Pause frame generate
|
input wire magic_sleep_n_23, // Enable Sleep Mode
|
input wire magic_sleep_n_23, // Enable Sleep Mode
|
output wire magic_wakeup_23, // Wake Up Request
|
output wire magic_wakeup_23, // Wake Up Request
|
|
|
|
// IEEE1588's code
|
|
input wire tx_egress_timestamp_request_valid_23, // Timestamp request valid from user
|
|
input wire [(TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_request_data_23, // Fingerprint associated to the timestamp request
|
|
input wire tx_egress_timestamp_insert_valid_23, // Timestamp insert in 1 step clock
|
|
output wire tx_egress_timestamp_valid_23, // Timestamp + fingerprint from TSU
|
|
output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_23, // Timestamp + fingerprint from TSU
|
|
input wire [96-1:0] tx_time_of_day_data_23, // Time of Day
|
|
input wire tx_ingress_timestamp_valid_23, // Timestamp to TSU
|
|
input wire [(96)-1:0] tx_ingress_timestamp_data_23, // Timestamp to TSU
|
|
output wire rx_ingress_timestamp_valid_23, // RX timestamp valid
|
|
output wire [(96)-1:0] rx_ingress_timestamp_data_23, // RX timestamp data
|
|
input wire [96-1:0] rx_time_of_day_data_23, // Time of Day
|
|
|
// RECONFIG BLOCK SIGNALS
|
// RECONFIG BLOCK SIGNALS
|
input wire reconfig_clk_23, // Clock for reconfiguration block
|
input wire reconfig_clk_23, // Clock for reconfiguration block
|
input wire reconfig_busy_23, // Busy from reconfiguration block
|
input wire reconfig_busy_23, // Busy from reconfiguration block
|
input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
|
input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
|
output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
|
output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
|
| Line 1606... |
Line 1925... |
assign led_char_err_22 = led_char_err_gx[22];
|
assign led_char_err_22 = led_char_err_gx[22];
|
assign led_link_22 = link_status[22];
|
assign led_link_22 = link_status[22];
|
assign led_char_err_23 = led_char_err_gx[23];
|
assign led_char_err_23 = led_char_err_gx[23];
|
assign led_link_23 = link_status[23];
|
assign led_link_23 = link_status[23];
|
|
|
//Resets the Reset Sequencer for the rising edge of Reset signal
|
// Based on PHYIP , when user assert reset - it hold the reset sequencer block in reset.
|
// ---------------------------------------------------------------
|
// , reset sequencing only start then reset_sequnece end.
|
reg reset_p1, reset_p2;
|
wire reset_sync;
|
reg reset_posedge;
|
reg reset_start;
|
always@(posedge clk)
|
|
begin
|
altera_tse_reset_synchronizer reset_sync_u0 (
|
reset_p1 <= reset;
|
.clk(clk),
|
reset_p2 <= reset_p1;
|
.reset_in(reset),
|
reset_posedge <= reset_p1 & ~reset_p2;
|
.reset_out(reset_sync)
|
|
);
|
|
|
|
always@(posedge clk or posedge reset_sync) begin
|
|
if (reset_sync) begin
|
|
reset_start <= 1'b1;
|
|
end
|
|
else begin
|
|
reset_start <= 1'b0;
|
end
|
end
|
|
end
|
|
|
|
wire pcs_phase_measure_clk_w;
|
|
|
|
generate
|
|
if (ENABLE_TIMESTAMPING == 0)
|
|
begin
|
|
assign pcs_phase_measure_clk_w = 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
assign pcs_phase_measure_clk_w = pcs_phase_measure_clk;
|
|
end
|
|
endgenerate
|
|
|
|
|
// Instantiation of the MAC_PCS core that connects to a PMA
|
// Instantiation of the MAC_PCS core that connects to a PMA
|
// --------------------------------------------------------
|
// --------------------------------------------------------
|
|
|
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
|
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
|
| Line 1641... |
Line 1983... |
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
|
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
|
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
|
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
|
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
|
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
|
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
|
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
|
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
|
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
|
|
.pcs_phase_measure_clk(pcs_phase_measure_clk_w),
|
|
|
// Channel 0
|
// Channel 0
|
|
|
|
|
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
|
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
|
| Line 1680... |
Line 2023... |
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
|
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
|
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
|
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
|
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_0(tx_egress_timestamp_request_valid_0), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_0(tx_egress_timestamp_request_data_0), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_0(tx_egress_timestamp_valid_0), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_0(tx_egress_timestamp_data_0), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_0(tx_time_of_day_data_0), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_0(tx_ingress_timestamp_valid_0), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_0(tx_ingress_timestamp_data_0), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_0(rx_ingress_timestamp_valid_0), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_0(rx_ingress_timestamp_data_0), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_0(rx_time_of_day_data_0), //INPUT : Time of Day
|
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1723... |
Line 2077... |
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
|
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
|
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
|
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
|
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_1(tx_egress_timestamp_request_valid_1), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_1(tx_egress_timestamp_request_data_1), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_1(tx_egress_timestamp_valid_1), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_1(tx_egress_timestamp_data_1), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_1(tx_time_of_day_data_1), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_1(tx_ingress_timestamp_valid_1), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_1(tx_ingress_timestamp_data_1), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_1(rx_ingress_timestamp_valid_1), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_1(rx_ingress_timestamp_data_1), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_1(rx_time_of_day_data_1), //INPUT : Time of Day
|
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1766... |
Line 2131... |
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
|
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
|
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
|
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
|
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_2(tx_egress_timestamp_request_valid_2), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_2(tx_egress_timestamp_request_data_2), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_2(tx_egress_timestamp_valid_2), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_2(tx_egress_timestamp_data_2), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_2(tx_time_of_day_data_2), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_2(tx_ingress_timestamp_valid_2), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_2(tx_ingress_timestamp_data_2), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_2(rx_ingress_timestamp_valid_2), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_2(rx_ingress_timestamp_data_2), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_2(rx_time_of_day_data_2), //INPUT : Time of Day
|
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1809... |
Line 2185... |
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
|
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
|
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
|
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
|
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_3(tx_egress_timestamp_request_valid_3), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_3(tx_egress_timestamp_request_data_3), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_3(tx_egress_timestamp_valid_3), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_3(tx_egress_timestamp_data_3), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_3(tx_time_of_day_data_3), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_3(tx_ingress_timestamp_valid_3), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_3(tx_ingress_timestamp_data_3), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_3(rx_ingress_timestamp_valid_3), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_3(rx_ingress_timestamp_data_3), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_3(rx_time_of_day_data_3), //INPUT : Time of Day
|
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1852... |
Line 2239... |
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
|
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
|
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
|
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
|
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_4(tx_egress_timestamp_request_valid_4), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_4(tx_egress_timestamp_request_data_4), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_4(tx_egress_timestamp_valid_4), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_4(tx_egress_timestamp_data_4), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_4(tx_time_of_day_data_4), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_4(tx_ingress_timestamp_valid_4), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_4(tx_ingress_timestamp_data_4), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_4(rx_ingress_timestamp_valid_4), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_4(rx_ingress_timestamp_data_4), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_4(rx_time_of_day_data_4), //INPUT : Time of Day
|
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1895... |
Line 2293... |
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
|
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
|
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
|
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
|
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_5(tx_egress_timestamp_request_valid_5), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_5(tx_egress_timestamp_request_data_5), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_5(tx_egress_timestamp_valid_5), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_5(tx_egress_timestamp_data_5), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_5(tx_time_of_day_data_5), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_5(tx_ingress_timestamp_valid_5), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_5(tx_ingress_timestamp_data_5), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_5(rx_ingress_timestamp_valid_5), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_5(rx_ingress_timestamp_data_5), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_5(rx_time_of_day_data_5), //INPUT : Time of Day
|
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1938... |
Line 2347... |
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
|
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
|
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
|
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
|
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_6(tx_egress_timestamp_request_valid_6), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_6(tx_egress_timestamp_request_data_6), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_6(tx_egress_timestamp_valid_6), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_6(tx_egress_timestamp_data_6), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_6(tx_time_of_day_data_6), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_6(tx_ingress_timestamp_valid_6), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_6(tx_ingress_timestamp_data_6), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_6(rx_ingress_timestamp_valid_6), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_6(rx_ingress_timestamp_data_6), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_6(rx_time_of_day_data_6), //INPUT : Time of Day
|
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 1981... |
Line 2401... |
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
|
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
|
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
|
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
|
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_7(tx_egress_timestamp_request_valid_7), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_7(tx_egress_timestamp_request_data_7), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_7(tx_egress_timestamp_valid_7), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_7(tx_egress_timestamp_data_7), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_7(tx_time_of_day_data_7), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_7(tx_ingress_timestamp_valid_7), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_7(tx_ingress_timestamp_data_7), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_7(rx_ingress_timestamp_valid_7), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_7(rx_ingress_timestamp_data_7), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_7(rx_time_of_day_data_7), //INPUT : Time of Day
|
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2024... |
Line 2455... |
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
|
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
|
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
|
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
|
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_8(tx_egress_timestamp_request_valid_8), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_8(tx_egress_timestamp_request_data_8), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_8(tx_egress_timestamp_valid_8), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_8(tx_egress_timestamp_data_8), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_8(tx_time_of_day_data_8), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_8(tx_ingress_timestamp_valid_8), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_8(tx_ingress_timestamp_data_8), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_8(rx_ingress_timestamp_valid_8), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_8(rx_ingress_timestamp_data_8), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_8(rx_time_of_day_data_8), //INPUT : Time of Day
|
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2067... |
Line 2509... |
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
|
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
|
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
|
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
|
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_9(tx_egress_timestamp_request_valid_9), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_9(tx_egress_timestamp_request_data_9), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_9(tx_egress_timestamp_valid_9), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_9(tx_egress_timestamp_data_9), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_9(tx_time_of_day_data_9), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_9(tx_ingress_timestamp_valid_9), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_9(tx_ingress_timestamp_data_9), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_9(rx_ingress_timestamp_valid_9), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_9(rx_ingress_timestamp_data_9), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_9(rx_time_of_day_data_9), //INPUT : Time of Day
|
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2110... |
Line 2563... |
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
|
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
|
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
|
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
|
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_10(tx_egress_timestamp_request_valid_10), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_10(tx_egress_timestamp_request_data_10), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_10(tx_egress_timestamp_valid_10), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_10(tx_egress_timestamp_data_10), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_10(tx_time_of_day_data_10), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_10(tx_ingress_timestamp_valid_10), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_10(tx_ingress_timestamp_data_10), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_10(rx_ingress_timestamp_valid_10), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_10(rx_ingress_timestamp_data_10), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_10(rx_time_of_day_data_10), //INPUT : Time of Day
|
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2153... |
Line 2617... |
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
|
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
|
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
|
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
|
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_11(tx_egress_timestamp_request_valid_11), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_11(tx_egress_timestamp_request_data_11), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_11(tx_egress_timestamp_valid_11), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_11(tx_egress_timestamp_data_11), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_11(tx_time_of_day_data_11), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_11(tx_ingress_timestamp_valid_11), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_11(tx_ingress_timestamp_data_11), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_11(rx_ingress_timestamp_valid_11), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_11(rx_ingress_timestamp_data_11), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_11(rx_time_of_day_data_11), //INPUT : Time of Day
|
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2196... |
Line 2671... |
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
|
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
|
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
|
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
|
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_12(tx_egress_timestamp_request_valid_12), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_12(tx_egress_timestamp_request_data_12), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_12(tx_egress_timestamp_valid_12), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_12(tx_egress_timestamp_data_12), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_12(tx_time_of_day_data_12), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_12(tx_ingress_timestamp_valid_12), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_12(tx_ingress_timestamp_data_12), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_12(rx_ingress_timestamp_valid_12), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_12(rx_ingress_timestamp_data_12), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_12(rx_time_of_day_data_12), //INPUT : Time of Day
|
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2239... |
Line 2725... |
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
|
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
|
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
|
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
|
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_13(tx_egress_timestamp_request_valid_13), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_13(tx_egress_timestamp_request_data_13), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_13(tx_egress_timestamp_valid_13), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_13(tx_egress_timestamp_data_13), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_13(tx_time_of_day_data_13), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_13(tx_ingress_timestamp_valid_13), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_13(tx_ingress_timestamp_data_13), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_13(rx_ingress_timestamp_valid_13), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_13(rx_ingress_timestamp_data_13), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_13(rx_time_of_day_data_13), //INPUT : Time of Day
|
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2282... |
Line 2779... |
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
|
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
|
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
|
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
|
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_14(tx_egress_timestamp_request_valid_14), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_14(tx_egress_timestamp_request_data_14), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_14(tx_egress_timestamp_valid_14), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_14(tx_egress_timestamp_data_14), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_14(tx_time_of_day_data_14), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_14(tx_ingress_timestamp_valid_14), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_14(tx_ingress_timestamp_data_14), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_14(rx_ingress_timestamp_valid_14), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_14(rx_ingress_timestamp_data_14), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_14(rx_time_of_day_data_14), //INPUT : Time of Day
|
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2325... |
Line 2833... |
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
|
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
|
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
|
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
|
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_15(tx_egress_timestamp_request_valid_15), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_15(tx_egress_timestamp_request_data_15), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_15(tx_egress_timestamp_valid_15), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_15(tx_egress_timestamp_data_15), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_15(tx_time_of_day_data_15), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_15(tx_ingress_timestamp_valid_15), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_15(tx_ingress_timestamp_data_15), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_15(rx_ingress_timestamp_valid_15), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_15(rx_ingress_timestamp_data_15), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_15(rx_time_of_day_data_15), //INPUT : Time of Day
|
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2368... |
Line 2887... |
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
|
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
|
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
|
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
|
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_16(tx_egress_timestamp_request_valid_16), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_16(tx_egress_timestamp_request_data_16), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_16(tx_egress_timestamp_valid_16), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_16(tx_egress_timestamp_data_16), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_16(tx_time_of_day_data_16), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_16(tx_ingress_timestamp_valid_16), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_16(tx_ingress_timestamp_data_16), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_16(rx_ingress_timestamp_valid_16), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_16(rx_ingress_timestamp_data_16), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_16(rx_time_of_day_data_16), //INPUT : Time of Day
|
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2411... |
Line 2941... |
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
|
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
|
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
|
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
|
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_17(tx_egress_timestamp_request_valid_17), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_17(tx_egress_timestamp_request_data_17), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_17(tx_egress_timestamp_valid_17), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_17(tx_egress_timestamp_data_17), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_17(tx_time_of_day_data_17), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_17(tx_ingress_timestamp_valid_17), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_17(tx_ingress_timestamp_data_17), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_17(rx_ingress_timestamp_valid_17), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_17(rx_ingress_timestamp_data_17), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_17(rx_time_of_day_data_17), //INPUT : Time of Day
|
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2454... |
Line 2995... |
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
|
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
|
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
|
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
|
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_18(tx_egress_timestamp_request_valid_18), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_18(tx_egress_timestamp_request_data_18), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_18(tx_egress_timestamp_valid_18), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_18(tx_egress_timestamp_data_18), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_18(tx_time_of_day_data_18), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_18(tx_ingress_timestamp_valid_18), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_18(tx_ingress_timestamp_data_18), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_18(rx_ingress_timestamp_valid_18), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_18(rx_ingress_timestamp_data_18), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_18(rx_time_of_day_data_18), //INPUT : Time of Day
|
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2497... |
Line 3049... |
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
|
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
|
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
|
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
|
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_19(tx_egress_timestamp_request_valid_19), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_19(tx_egress_timestamp_request_data_19), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_19(tx_egress_timestamp_valid_19), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_19(tx_egress_timestamp_data_19), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_19(tx_time_of_day_data_19), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_19(tx_ingress_timestamp_valid_19), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_19(tx_ingress_timestamp_data_19), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_19(rx_ingress_timestamp_valid_19), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_19(rx_ingress_timestamp_data_19), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_19(rx_time_of_day_data_19), //INPUT : Time of Day
|
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2540... |
Line 3103... |
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
|
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
|
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
|
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
|
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_20(tx_egress_timestamp_request_valid_20), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_20(tx_egress_timestamp_request_data_20), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_20(tx_egress_timestamp_valid_20), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_20(tx_egress_timestamp_data_20), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_20(tx_time_of_day_data_20), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_20(tx_ingress_timestamp_valid_20), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_20(tx_ingress_timestamp_data_20), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_20(rx_ingress_timestamp_valid_20), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_20(rx_ingress_timestamp_data_20), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_20(rx_time_of_day_data_20), //INPUT : Time of Day
|
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2583... |
Line 3157... |
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
|
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
|
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
|
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
|
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_21(tx_egress_timestamp_request_valid_21), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_21(tx_egress_timestamp_request_data_21), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_21(tx_egress_timestamp_valid_21), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_21(tx_egress_timestamp_data_21), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_21(tx_time_of_day_data_21), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_21(tx_ingress_timestamp_valid_21), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_21(tx_ingress_timestamp_data_21), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_21(rx_ingress_timestamp_valid_21), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_21(rx_ingress_timestamp_data_21), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_21(rx_time_of_day_data_21), //INPUT : Time of Day
|
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2626... |
Line 3211... |
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
|
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
|
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
|
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
|
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_22(tx_egress_timestamp_request_valid_22), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_22(tx_egress_timestamp_request_data_22), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_22(tx_egress_timestamp_valid_22), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_22(tx_egress_timestamp_data_22), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_22(tx_time_of_day_data_22), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_22(tx_ingress_timestamp_valid_22), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_22(tx_ingress_timestamp_data_22), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_22(rx_ingress_timestamp_valid_22), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_22(rx_ingress_timestamp_data_22), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_22(rx_time_of_day_data_22), //INPUT : Time of Day
|
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2669... |
Line 3265... |
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
|
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
|
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
|
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
|
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
|
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
|
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
|
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
|
|
//IEEE1588's code
|
|
.tx_egress_timestamp_request_valid_23(tx_egress_timestamp_request_valid_23), //INPUT : Timestamp request valid from user
|
|
.tx_egress_timestamp_request_data_23(tx_egress_timestamp_request_data_23), //INPUT : Fingerprint associated to the timestamp request
|
|
.tx_egress_timestamp_valid_23(tx_egress_timestamp_valid_23), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_egress_timestamp_data_23(tx_egress_timestamp_data_23), //OUTPUT : Timestamp + Fingerprint from TSU
|
|
.tx_time_of_day_data_23(tx_time_of_day_data_23), //INPUT : Time of Day
|
|
.tx_ingress_timestamp_valid_23(tx_ingress_timestamp_valid_23), //INPUT : Timestamp to TSU
|
|
.tx_ingress_timestamp_data_23(tx_ingress_timestamp_data_23), //INPUT : Timestamp to TSU
|
|
.rx_ingress_timestamp_valid_23(rx_ingress_timestamp_valid_23), //OUTPUT : RX timestamp valid
|
|
.rx_ingress_timestamp_data_23(rx_ingress_timestamp_data_23), //OUTPUT : RX timestamp data
|
|
.rx_time_of_day_data_23(rx_time_of_day_data_23), //INPUT : Time of Day
|
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
|
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
|
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
|
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
|
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
|
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
|
|
|
| Line 2710... |
Line 3317... |
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
|
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
|
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
|
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
|
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
|
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
|
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
|
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
|
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
|
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
|
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
|
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
|
|
U_MULTI_MAC_PCS.TSTAMP_FP_WIDTH = TSTAMP_FP_WIDTH,
|
|
U_MULTI_MAC_PCS.ENABLE_TIMESTAMPING = ENABLE_TIMESTAMPING,
|
|
U_MULTI_MAC_PCS.ENABLE_PTP_1STEP = ENABLE_PTP_1STEP;
|
|
|
|
|
|
|
// #######################################################################
|
// #######################################################################
|
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
|
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
|
| Line 2754... |
Line 3364... |
wire locked_signal_0;
|
wire locked_signal_0;
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_0(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_0(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset | gxb_pwrdn_in_sig_clk_0),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_0),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_0),// output
|
.pll_powerdown(pll_powerdown_sqcnr_0),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_0),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_0),// output
|
| Line 2771... |
Line 3381... |
.pll_is_locked(locked_signal_0),
|
.pll_is_locked(locked_signal_0),
|
.rx_is_lockedtodata(rx_freqlocked_0),
|
.rx_is_lockedtodata(rx_freqlocked_0),
|
.manual_mode(1'b0),
|
.manual_mode(1'b0),
|
.rx_oc_busy(reconfig_busy_0)
|
.rx_oc_busy(reconfig_busy_0)
|
);
|
);
|
|
|
assign locked_signal_0 = (reset? 1'b0: pll_locked_0);
|
assign locked_signal_0 = (reset? 1'b0: pll_locked_0);
|
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
|
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
|
// -----------------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------------
|
|
|
|
|
| Line 2863... |
Line 3472... |
assign reconfig_fromgxb_0 = {17{1'b0}};
|
assign reconfig_fromgxb_0 = {17{1'b0}};
|
assign led_char_err_gx[0] = 1'b0;
|
assign led_char_err_gx[0] = 1'b0;
|
assign link_status[0] = 1'b0;
|
assign link_status[0] = 1'b0;
|
assign led_disp_err_0 = 1'b0;
|
assign led_disp_err_0 = 1'b0;
|
assign txp_0 = 1'b0;
|
assign txp_0 = 1'b0;
|
assign pcs_clk_c0 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 2905... |
Line 3513... |
|
|
|
|
generate if (MAX_CHANNELS > 1)
|
generate if (MAX_CHANNELS > 1)
|
begin
|
begin
|
wire locked_signal_1;
|
wire locked_signal_1;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_1(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_1(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset | gxb_pwrdn_in_sig_clk_1),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_1),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_1),// output
|
.pll_powerdown(pll_powerdown_sqcnr_1),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_1),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_1),// output
|
| Line 2940... |
Line 3546... |
altera_tse_reset_synchronizer ch_1_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_1_reset_sync_0 (
|
.clk(rx_pcs_clk_c1),
|
.clk(rx_pcs_clk_c1),
|
.reset_in(rx_digitalreset_sqcnr_1),
|
.reset_in(rx_digitalreset_sqcnr_1),
|
.reset_out(reset_rx_pcs_clk_c1_int)
|
.reset_out(reset_rx_pcs_clk_c1_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
|
(
|
(
|
.clk(rx_pcs_clk_c1),
|
.clk(rx_pcs_clk_c1),
|
.reset(reset_rx_pcs_clk_c1_int),
|
.reset(reset_rx_pcs_clk_c1_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3018... |
Line 3625... |
assign reconfig_fromgxb_1 = {17{1'b0}};
|
assign reconfig_fromgxb_1 = {17{1'b0}};
|
assign led_char_err_gx[1] = 1'b0;
|
assign led_char_err_gx[1] = 1'b0;
|
assign link_status[1] = 1'b0;
|
assign link_status[1] = 1'b0;
|
assign led_disp_err_1 = 1'b0;
|
assign led_disp_err_1 = 1'b0;
|
assign txp_1 = 1'b0;
|
assign txp_1 = 1'b0;
|
assign pcs_clk_c1 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3033... |
Line 3639... |
// Export powerdown signal or wire it internally
|
// Export powerdown signal or wire it internally
|
// ---------------------------------------------
|
// ---------------------------------------------
|
reg data_in_2,gxb_pwrdn_in_sig_clk_2;
|
reg data_in_2,gxb_pwrdn_in_sig_clk_2;
|
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
|
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
|
begin
|
begin
|
|
|
always @(posedge clk or posedge gxb_pwrdn_in_2)
|
always @(posedge clk or posedge gxb_pwrdn_in_2)
|
begin
|
begin
|
if (gxb_pwrdn_in_2 == 1) begin
|
if (gxb_pwrdn_in_2 == 1) begin
|
data_in_2 <= 1;
|
data_in_2 <= 1;
|
gxb_pwrdn_in_sig_clk_2 <= 1;
|
gxb_pwrdn_in_sig_clk_2 <= 1;
|
| Line 3061... |
Line 3666... |
|
|
|
|
generate if (MAX_CHANNELS > 2)
|
generate if (MAX_CHANNELS > 2)
|
begin
|
begin
|
wire locked_signal_2;
|
wire locked_signal_2;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_2(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_2(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset | gxb_pwrdn_in_sig_clk_2),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_2),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_2),// output
|
.pll_powerdown(pll_powerdown_sqcnr_2),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_2),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_2),// output
|
| Line 3096... |
Line 3699... |
altera_tse_reset_synchronizer ch_2_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_2_reset_sync_0 (
|
.clk(rx_pcs_clk_c2),
|
.clk(rx_pcs_clk_c2),
|
.reset_in(rx_digitalreset_sqcnr_2),
|
.reset_in(rx_digitalreset_sqcnr_2),
|
.reset_out(reset_rx_pcs_clk_c2_int)
|
.reset_out(reset_rx_pcs_clk_c2_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
|
(
|
(
|
.clk(rx_pcs_clk_c2),
|
.clk(rx_pcs_clk_c2),
|
.reset(reset_rx_pcs_clk_c2_int),
|
.reset(reset_rx_pcs_clk_c2_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3174... |
Line 3778... |
assign reconfig_fromgxb_2 = {17{1'b0}};
|
assign reconfig_fromgxb_2 = {17{1'b0}};
|
assign led_char_err_gx[2] = 1'b0;
|
assign led_char_err_gx[2] = 1'b0;
|
assign link_status[2] = 1'b0;
|
assign link_status[2] = 1'b0;
|
assign led_disp_err_2 = 1'b0;
|
assign led_disp_err_2 = 1'b0;
|
assign txp_2 = 1'b0;
|
assign txp_2 = 1'b0;
|
assign pcs_clk_c2 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3212... |
Line 3815... |
gxb_pwrdn_in_sig_clk_3 = gxb_pwrdn_in_sig[3];
|
gxb_pwrdn_in_sig_clk_3 = gxb_pwrdn_in_sig[3];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 3)
|
generate if (MAX_CHANNELS > 3)
|
begin
|
begin
|
wire locked_signal_3;
|
wire locked_signal_3;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_3(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_3(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_3),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_3),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_3),// output
|
.pll_powerdown(pll_powerdown_sqcnr_3),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_3),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_3),// output
|
| Line 3250... |
Line 3852... |
altera_tse_reset_synchronizer ch_3_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_3_reset_sync_0 (
|
.clk(rx_pcs_clk_c3),
|
.clk(rx_pcs_clk_c3),
|
.reset_in(rx_digitalreset_sqcnr_3),
|
.reset_in(rx_digitalreset_sqcnr_3),
|
.reset_out(reset_rx_pcs_clk_c3_int)
|
.reset_out(reset_rx_pcs_clk_c3_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
|
(
|
(
|
.clk(rx_pcs_clk_c3),
|
.clk(rx_pcs_clk_c3),
|
.reset(reset_rx_pcs_clk_c3_int),
|
.reset(reset_rx_pcs_clk_c3_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3328... |
Line 3931... |
assign reconfig_fromgxb_3 = {17{1'b0}};
|
assign reconfig_fromgxb_3 = {17{1'b0}};
|
assign led_char_err_gx[3] = 1'b0;
|
assign led_char_err_gx[3] = 1'b0;
|
assign link_status[3] = 1'b0;
|
assign link_status[3] = 1'b0;
|
assign led_disp_err_3 = 1'b0;
|
assign led_disp_err_3 = 1'b0;
|
assign txp_3 = 1'b0;
|
assign txp_3 = 1'b0;
|
assign pcs_clk_c3 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3366... |
Line 3968... |
gxb_pwrdn_in_sig_clk_4 = gxb_pwrdn_in_sig[4];
|
gxb_pwrdn_in_sig_clk_4 = gxb_pwrdn_in_sig[4];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 4)
|
generate if (MAX_CHANNELS > 4)
|
begin
|
begin
|
wire locked_signal_4;
|
wire locked_signal_4;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_4(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_4(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_4),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_4),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_4),// output
|
.pll_powerdown(pll_powerdown_sqcnr_4),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_4),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_4),// output
|
| Line 3404... |
Line 4005... |
altera_tse_reset_synchronizer ch_4_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_4_reset_sync_0 (
|
.clk(rx_pcs_clk_c4),
|
.clk(rx_pcs_clk_c4),
|
.reset_in(rx_digitalreset_sqcnr_4),
|
.reset_in(rx_digitalreset_sqcnr_4),
|
.reset_out(reset_rx_pcs_clk_c4_int)
|
.reset_out(reset_rx_pcs_clk_c4_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
|
(
|
(
|
.clk(rx_pcs_clk_c4),
|
.clk(rx_pcs_clk_c4),
|
.reset(reset_rx_pcs_clk_c4_int),
|
.reset(reset_rx_pcs_clk_c4_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3482... |
Line 4084... |
assign reconfig_fromgxb_4 = {17{1'b0}};
|
assign reconfig_fromgxb_4 = {17{1'b0}};
|
assign led_char_err_gx[4] = 1'b0;
|
assign led_char_err_gx[4] = 1'b0;
|
assign link_status[4] = 1'b0;
|
assign link_status[4] = 1'b0;
|
assign led_disp_err_4 = 1'b0;
|
assign led_disp_err_4 = 1'b0;
|
assign txp_4 = 1'b0;
|
assign txp_4 = 1'b0;
|
assign pcs_clk_c4 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3524... |
Line 4125... |
|
|
|
|
generate if (MAX_CHANNELS > 5)
|
generate if (MAX_CHANNELS > 5)
|
begin
|
begin
|
wire locked_signal_5;
|
wire locked_signal_5;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_5(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_5(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_5),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_5),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_5),// output
|
.pll_powerdown(pll_powerdown_sqcnr_5),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_5),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_5),// output
|
| Line 3559... |
Line 4158... |
altera_tse_reset_synchronizer ch_5_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_5_reset_sync_0 (
|
.clk(rx_pcs_clk_c5),
|
.clk(rx_pcs_clk_c5),
|
.reset_in(rx_digitalreset_sqcnr_5),
|
.reset_in(rx_digitalreset_sqcnr_5),
|
.reset_out(reset_rx_pcs_clk_c5_int)
|
.reset_out(reset_rx_pcs_clk_c5_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
|
(
|
(
|
.clk(rx_pcs_clk_c5),
|
.clk(rx_pcs_clk_c5),
|
.reset(reset_rx_pcs_clk_c5_int),
|
.reset(reset_rx_pcs_clk_c5_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3605... |
Line 4205... |
.rx_cruclk (ref_clk),
|
.rx_cruclk (ref_clk),
|
.rx_ctrldetect (rx_kchar_5),
|
.rx_ctrldetect (rx_kchar_5),
|
.rx_clkout (rx_pcs_clk_c5),
|
.rx_clkout (rx_pcs_clk_c5),
|
.rx_datain (rxp_5),
|
.rx_datain (rxp_5),
|
.rx_dataout (rx_frame_5),
|
.rx_dataout (rx_frame_5),
|
.rx_digitalreset (rx_digitalreset_sqcnr_4),
|
.rx_digitalreset (rx_digitalreset_sqcnr_5),
|
.rx_disperr (rx_disp_err[5]),
|
.rx_disperr (rx_disp_err[5]),
|
.rx_errdetect (rx_char_err_gx[5]),
|
.rx_errdetect (rx_char_err_gx[5]),
|
.rx_patterndetect (rx_patterndetect[5]),
|
.rx_patterndetect (rx_patterndetect[5]),
|
.rx_rlv (rx_runlengthviolation[5]),
|
.rx_rlv (rx_runlengthviolation[5]),
|
.rx_seriallpbken (sd_loopback_5),
|
.rx_seriallpbken (sd_loopback_5),
|
| Line 3637... |
Line 4237... |
assign reconfig_fromgxb_5 = {17{1'b0}};
|
assign reconfig_fromgxb_5 = {17{1'b0}};
|
assign led_char_err_gx[5] = 1'b0;
|
assign led_char_err_gx[5] = 1'b0;
|
assign link_status[5] = 1'b0;
|
assign link_status[5] = 1'b0;
|
assign led_disp_err_5 = 1'b0;
|
assign led_disp_err_5 = 1'b0;
|
assign txp_5 = 1'b0;
|
assign txp_5 = 1'b0;
|
assign pcs_clk_c5 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3675... |
Line 4274... |
gxb_pwrdn_in_sig_clk_6 = gxb_pwrdn_in_sig[6];
|
gxb_pwrdn_in_sig_clk_6 = gxb_pwrdn_in_sig[6];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 6)
|
generate if (MAX_CHANNELS > 6)
|
begin
|
begin
|
wire locked_signal_6;
|
wire locked_signal_6;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_6(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_6(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_6),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_6),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_6),// output
|
.pll_powerdown(pll_powerdown_sqcnr_6),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_6),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_6),// output
|
| Line 3713... |
Line 4311... |
altera_tse_reset_synchronizer ch_6_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_6_reset_sync_0 (
|
.clk(rx_pcs_clk_c6),
|
.clk(rx_pcs_clk_c6),
|
.reset_in(rx_digitalreset_sqcnr_6),
|
.reset_in(rx_digitalreset_sqcnr_6),
|
.reset_out(reset_rx_pcs_clk_c6_int)
|
.reset_out(reset_rx_pcs_clk_c6_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
|
(
|
(
|
.clk(rx_pcs_clk_c6),
|
.clk(rx_pcs_clk_c6),
|
.reset(reset_rx_pcs_clk_c6_int),
|
.reset(reset_rx_pcs_clk_c6_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3791... |
Line 4390... |
assign reconfig_fromgxb_6 = {17{1'b0}};
|
assign reconfig_fromgxb_6 = {17{1'b0}};
|
assign led_char_err_gx[6] = 1'b0;
|
assign led_char_err_gx[6] = 1'b0;
|
assign link_status[6] = 1'b0;
|
assign link_status[6] = 1'b0;
|
assign led_disp_err_6 = 1'b0;
|
assign led_disp_err_6 = 1'b0;
|
assign txp_6 = 1'b0;
|
assign txp_6 = 1'b0;
|
assign pcs_clk_c6 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3833... |
Line 4431... |
|
|
|
|
generate if (MAX_CHANNELS > 7)
|
generate if (MAX_CHANNELS > 7)
|
begin
|
begin
|
wire locked_signal_7;
|
wire locked_signal_7;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_7(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_7(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_7),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_7),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_7),// output
|
.pll_powerdown(pll_powerdown_sqcnr_7),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_7),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_7),// output
|
| Line 3868... |
Line 4464... |
altera_tse_reset_synchronizer ch_7_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_7_reset_sync_0 (
|
.clk(rx_pcs_clk_c7),
|
.clk(rx_pcs_clk_c7),
|
.reset_in(rx_digitalreset_sqcnr_7),
|
.reset_in(rx_digitalreset_sqcnr_7),
|
.reset_out(reset_rx_pcs_clk_c7_int)
|
.reset_out(reset_rx_pcs_clk_c7_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
|
(
|
(
|
.clk(rx_pcs_clk_c7),
|
.clk(rx_pcs_clk_c7),
|
.reset(reset_rx_pcs_clk_c7_int),
|
.reset(reset_rx_pcs_clk_c7_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 3946... |
Line 4543... |
assign reconfig_fromgxb_7 = {17{1'b0}};
|
assign reconfig_fromgxb_7 = {17{1'b0}};
|
assign led_char_err_gx[7] = 1'b0;
|
assign led_char_err_gx[7] = 1'b0;
|
assign link_status[7] = 1'b0;
|
assign link_status[7] = 1'b0;
|
assign led_disp_err_7 = 1'b0;
|
assign led_disp_err_7 = 1'b0;
|
assign txp_7 = 1'b0;
|
assign txp_7 = 1'b0;
|
assign pcs_clk_c7 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 3984... |
Line 4580... |
gxb_pwrdn_in_sig_clk_8 = gxb_pwrdn_in_sig[8];
|
gxb_pwrdn_in_sig_clk_8 = gxb_pwrdn_in_sig[8];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 8)
|
generate if (MAX_CHANNELS > 8)
|
begin
|
begin
|
wire locked_signal_8;
|
wire locked_signal_8;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_8(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_8(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_8),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_8),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_8),// output
|
.pll_powerdown(pll_powerdown_sqcnr_8),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_8),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_8),// output
|
| Line 4022... |
Line 4617... |
altera_tse_reset_synchronizer ch_8_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_8_reset_sync_0 (
|
.clk(rx_pcs_clk_c8),
|
.clk(rx_pcs_clk_c8),
|
.reset_in(rx_digitalreset_sqcnr_8),
|
.reset_in(rx_digitalreset_sqcnr_8),
|
.reset_out(reset_rx_pcs_clk_c8_int)
|
.reset_out(reset_rx_pcs_clk_c8_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
|
(
|
(
|
.clk(rx_pcs_clk_c8),
|
.clk(rx_pcs_clk_c8),
|
.reset(reset_rx_pcs_clk_c8_int),
|
.reset(reset_rx_pcs_clk_c8_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4100... |
Line 4696... |
assign reconfig_fromgxb_8 = {17{1'b0}};
|
assign reconfig_fromgxb_8 = {17{1'b0}};
|
assign led_char_err_gx[8] = 1'b0;
|
assign led_char_err_gx[8] = 1'b0;
|
assign link_status[8] = 1'b0;
|
assign link_status[8] = 1'b0;
|
assign led_disp_err_8 = 1'b0;
|
assign led_disp_err_8 = 1'b0;
|
assign txp_8 = 1'b0;
|
assign txp_8 = 1'b0;
|
assign pcs_clk_c8 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4142... |
Line 4737... |
|
|
|
|
generate if (MAX_CHANNELS > 9)
|
generate if (MAX_CHANNELS > 9)
|
begin
|
begin
|
wire locked_signal_9;
|
wire locked_signal_9;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_9(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_9(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_9),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_9),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_9),// output
|
.pll_powerdown(pll_powerdown_sqcnr_9),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_9),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_9),// output
|
| Line 4177... |
Line 4770... |
altera_tse_reset_synchronizer ch_9_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_9_reset_sync_0 (
|
.clk(rx_pcs_clk_c9),
|
.clk(rx_pcs_clk_c9),
|
.reset_in(rx_digitalreset_sqcnr_9),
|
.reset_in(rx_digitalreset_sqcnr_9),
|
.reset_out(reset_rx_pcs_clk_c9_int)
|
.reset_out(reset_rx_pcs_clk_c9_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
|
(
|
(
|
.clk(rx_pcs_clk_c9),
|
.clk(rx_pcs_clk_c9),
|
.reset(reset_rx_pcs_clk_c9_int),
|
.reset(reset_rx_pcs_clk_c9_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4255... |
Line 4849... |
assign reconfig_fromgxb_9 = {17{1'b0}};
|
assign reconfig_fromgxb_9 = {17{1'b0}};
|
assign led_char_err_gx[9] = 1'b0;
|
assign led_char_err_gx[9] = 1'b0;
|
assign link_status[9] = 1'b0;
|
assign link_status[9] = 1'b0;
|
assign led_disp_err_9 = 1'b0;
|
assign led_disp_err_9 = 1'b0;
|
assign txp_9 = 1'b0;
|
assign txp_9 = 1'b0;
|
assign pcs_clk_c9 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4293... |
Line 4886... |
gxb_pwrdn_in_sig_clk_10 = gxb_pwrdn_in_sig[10];
|
gxb_pwrdn_in_sig_clk_10 = gxb_pwrdn_in_sig[10];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 10)
|
generate if (MAX_CHANNELS > 10)
|
begin
|
begin
|
wire locked_signal_10;
|
wire locked_signal_10;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_10(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_10(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_10),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_10),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_10),// output
|
.pll_powerdown(pll_powerdown_sqcnr_10),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_10),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_10),// output
|
| Line 4331... |
Line 4923... |
altera_tse_reset_synchronizer ch_10_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_10_reset_sync_0 (
|
.clk(rx_pcs_clk_c10),
|
.clk(rx_pcs_clk_c10),
|
.reset_in(rx_digitalreset_sqcnr_10),
|
.reset_in(rx_digitalreset_sqcnr_10),
|
.reset_out(reset_rx_pcs_clk_c10_int)
|
.reset_out(reset_rx_pcs_clk_c10_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
|
(
|
(
|
.clk(rx_pcs_clk_c10),
|
.clk(rx_pcs_clk_c10),
|
.reset(reset_rx_pcs_clk_c10_int),
|
.reset(reset_rx_pcs_clk_c10_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4409... |
Line 5002... |
assign reconfig_fromgxb_10 = {17{1'b0}};
|
assign reconfig_fromgxb_10 = {17{1'b0}};
|
assign led_char_err_gx[10] = 1'b0;
|
assign led_char_err_gx[10] = 1'b0;
|
assign link_status[10] = 1'b0;
|
assign link_status[10] = 1'b0;
|
assign led_disp_err_10 = 1'b0;
|
assign led_disp_err_10 = 1'b0;
|
assign txp_10 = 1'b0;
|
assign txp_10 = 1'b0;
|
assign pcs_clk_c10 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4451... |
Line 5043... |
|
|
|
|
generate if (MAX_CHANNELS > 11)
|
generate if (MAX_CHANNELS > 11)
|
begin
|
begin
|
wire locked_signal_11;
|
wire locked_signal_11;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_11(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_11(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_11),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_11),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_11),// output
|
.pll_powerdown(pll_powerdown_sqcnr_11),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_11),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_11),// output
|
| Line 4486... |
Line 5076... |
altera_tse_reset_synchronizer ch_11_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_11_reset_sync_0 (
|
.clk(rx_pcs_clk_c11),
|
.clk(rx_pcs_clk_c11),
|
.reset_in(rx_digitalreset_sqcnr_11),
|
.reset_in(rx_digitalreset_sqcnr_11),
|
.reset_out(reset_rx_pcs_clk_c11_int)
|
.reset_out(reset_rx_pcs_clk_c11_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
|
(
|
(
|
.clk(rx_pcs_clk_c11),
|
.clk(rx_pcs_clk_c11),
|
.reset(reset_rx_pcs_clk_c11_int),
|
.reset(reset_rx_pcs_clk_c11_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4564... |
Line 5155... |
assign reconfig_fromgxb_11 = {17{1'b0}};
|
assign reconfig_fromgxb_11 = {17{1'b0}};
|
assign led_char_err_gx[11] = 1'b0;
|
assign led_char_err_gx[11] = 1'b0;
|
assign link_status[11] = 1'b0;
|
assign link_status[11] = 1'b0;
|
assign led_disp_err_11 = 1'b0;
|
assign led_disp_err_11 = 1'b0;
|
assign txp_11 = 1'b0;
|
assign txp_11 = 1'b0;
|
assign pcs_clk_c11 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4606... |
Line 5196... |
|
|
|
|
generate if (MAX_CHANNELS > 12)
|
generate if (MAX_CHANNELS > 12)
|
begin
|
begin
|
wire locked_signal_12;
|
wire locked_signal_12;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_12(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_12(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_12),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_12),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_12),// output
|
.pll_powerdown(pll_powerdown_sqcnr_12),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_12),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_12),// output
|
| Line 4641... |
Line 5229... |
altera_tse_reset_synchronizer ch_12_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_12_reset_sync_0 (
|
.clk(rx_pcs_clk_c12),
|
.clk(rx_pcs_clk_c12),
|
.reset_in(rx_digitalreset_sqcnr_12),
|
.reset_in(rx_digitalreset_sqcnr_12),
|
.reset_out(reset_rx_pcs_clk_c12_int)
|
.reset_out(reset_rx_pcs_clk_c12_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
|
(
|
(
|
.clk(rx_pcs_clk_c12),
|
.clk(rx_pcs_clk_c12),
|
.reset(reset_rx_pcs_clk_c12_int),
|
.reset(reset_rx_pcs_clk_c12_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4719... |
Line 5308... |
assign reconfig_fromgxb_12 = {17{1'b0}};
|
assign reconfig_fromgxb_12 = {17{1'b0}};
|
assign led_char_err_gx[12] = 1'b0;
|
assign led_char_err_gx[12] = 1'b0;
|
assign link_status[12] = 1'b0;
|
assign link_status[12] = 1'b0;
|
assign led_disp_err_12 = 1'b0;
|
assign led_disp_err_12 = 1'b0;
|
assign txp_12 = 1'b0;
|
assign txp_12 = 1'b0;
|
assign pcs_clk_c12 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4757... |
Line 5345... |
gxb_pwrdn_in_sig_clk_13 = gxb_pwrdn_in_sig[13];
|
gxb_pwrdn_in_sig_clk_13 = gxb_pwrdn_in_sig[13];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 13)
|
generate if (MAX_CHANNELS > 13)
|
begin
|
begin
|
wire locked_signal_13;
|
wire locked_signal_13;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_13(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_13(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_13),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_13),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_13),// output
|
.pll_powerdown(pll_powerdown_sqcnr_13),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_13),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_13),// output
|
| Line 4795... |
Line 5382... |
altera_tse_reset_synchronizer ch_13_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_13_reset_sync_0 (
|
.clk(rx_pcs_clk_c13),
|
.clk(rx_pcs_clk_c13),
|
.reset_in(rx_digitalreset_sqcnr_13),
|
.reset_in(rx_digitalreset_sqcnr_13),
|
.reset_out(reset_rx_pcs_clk_c13_int)
|
.reset_out(reset_rx_pcs_clk_c13_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
|
(
|
(
|
.clk(rx_pcs_clk_c13),
|
.clk(rx_pcs_clk_c13),
|
.reset(reset_rx_pcs_clk_c13_int),
|
.reset(reset_rx_pcs_clk_c13_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 4873... |
Line 5461... |
assign reconfig_fromgxb_13 = {17{1'b0}};
|
assign reconfig_fromgxb_13 = {17{1'b0}};
|
assign led_char_err_gx[13] = 1'b0;
|
assign led_char_err_gx[13] = 1'b0;
|
assign link_status[13] = 1'b0;
|
assign link_status[13] = 1'b0;
|
assign led_disp_err_13 = 1'b0;
|
assign led_disp_err_13 = 1'b0;
|
assign txp_13 = 1'b0;
|
assign txp_13 = 1'b0;
|
assign pcs_clk_c13 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 4911... |
Line 5498... |
gxb_pwrdn_in_sig_clk_14 = gxb_pwrdn_in_sig[14];
|
gxb_pwrdn_in_sig_clk_14 = gxb_pwrdn_in_sig[14];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 14)
|
generate if (MAX_CHANNELS > 14)
|
begin
|
begin
|
wire locked_signal_14;
|
wire locked_signal_14;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_14(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_14(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_14),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_14),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_14),// output
|
.pll_powerdown(pll_powerdown_sqcnr_14),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_14),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_14),// output
|
| Line 4949... |
Line 5535... |
altera_tse_reset_synchronizer ch_14_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_14_reset_sync_0 (
|
.clk(rx_pcs_clk_c14),
|
.clk(rx_pcs_clk_c14),
|
.reset_in(rx_digitalreset_sqcnr_14),
|
.reset_in(rx_digitalreset_sqcnr_14),
|
.reset_out(reset_rx_pcs_clk_c14_int)
|
.reset_out(reset_rx_pcs_clk_c14_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
|
(
|
(
|
.clk(rx_pcs_clk_c14),
|
.clk(rx_pcs_clk_c14),
|
.reset(reset_rx_pcs_clk_c14_int),
|
.reset(reset_rx_pcs_clk_c14_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5027... |
Line 5614... |
assign reconfig_fromgxb_14 = {17{1'b0}};
|
assign reconfig_fromgxb_14 = {17{1'b0}};
|
assign led_char_err_gx[14] = 1'b0;
|
assign led_char_err_gx[14] = 1'b0;
|
assign link_status[14] = 1'b0;
|
assign link_status[14] = 1'b0;
|
assign led_disp_err_14 = 1'b0;
|
assign led_disp_err_14 = 1'b0;
|
assign txp_14 = 1'b0;
|
assign txp_14 = 1'b0;
|
assign pcs_clk_c14 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5065... |
Line 5651... |
gxb_pwrdn_in_sig_clk_15 = gxb_pwrdn_in_sig[15];
|
gxb_pwrdn_in_sig_clk_15 = gxb_pwrdn_in_sig[15];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 15)
|
generate if (MAX_CHANNELS > 15)
|
begin
|
begin
|
wire locked_signal_15;
|
wire locked_signal_15;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_15(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_15(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_15),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_15),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_15),// output
|
.pll_powerdown(pll_powerdown_sqcnr_15),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_15),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_15),// output
|
| Line 5103... |
Line 5688... |
altera_tse_reset_synchronizer ch_15_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_15_reset_sync_0 (
|
.clk(rx_pcs_clk_c15),
|
.clk(rx_pcs_clk_c15),
|
.reset_in(rx_digitalreset_sqcnr_15),
|
.reset_in(rx_digitalreset_sqcnr_15),
|
.reset_out(reset_rx_pcs_clk_c15_int)
|
.reset_out(reset_rx_pcs_clk_c15_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
|
(
|
(
|
.clk(rx_pcs_clk_c15),
|
.clk(rx_pcs_clk_c15),
|
.reset(reset_rx_pcs_clk_c15_int),
|
.reset(reset_rx_pcs_clk_c15_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5181... |
Line 5767... |
assign reconfig_fromgxb_15 = {17{1'b0}};
|
assign reconfig_fromgxb_15 = {17{1'b0}};
|
assign led_char_err_gx[15] = 1'b0;
|
assign led_char_err_gx[15] = 1'b0;
|
assign link_status[15] = 1'b0;
|
assign link_status[15] = 1'b0;
|
assign led_disp_err_15 = 1'b0;
|
assign led_disp_err_15 = 1'b0;
|
assign txp_15 = 1'b0;
|
assign txp_15 = 1'b0;
|
assign pcs_clk_c15 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5219... |
Line 5804... |
gxb_pwrdn_in_sig_clk_16 = gxb_pwrdn_in_sig[16];
|
gxb_pwrdn_in_sig_clk_16 = gxb_pwrdn_in_sig[16];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 16)
|
generate if (MAX_CHANNELS > 16)
|
begin
|
begin
|
wire locked_signal_16;
|
wire locked_signal_16;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_16(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_16(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_16),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_16),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_16),// output
|
.pll_powerdown(pll_powerdown_sqcnr_16),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_16),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_16),// output
|
| Line 5257... |
Line 5841... |
altera_tse_reset_synchronizer ch_16_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_16_reset_sync_0 (
|
.clk(rx_pcs_clk_c16),
|
.clk(rx_pcs_clk_c16),
|
.reset_in(rx_digitalreset_sqcnr_16),
|
.reset_in(rx_digitalreset_sqcnr_16),
|
.reset_out(reset_rx_pcs_clk_c16_int)
|
.reset_out(reset_rx_pcs_clk_c16_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
|
(
|
(
|
.clk(rx_pcs_clk_c16),
|
.clk(rx_pcs_clk_c16),
|
.reset(reset_rx_pcs_clk_c16_int),
|
.reset(reset_rx_pcs_clk_c16_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5335... |
Line 5920... |
assign reconfig_fromgxb_16 = {17{1'b0}};
|
assign reconfig_fromgxb_16 = {17{1'b0}};
|
assign led_char_err_gx[16] = 1'b0;
|
assign led_char_err_gx[16] = 1'b0;
|
assign link_status[16] = 1'b0;
|
assign link_status[16] = 1'b0;
|
assign led_disp_err_16 = 1'b0;
|
assign led_disp_err_16 = 1'b0;
|
assign txp_16 = 1'b0;
|
assign txp_16 = 1'b0;
|
assign pcs_clk_c16 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5373... |
Line 5957... |
gxb_pwrdn_in_sig_clk_17 = gxb_pwrdn_in_sig[17];
|
gxb_pwrdn_in_sig_clk_17 = gxb_pwrdn_in_sig[17];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 17)
|
generate if (MAX_CHANNELS > 17)
|
begin
|
begin
|
wire locked_signal_17;
|
wire locked_signal_17;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_17(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_17(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_17),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_17),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_17),// output
|
.pll_powerdown(pll_powerdown_sqcnr_17),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_17),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_17),// output
|
| Line 5411... |
Line 5994... |
altera_tse_reset_synchronizer ch_17_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_17_reset_sync_0 (
|
.clk(rx_pcs_clk_c17),
|
.clk(rx_pcs_clk_c17),
|
.reset_in(rx_digitalreset_sqcnr_17),
|
.reset_in(rx_digitalreset_sqcnr_17),
|
.reset_out(reset_rx_pcs_clk_c17_int)
|
.reset_out(reset_rx_pcs_clk_c17_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
|
(
|
(
|
.clk(rx_pcs_clk_c17),
|
.clk(rx_pcs_clk_c17),
|
.reset(reset_rx_pcs_clk_c17_int),
|
.reset(reset_rx_pcs_clk_c17_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5489... |
Line 6073... |
assign reconfig_fromgxb_17 = {17{1'b0}};
|
assign reconfig_fromgxb_17 = {17{1'b0}};
|
assign led_char_err_gx[17] = 1'b0;
|
assign led_char_err_gx[17] = 1'b0;
|
assign link_status[17] = 1'b0;
|
assign link_status[17] = 1'b0;
|
assign led_disp_err_17 = 1'b0;
|
assign led_disp_err_17 = 1'b0;
|
assign txp_17 = 1'b0;
|
assign txp_17 = 1'b0;
|
assign pcs_clk_c17 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5527... |
Line 6110... |
gxb_pwrdn_in_sig_clk_18 = gxb_pwrdn_in_sig[18];
|
gxb_pwrdn_in_sig_clk_18 = gxb_pwrdn_in_sig[18];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 18)
|
generate if (MAX_CHANNELS > 18)
|
begin
|
begin
|
wire locked_signal_18;
|
wire locked_signal_18;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_18(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_18(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_18),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_18),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_18),// output
|
.pll_powerdown(pll_powerdown_sqcnr_18),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_18),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_18),// output
|
| Line 5565... |
Line 6147... |
altera_tse_reset_synchronizer ch_18_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_18_reset_sync_0 (
|
.clk(rx_pcs_clk_c18),
|
.clk(rx_pcs_clk_c18),
|
.reset_in(rx_digitalreset_sqcnr_18),
|
.reset_in(rx_digitalreset_sqcnr_18),
|
.reset_out(reset_rx_pcs_clk_c18_int)
|
.reset_out(reset_rx_pcs_clk_c18_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
|
(
|
(
|
.clk(rx_pcs_clk_c18),
|
.clk(rx_pcs_clk_c18),
|
.reset(reset_rx_pcs_clk_c18_int),
|
.reset(reset_rx_pcs_clk_c18_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5643... |
Line 6226... |
assign reconfig_fromgxb_18 = {17{1'b0}};
|
assign reconfig_fromgxb_18 = {17{1'b0}};
|
assign led_char_err_gx[18] = 1'b0;
|
assign led_char_err_gx[18] = 1'b0;
|
assign link_status[18] = 1'b0;
|
assign link_status[18] = 1'b0;
|
assign led_disp_err_18 = 1'b0;
|
assign led_disp_err_18 = 1'b0;
|
assign txp_18 = 1'b0;
|
assign txp_18 = 1'b0;
|
assign pcs_clk_c18 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5681... |
Line 6263... |
gxb_pwrdn_in_sig_clk_19 = gxb_pwrdn_in_sig[19];
|
gxb_pwrdn_in_sig_clk_19 = gxb_pwrdn_in_sig[19];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 19)
|
generate if (MAX_CHANNELS > 19)
|
begin
|
begin
|
wire locked_signal_19;
|
wire locked_signal_19;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_19(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_19(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_19),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_19),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_19),// output
|
.pll_powerdown(pll_powerdown_sqcnr_19),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_19),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_19),// output
|
| Line 5719... |
Line 6300... |
altera_tse_reset_synchronizer ch_19_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_19_reset_sync_0 (
|
.clk(rx_pcs_clk_c19),
|
.clk(rx_pcs_clk_c19),
|
.reset_in(rx_digitalreset_sqcnr_19),
|
.reset_in(rx_digitalreset_sqcnr_19),
|
.reset_out(reset_rx_pcs_clk_c19_int)
|
.reset_out(reset_rx_pcs_clk_c19_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
|
(
|
(
|
.clk(rx_pcs_clk_c19),
|
.clk(rx_pcs_clk_c19),
|
.reset(reset_rx_pcs_clk_c19_int),
|
.reset(reset_rx_pcs_clk_c19_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5775... |
Line 6357... |
.rx_seriallpbken (sd_loopback_19),
|
.rx_seriallpbken (sd_loopback_19),
|
.rx_syncstatus (rx_syncstatus[19]),
|
.rx_syncstatus (rx_syncstatus[19]),
|
.tx_clkout (tx_pcs_clk_c19),
|
.tx_clkout (tx_pcs_clk_c19),
|
.tx_ctrlenable (tx_kchar_19),
|
.tx_ctrlenable (tx_kchar_19),
|
.tx_datain (tx_frame_19),
|
.tx_datain (tx_frame_19),
|
.tx_dataout (txp_19),
|
|
.rx_freqlocked (rx_freqlocked_19),
|
.rx_freqlocked (rx_freqlocked_19),
|
|
.tx_dataout (txp_19),
|
.tx_digitalreset (tx_digitalreset_sqcnr_19),
|
.tx_digitalreset (tx_digitalreset_sqcnr_19),
|
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
|
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
|
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
|
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
|
.rx_runningdisp(rx_runningdisp[19]),
|
.rx_runningdisp(rx_runningdisp[19]),
|
.pll_powerdown(gxb_pwrdn_in_sig[19]),
|
.pll_powerdown(gxb_pwrdn_in_sig[19]),
|
| Line 5797... |
Line 6379... |
assign reconfig_fromgxb_19 = {17{1'b0}};
|
assign reconfig_fromgxb_19 = {17{1'b0}};
|
assign led_char_err_gx[19] = 1'b0;
|
assign led_char_err_gx[19] = 1'b0;
|
assign link_status[19] = 1'b0;
|
assign link_status[19] = 1'b0;
|
assign led_disp_err_19 = 1'b0;
|
assign led_disp_err_19 = 1'b0;
|
assign txp_19 = 1'b0;
|
assign txp_19 = 1'b0;
|
assign pcs_clk_c19 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5835... |
Line 6416... |
gxb_pwrdn_in_sig_clk_20 = gxb_pwrdn_in_sig[20];
|
gxb_pwrdn_in_sig_clk_20 = gxb_pwrdn_in_sig[20];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 20)
|
generate if (MAX_CHANNELS > 20)
|
begin
|
begin
|
wire locked_signal_20;
|
wire locked_signal_20;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_20(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_20(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_20),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_20),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_20),// output
|
.pll_powerdown(pll_powerdown_sqcnr_20),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_20),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_20),// output
|
| Line 5873... |
Line 6453... |
altera_tse_reset_synchronizer ch_20_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_20_reset_sync_0 (
|
.clk(rx_pcs_clk_c20),
|
.clk(rx_pcs_clk_c20),
|
.reset_in(rx_digitalreset_sqcnr_20),
|
.reset_in(rx_digitalreset_sqcnr_20),
|
.reset_out(reset_rx_pcs_clk_c20_int)
|
.reset_out(reset_rx_pcs_clk_c20_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
|
(
|
(
|
.clk(rx_pcs_clk_c20),
|
.clk(rx_pcs_clk_c20),
|
.reset(reset_rx_pcs_clk_c20_int),
|
.reset(reset_rx_pcs_clk_c20_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 5951... |
Line 6532... |
assign reconfig_fromgxb_20 = {17{1'b0}};
|
assign reconfig_fromgxb_20 = {17{1'b0}};
|
assign led_char_err_gx[20] = 1'b0;
|
assign led_char_err_gx[20] = 1'b0;
|
assign link_status[20] = 1'b0;
|
assign link_status[20] = 1'b0;
|
assign led_disp_err_20 = 1'b0;
|
assign led_disp_err_20 = 1'b0;
|
assign txp_20 = 1'b0;
|
assign txp_20 = 1'b0;
|
assign pcs_clk_c20 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 5989... |
Line 6569... |
gxb_pwrdn_in_sig_clk_21 = gxb_pwrdn_in_sig[21];
|
gxb_pwrdn_in_sig_clk_21 = gxb_pwrdn_in_sig[21];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 21)
|
generate if (MAX_CHANNELS > 21)
|
begin
|
begin
|
wire locked_signal_21;
|
wire locked_signal_21;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_21(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_21(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_21),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_21),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_21),// output
|
.pll_powerdown(pll_powerdown_sqcnr_21),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_21),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_21),// output
|
.rx_analogreset(rx_analogreset_sqcnr_21),// output
|
.rx_analogreset(rx_analogreset_sqcnr_21),// output
|
.rx_digitalreset(rx_digitalreset_sqcnr_21),// output
|
.rx_digitalreset(rx_digitalreset_sqcnr_21),// output
|
.gxb_powerdown(gxb_powerdown_sqcnr_21),// output
|
.gxb_powerdown(gxb_powerdown_sqcnr_21),// output
|
.pll_is_locked(pll_locked_21),
|
.pll_is_locked(locked_signal_21),
|
.rx_is_lockedtodata(rx_freqlocked_21),
|
.rx_is_lockedtodata(rx_freqlocked_21),
|
.manual_mode(1'b0),
|
.manual_mode(1'b0),
|
.rx_oc_busy(reconfig_busy_21)
|
.rx_oc_busy(reconfig_busy_21)
|
);
|
);
|
assign locked_signal_21 = (reset? 1'b0: pll_locked_21);
|
assign locked_signal_21 = (reset? 1'b0: pll_locked_21);
|
| Line 6027... |
Line 6606... |
altera_tse_reset_synchronizer ch_21_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_21_reset_sync_0 (
|
.clk(rx_pcs_clk_c21),
|
.clk(rx_pcs_clk_c21),
|
.reset_in(rx_digitalreset_sqcnr_21),
|
.reset_in(rx_digitalreset_sqcnr_21),
|
.reset_out(reset_rx_pcs_clk_c21_int)
|
.reset_out(reset_rx_pcs_clk_c21_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
|
(
|
(
|
.clk(rx_pcs_clk_c21),
|
.clk(rx_pcs_clk_c21),
|
.reset(reset_rx_pcs_clk_c21_int),
|
.reset(reset_rx_pcs_clk_c21_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 6105... |
Line 6685... |
assign reconfig_fromgxb_21 = {17{1'b0}};
|
assign reconfig_fromgxb_21 = {17{1'b0}};
|
assign led_char_err_gx[21] = 1'b0;
|
assign led_char_err_gx[21] = 1'b0;
|
assign link_status[21] = 1'b0;
|
assign link_status[21] = 1'b0;
|
assign led_disp_err_21 = 1'b0;
|
assign led_disp_err_21 = 1'b0;
|
assign txp_21 = 1'b0;
|
assign txp_21 = 1'b0;
|
assign pcs_clk_c21 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 6143... |
Line 6722... |
gxb_pwrdn_in_sig_clk_22 = gxb_pwrdn_in_sig[22];
|
gxb_pwrdn_in_sig_clk_22 = gxb_pwrdn_in_sig[22];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 22)
|
generate if (MAX_CHANNELS > 22)
|
begin
|
begin
|
wire locked_signal_22;
|
wire locked_signal_22;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_22(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_22(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_22),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_22),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_22),// output
|
.pll_powerdown(pll_powerdown_sqcnr_22),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_22),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_22),// output
|
.rx_analogreset(rx_analogreset_sqcnr_22),// output
|
.rx_analogreset(rx_analogreset_sqcnr_22),// output
|
.rx_digitalreset(rx_digitalreset_sqcnr_22),// output
|
.rx_digitalreset(rx_digitalreset_sqcnr_22),// output
|
.gxb_powerdown(gxb_powerdown_sqcnr_22),// output
|
.gxb_powerdown(gxb_powerdown_sqcnr_22),// output
|
.pll_is_locked(pll_locked_22),
|
.pll_is_locked(locked_signal_22),
|
.rx_is_lockedtodata(rx_freqlocked_22),
|
.rx_is_lockedtodata(rx_freqlocked_22),
|
.manual_mode(1'b0),
|
.manual_mode(1'b0),
|
.rx_oc_busy(reconfig_busy_22)
|
.rx_oc_busy(reconfig_busy_22)
|
);
|
);
|
assign locked_signal_22 = (reset? 1'b0: pll_locked_22);
|
assign locked_signal_22 = (reset? 1'b0: pll_locked_22);
|
| Line 6181... |
Line 6759... |
altera_tse_reset_synchronizer ch_22_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_22_reset_sync_0 (
|
.clk(rx_pcs_clk_c22),
|
.clk(rx_pcs_clk_c22),
|
.reset_in(rx_digitalreset_sqcnr_22),
|
.reset_in(rx_digitalreset_sqcnr_22),
|
.reset_out(reset_rx_pcs_clk_c22_int)
|
.reset_out(reset_rx_pcs_clk_c22_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
|
(
|
(
|
.clk(rx_pcs_clk_c22),
|
.clk(rx_pcs_clk_c22),
|
.reset(reset_rx_pcs_clk_c22_int),
|
.reset(reset_rx_pcs_clk_c22_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 6259... |
Line 6838... |
assign reconfig_fromgxb_22 = {17{1'b0}};
|
assign reconfig_fromgxb_22 = {17{1'b0}};
|
assign led_char_err_gx[22] = 1'b0;
|
assign led_char_err_gx[22] = 1'b0;
|
assign link_status[22] = 1'b0;
|
assign link_status[22] = 1'b0;
|
assign led_disp_err_22 = 1'b0;
|
assign led_disp_err_22 = 1'b0;
|
assign txp_22 = 1'b0;
|
assign txp_22 = 1'b0;
|
assign pcs_clk_c22 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
| Line 6297... |
Line 6875... |
gxb_pwrdn_in_sig_clk_23 = gxb_pwrdn_in_sig[23];
|
gxb_pwrdn_in_sig_clk_23 = gxb_pwrdn_in_sig[23];
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
generate if (MAX_CHANNELS > 23)
|
generate if (MAX_CHANNELS > 23)
|
begin
|
begin
|
wire locked_signal_23;
|
wire locked_signal_23;
|
// Reset logic used to reset the PMA blocks
|
|
// ----------------------------------------
|
|
// ALTGX Reset Sequencer
|
// ALTGX Reset Sequencer
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_23(
|
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_23(
|
// User inputs and outputs
|
// User inputs and outputs
|
.clock(clk),
|
.clock(clk),
|
.reset_all(reset|gxb_pwrdn_in_sig_clk_23),
|
.reset_all(reset_start | gxb_pwrdn_in_sig_clk_23),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_tx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
//.reset_rx_digital(reset_ref_clk),
|
.powerdown_all(reset_posedge),
|
.powerdown_all(reset_sync),
|
.tx_ready(), // output
|
.tx_ready(), // output
|
.rx_ready(), // output
|
.rx_ready(), // output
|
// I/O transceiver and status
|
// I/O transceiver and status
|
.pll_powerdown(pll_powerdown_sqcnr_23),// output
|
.pll_powerdown(pll_powerdown_sqcnr_23),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_23),// output
|
.tx_digitalreset(tx_digitalreset_sqcnr_23),// output
|
| Line 6335... |
Line 6912... |
altera_tse_reset_synchronizer ch_23_reset_sync_0 (
|
altera_tse_reset_synchronizer ch_23_reset_sync_0 (
|
.clk(rx_pcs_clk_c23),
|
.clk(rx_pcs_clk_c23),
|
.reset_in(rx_digitalreset_sqcnr_23),
|
.reset_in(rx_digitalreset_sqcnr_23),
|
.reset_out(reset_rx_pcs_clk_c23_int)
|
.reset_out(reset_rx_pcs_clk_c23_int)
|
);
|
);
|
|
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
|
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
|
(
|
(
|
.clk(rx_pcs_clk_c23),
|
.clk(rx_pcs_clk_c23),
|
.reset(reset_rx_pcs_clk_c23_int),
|
.reset(reset_rx_pcs_clk_c23_int),
|
//input (from alt2gxb)
|
//input (from alt2gxb)
|
| Line 6413... |
Line 6991... |
assign reconfig_fromgxb_23 = {17{1'b0}};
|
assign reconfig_fromgxb_23 = {17{1'b0}};
|
assign led_char_err_gx[23] = 1'b0;
|
assign led_char_err_gx[23] = 1'b0;
|
assign link_status[23] = 1'b0;
|
assign link_status[23] = 1'b0;
|
assign led_disp_err_23 = 1'b0;
|
assign led_disp_err_23 = 1'b0;
|
assign txp_23 = 1'b0;
|
assign txp_23 = 1'b0;
|
assign pcs_clk_c23 = 1'b0;
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
