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//
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//
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// $RCSfile: altera_tse_pcs_pma_gige.v,v $
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// $RCSfile: altera_tse_pcs_pma_gige.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma_gige.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma_gige.v,v $
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//
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//
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// $Date: 2012/06/21 $
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// Check in by : $Author: max $
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// Check in by : $Author: swbranch $
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// Author : Arul Paniandi
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// Author : Arul Paniandi
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//
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//
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// Project : Triple Speed Ethernet
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// Project : Triple Speed Ethernet
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//
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//
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// Description :
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// Description :
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defparam
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defparam
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altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
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altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
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altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
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altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
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altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
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altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
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//Resets the Reset Sequencer for the rising edge of Reset signal
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// ---------------------------------------------------------------
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// Based on PHYIP , when user assert reset - it hold the reset sequencer block in reset.
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reg reset_p1, reset_p2;
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// , reset sequencing only start then reset_sequnece end.
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reg reset_posedge;
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wire reset_sync;
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always@(posedge clk)
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reg reset_start;
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begin
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reset_p1 <= reset;
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altera_tse_reset_synchronizer reset_sync_u0 (
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reset_p2 <= reset_p1;
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.clk(clk),
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reset_posedge <= reset_p1 & ~reset_p2;
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.reset_in(reset),
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.reset_out(reset_sync)
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);
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always@(posedge clk or posedge reset_sync) begin
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if (reset_sync) begin
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reset_start <= 1'b1;
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end
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else begin
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reset_start <= 1'b0;
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end
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end
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end
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// Export powerdown signal or wire it internally
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// Export powerdown signal or wire it internally
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// ---------------------------------------------
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// ---------------------------------------------
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reg data_in_d1,gxb_pwrdn_in_sig_clk;
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reg data_in_d1,gxb_pwrdn_in_sig_clk;
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generate if (EXPORT_PWRDN == 1)
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generate if (EXPORT_PWRDN == 1)
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// ----------------------------------------
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// ----------------------------------------
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// ALTGX Reset Sequencer
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// ALTGX Reset Sequencer
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altera_tse_reset_sequencer altera_tse_reset_sequencer_inst(
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altera_tse_reset_sequencer altera_tse_reset_sequencer_inst(
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// User inputs and outputs
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// User inputs and outputs
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.clock(clk),
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.clock(clk),
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.reset_all(reset | gxb_pwrdn_in_sig_clk),
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.reset_all(reset_start | gxb_pwrdn_in_sig_clk),
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//.reset_tx_digital(reset_ref_clk),
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//.reset_tx_digital(reset_ref_clk),
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//.reset_rx_digital(reset_ref_clk),
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//.reset_rx_digital(reset_ref_clk),
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.powerdown_all(reset_posedge),
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.powerdown_all(reset_sync),
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.tx_ready(), // output
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.tx_ready(), // output
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.rx_ready(), // output
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.rx_ready(), // output
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// I/O transceiver and status
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// I/O transceiver and status
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.pll_powerdown(pll_powerdown_sqcnr),// output
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.pll_powerdown(pll_powerdown_sqcnr),// output
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.tx_digitalreset(tx_digitalreset_sqcnr),// output
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.tx_digitalreset(tx_digitalreset_sqcnr),// output
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