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| Rev 9 |
Rev 20 |
| Line 85... |
Line 85... |
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// rinit state bit, triggered by spulse, waits while rhold = 1
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// rinit state bit, triggered by spulse, waits while rhold = 1
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assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
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assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
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always @(posedge clock or posedge aclr)
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always @(posedge clock or posedge aclr)
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if (aclr == 1'b1)
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if (aclr == 1'b1)
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rinit <= 0;
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rinit <= 1;
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else
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else
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rinit <= rinit_next;
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rinit <= rinit_next;
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// optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
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// optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
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generate
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generate
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| Line 174... |
Line 174... |
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if (reset_hold_cycles == 1)
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if (reset_hold_cycles == 1)
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// a single-cycle reset pulse needs 1 register
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// a single-cycle reset pulse needs 1 register
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always @(posedge clock or posedge aclr)
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always @(posedge clock or posedge aclr)
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if (aclr == 1'b1)
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if (aclr == 1'b1)
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zspulse <= 0;
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zspulse <= 1;
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else
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else
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zspulse <= spulse;
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zspulse <= spulse;
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else begin
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else begin
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// multi-cycle reset pulse needs a counter
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// multi-cycle reset pulse needs a counter
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always @(posedge clock or posedge aclr)
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always @(posedge clock or posedge aclr)
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begin
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begin
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if (aclr == 1'b1)
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if (aclr == 1'b1)
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zspulse <= 0;
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zspulse <= {rhc_bits + 1 { 1'b1}};
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else if (spulse == 1)
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else if (spulse == 1)
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zspulse <= rhc_load_constant[rhc_bits:0];
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zspulse <= rhc_load_constant[rhc_bits:0];
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else if (zspulse[rhc_bits] == 1)
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else if (zspulse[rhc_bits] == 1)
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zspulse <= zspulse - 1'b1;
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zspulse <= zspulse - 1'b1;
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end
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end
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