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--
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--
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--
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-- This file is a part of JOP, the Java Optimized Processor
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--
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-- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- sc_pack.vhd
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-- sc_pack.vhd
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--
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--
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-- Package for SimpCon defines
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-- Package for SimpCon defines
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--
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--
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-- Author: Martin Schoeberl (martin@jopdesign.com)
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-- Author: Martin Schoeberl (martin@jopdesign.com)
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--
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--
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-- 2007-03-16 first version
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-- 2007-03-16 first version
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--
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--
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--
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--
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library std;
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use std.textio.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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package sc_pack is
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package sc_pack is
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constant MEM_ADDR_SIZE : integer := 21;
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-- two more bits than needed for the main memory
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constant IO_ADDR_SIZE : integer := 7;
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-- one to distinguishe between memory and IO access
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-- one more to allow memory mirroring for size auto
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-- detection at boot time
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constant SC_ADDR_SIZE : integer := 23;
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constant RDY_CNT_SIZE : integer := 2;
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constant RDY_CNT_SIZE : integer := 2;
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type sc_mem_out_type is record
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type sc_out_type is record
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address : std_logic_vector(MEM_ADDR_SIZE-1 downto 0);
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address : std_logic_vector(SC_ADDR_SIZE-1 downto 0);
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wr_data : std_logic_vector(31 downto 0);
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rd : std_logic;
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wr : std_logic;
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end record;
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type sc_io_out_type is record
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address : std_logic_vector(IO_ADDR_SIZE-1 downto 0);
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wr_data : std_logic_vector(31 downto 0);
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wr_data : std_logic_vector(31 downto 0);
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rd : std_logic;
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rd : std_logic;
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wr : std_logic;
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wr : std_logic;
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atomic : std_logic;
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nc : std_logic;
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end record;
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end record;
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type sc_in_type is record
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type sc_in_type is record
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rd_data : std_logic_vector(31 downto 0);
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rd_data : std_logic_vector(31 downto 0);
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rdy_cnt : unsigned(RDY_CNT_SIZE-1 downto 0);
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rdy_cnt : unsigned(RDY_CNT_SIZE-1 downto 0);
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end record;
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end record;
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type sc_io_out_array_type is array (integer range <>) of sc_io_out_type;
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type sc_out_array_type is array (integer range <>) of sc_out_type;
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type sc_in_array_type is array (integer range <>) of sc_in_type;
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type sc_in_array_type is array (integer range <>) of sc_in_type;
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constant TIMEOUT : integer := 50;
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procedure sc_write(
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signal clk : in std_logic;
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constant addr : in natural;
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constant data : in natural;
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signal sc_out : out sc_out_type;
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signal sc_in : in sc_in_type);
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procedure sc_read(
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signal clk : in std_logic;
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constant addr : in natural;
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variable data : out natural;
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signal sc_out : out sc_out_type;
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signal sc_in : in sc_in_type);
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end sc_pack;
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package body sc_pack is
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procedure sc_write(
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signal clk : in std_logic;
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constant addr : in natural;
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constant data : in natural;
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signal sc_out : out sc_out_type;
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signal sc_in : in sc_in_type) is
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variable txt : line;
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begin
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write(txt, now, right, 8);
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write(txt, string'(" wrote "));
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write(txt, data);
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write(txt, string'(" to addr. "));
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write(txt, addr);
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sc_out.wr_data <= std_logic_vector(to_unsigned(data, sc_out.wr_data'length));
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sc_out.address <= std_logic_vector(to_unsigned(addr, sc_out.address'length));
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sc_out.wr <= '1';
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sc_out.rd <= '0';
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-- one cycle valid
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wait until rising_edge(clk);
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sc_out.wr_data <= (others => 'X');
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sc_out.address <= (others => 'X');
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sc_out.wr <= '0';
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for i in 1 to TIMEOUT loop
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wait until rising_edge(clk);
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exit when sc_in.rdy_cnt = "00";
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if (i = TIMEOUT) then
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write (txt, string'("No acknowledge recevied!"));
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end if;
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end loop;
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writeline(output, txt);
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end;
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procedure sc_read(
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signal clk : in std_logic;
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constant addr : in natural;
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variable data : out natural;
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signal sc_out : out sc_out_type;
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signal sc_in : in sc_in_type) is
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variable txt : line;
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variable in_data : natural;
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begin
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write(txt, now, right, 8);
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write(txt, string'(" read from addr. "));
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write(txt, addr);
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writeline(output, txt);
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sc_out.address <= std_logic_vector(to_unsigned(addr, sc_out.address'length));
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sc_out.wr_data <= (others => 'X');
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sc_out.wr <= '0';
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sc_out.rd <= '1';
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-- one cycle valid
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wait until rising_edge(clk);
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sc_out.address <= (others => 'X');
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sc_out.rd <= '0';
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-- wait for acknowledge
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for i in 1 to TIMEOUT loop
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wait until rising_edge(clk);
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exit when sc_in.rdy_cnt = "00";
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if (i = TIMEOUT) then
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write (txt, string'("No acknowledge recevied!"));
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end if;
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end loop;
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in_data := to_integer(unsigned(sc_in.rd_data));
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data := in_data;
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write(txt, now, right, 8);
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write(txt, string'(" value: "));
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write(txt, in_data);
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writeline(output, txt);
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end;
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end sc_pack;
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end sc_pack;
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