| Line 1... |
Line 1... |
--
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--
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--
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-- This file is a part of JOP, the Java Optimized Processor
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--
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-- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- sc_sys.vhd
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-- sc_sys.vhd
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--
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--
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-- counter, interrrupt handling and watchdog bit
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-- counter, interrrupt handling and watchdog bit
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--
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--
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-- Author: Martin Schoeberl martin@good-ear.com
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-- Author: Martin Schoeberl martin@jopdesign.com
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--
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--
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-- address map:
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-- address map:
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--
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--
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-- 0 read clk counter, write irq ena
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-- 0 read clk counter, write irq ena
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-- 1 read 1 MHz counter, write timer val (us) + irq ack
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-- 1 read 1 MHz counter, write timer val (us)
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-- 2 write generates sw-int (for yield())
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-- 2 write generates sw-int (for yield())
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-- 3 write wd port
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-- 3 write wd port
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-- 4 write generates SW exception, read exception reason
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-- 4 write generates SW exception, read exception reason
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--
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--
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-- todo:
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-- todo:
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| Line 20... |
Line 41... |
-- 2003-08-15 us counter, irq added
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-- 2003-08-15 us counter, irq added
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-- 2005-11-30 change interface to SimpCon
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-- 2005-11-30 change interface to SimpCon
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-- 2006-01-11 added exception
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-- 2006-01-11 added exception
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-- 2007-03-17 changed interrupts to records
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-- 2007-03-17 changed interrupts to records
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-- 2007-06-01 changed name from sc_cnt to sc_sys
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-- 2007-06-01 changed name from sc_cnt to sc_sys
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-- 2007-11-22 added global lock and bootup of CMP
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-- 2007-12-03 prioritized interrupt processing
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-- 2007-12-07 global lock redesign
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--
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-- state for a single interrupt
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity intstate is
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port (
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clk : in std_logic;
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reset : in std_logic;
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irq : in std_logic; -- external request
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ena : in std_logic; -- local enable
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ack : in std_logic; -- is served
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clear : in std_logic; -- reset pending interrupt
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pending : out std_logic -- the output request
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);
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end intstate;
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architecture rtl of intstate is
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signal flag : std_logic;
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begin
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-- TODO: add minimum interarrival time
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process(clk, reset) begin
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if reset='1' then
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flag <= '0';
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elsif rising_edge(clk) then
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if ack='1' or clear='1' then
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flag <= '0';
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elsif irq='1' then
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flag <= '1';
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end if;
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end if;
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end process;
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pending <= flag and ena;
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end rtl;
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--
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-- the sc_sys component
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.jop_types.all;
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use work.jop_types.all;
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entity sc_sys is
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entity sc_sys is
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generic (addr_bits : integer;
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generic (addr_bits : integer;
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clk_freq : integer;
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clk_freq : integer;
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cpu_id : integer);
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cpu_id : integer;
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cpu_cnt : integer;
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num_io_int : integer := 2); -- a default value to play with SW interrupts
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- SimpCon interface
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-- SimpCon interface
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| Line 48... |
Line 124... |
rdy_cnt : out unsigned(1 downto 0);
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rdy_cnt : out unsigned(1 downto 0);
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--
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--
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-- Interrupts from IO devices
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-- Interrupts from IO devices
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--
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--
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irq_in : out irq_in_type;
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irq_in : out irq_bcf_type;
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irq_out : in irq_ack_type;
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exc_req : in exception_type;
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exc_req : in exception_type;
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sync_out : in sync_out_type;
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io_int : in std_logic_vector(num_io_int-1 downto 0) := "00";
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sync_out : in sync_out_type := NO_SYNC;
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sync_in : out sync_in_type;
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sync_in : out sync_in_type;
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wd : out std_logic
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wd : out std_logic;
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-- remove the comment for RAM access counting
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-- ram_count : in std_logic;
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inval : out std_logic
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);
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);
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end sc_sys ;
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end sc_sys ;
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architecture rtl of sc_sys is
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architecture rtl of sc_sys is
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| Line 68... |
Line 152... |
signal us_cnt : std_logic_vector(31 downto 0);
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signal us_cnt : std_logic_vector(31 downto 0);
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constant div_val : integer := clk_freq/1000000-1;
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constant div_val : integer := clk_freq/1000000-1;
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signal timer_int : std_logic;
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signal timer_int : std_logic;
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signal yield_int : std_logic;
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signal int_ack : std_logic;
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signal timer : std_logic;
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signal timer_cnt : std_logic_vector(31 downto 0);
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signal yield : std_logic;
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signal irq_cnt : std_logic_vector(31 downto 0);
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signal timer_equ : std_logic;
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signal timer_equ : std_logic;
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signal timer_dly : std_logic;
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signal timer_dly : std_logic;
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signal exc_type : std_logic_vector(7 downto 0);
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signal exc_type : std_logic_vector(7 downto 0);
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signal cpu_identity : std_logic_vector(31 downto 0);
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signal cpu_identity : std_logic_vector(31 downto 0);
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signal lock_reqest : std_logic;
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-- remove the comment for RAM access counting
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-- signal ram_counter : std_logic_vector(31 downto 0);
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signal cnt_ena : unsigned(31 downto 0);
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--
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-- signals for interrupt handling
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--
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signal int_pend : std_logic;
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signal int_ena : std_logic;
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signal exc_pend : std_logic;
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signal irq_gate : std_logic;
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signal irq_dly : std_logic;
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signal exc_dly : std_logic;
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--
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-- signals for interrupt source state machines
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--
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constant NUM_INT : integer := num_io_int+1; -- plus timer interrupt
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signal hwreq : std_logic_vector(NUM_INT-1 downto 0);
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signal swreq : std_logic_vector(NUM_INT-1 downto 0);
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signal intreq : std_logic_vector(NUM_INT-1 downto 0);
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signal mask : std_logic_vector(NUM_INT-1 downto 0);
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signal ack : std_logic_vector(NUM_INT-1 downto 0);
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signal pending : std_logic_vector(NUM_INT-1 downto 0);
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signal prioint : std_logic_vector(4 downto 0);
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signal intnr : std_logic_vector(4 downto 0); -- processing int number
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signal clearall : std_logic;
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begin
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begin
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cpu_identity <= std_logic_vector(to_unsigned(cpu_id,32));
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cpu_identity <= std_logic_vector(to_unsigned(cpu_id,32));
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rdy_cnt <= "00"; -- no wait states
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rdy_cnt <= "11" when (sync_out.halted='1' and lock_reqest='1') else "00";
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--
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--
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-- read cnt values
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-- read cnt values
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--
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--
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process(clk, reset)
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process(clk, reset)
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begin
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begin
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if (reset='1') then
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if reset='1' then
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rd_data <= (others => '0');
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rd_data <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if rd='1' then
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if rd='1' then
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case address(2 downto 0) is
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case address(3 downto 0) is
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when "000" =>
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when "0000" =>
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rd_data <= clock_cnt;
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rd_data <= clock_cnt;
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when "001" =>
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when "0001" =>
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rd_data <= us_cnt;
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rd_data <= us_cnt;
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when "100" =>
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when "0010" =>
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rd_data(4 downto 0) <= intnr;
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rd_data(31 downto 5) <= (others => '0');
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when "0100" =>
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rd_data(7 downto 0) <= exc_type;
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rd_data(7 downto 0) <= exc_type;
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rd_data(31 downto 8) <= (others => '0');
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rd_data(31 downto 8) <= (others => '0');
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when "110" =>
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when "0101" =>
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rd_data(0) <= lock_reqest;
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rd_data(31 downto 1) <= (others => '0');
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when "0110" =>
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rd_data <= cpu_identity;
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rd_data <= cpu_identity;
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-- when "111" =>
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when "0111" =>
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when others =>
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rd_data(0) <= sync_out.s_out;
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rd_data(0) <= sync_out.s_out;
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rd_data(31 downto 1) <= (others => '0');
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rd_data(31 downto 1) <= (others => '0');
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-- remove the comment for RAM access counting
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-- when "1010" =>
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-- rd_data(31 downto 0) <= ram_counter;
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when "1011" =>
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rd_data <= std_logic_vector(to_unsigned(cpu_cnt, 32));
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when "1111" =>
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-- nothing, cache inval is write only
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when others =>
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-- nothing
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--
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--
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-- compare timer value and us counter
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-- compare timer value and us counter
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-- and generate single shot
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-- and generate single shot
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--
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--
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process(us_cnt, irq_cnt) begin
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process(us_cnt, timer_cnt) begin
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timer_equ <= '0';
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timer_equ <= '0';
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if us_cnt = irq_cnt then
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if us_cnt = timer_cnt then
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timer_equ <= '1';
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timer_equ <= '1';
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end if;
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end if;
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end process;
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end process;
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process(clk, reset, timer_equ) begin
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process(clk, reset) begin
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if (reset='1') then
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if reset='1' then
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timer_dly <= '0';
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timer_dly <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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timer_dly <= timer_equ;
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timer_dly <= timer_equ;
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end if;
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end if;
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end process;
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end process;
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| Line 143... |
Line 266... |
timer_int <= timer_equ and not timer_dly;
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timer_int <= timer_equ and not timer_dly;
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--
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--
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-- int processing from timer and yield request
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-- int processing from timer and yield request
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--
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--
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process(clk, reset, timer_int, yield_int) begin
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if (reset='1') then
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hwreq(0) <= timer_int;
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timer <= '0';
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hwreq(NUM_INT-1 downto 1) <= io_int;
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yield <= '0';
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elsif rising_edge(clk) then
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process(prioint, irq_out.ack_irq) begin
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if int_ack='1' then
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ack <= (others => '0');
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timer <= '0';
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ack(to_integer(unsigned(prioint))) <= irq_out.ack_irq;
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yield <= '0';
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end process;
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else
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if timer_int='1' then
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gen_int: for i in 0 to NUM_INT-1 generate
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timer <= '1';
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intreq(i) <= hwreq(i) or swreq(i);
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end if;
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cis: entity work.intstate
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if yield_int='1' then
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port map(clk, reset,
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yield <= '1';
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irq => intreq(i),
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ena => mask(i),
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ack => ack(i),
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clear => clearall,
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pending => pending(i)
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);
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end generate;
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-- find highest priority pending interrupt
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process(pending) begin
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int_pend <= '0';
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prioint <= (others => '0');
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for i in NUM_INT-1 downto 0 loop
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if pending(i)='1' then
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int_pend <= '1';
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prioint <= std_logic_vector(to_unsigned(i, 5));
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exit;
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end if;
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end if;
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end loop;
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end process;
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|
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--
|
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-- interrupt processing
|
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--
|
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process(clk, reset) begin
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|
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if reset='1' then
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irq_dly <= '0';
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exc_dly <= '0';
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intnr <= (others => '0');
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elsif rising_edge(clk) then
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|
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irq_dly <= irq_gate;
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exc_dly <= exc_pend;
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-- save processing interrupt number
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if irq_out.ack_irq='1' then
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intnr <= prioint;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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irq_in.irq <= timer or yield;
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irq_gate <= int_pend and int_ena;
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irq_in.irq <= irq_gate and not irq_dly;
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irq_in.exc <= exc_pend and not exc_dly;
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irq_in.ena <= int_ena;
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--
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--
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-- counters
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-- counters
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-- pre_scale is 8 bit => fmax = 255 MHz
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-- pre_scale is 8 bit => fmax = 255 MHz
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| Line 199... |
Line 365... |
process(clk, reset)
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process(clk, reset)
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|
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begin
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begin
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if (reset='1') then
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if (reset='1') then
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|
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irq_in.irq_ena <= '0';
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int_ena <= '0';
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irq_cnt <= (others => '0');
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timer_cnt <= (others => '0');
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int_ack <= '0';
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wd <= '0';
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wd <= '0';
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sync_in.s_in <= '0';
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sync_in.s_in <= '0';
|
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sync_in.lock_req <= '0';
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lock_reqest <= '0';
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exc_type <= (others => '0');
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exc_type <= (others => '0');
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irq_in.exc_int <= '0';
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exc_pend <= '0';
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|
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swreq <= (others => '0');
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mask <= (others => '0');
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clearall <= '0';
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|
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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|
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int_ack <= '0';
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exc_pend <= '0';
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yield_int <= '0';
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swreq <= (others => '0');
|
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clearall <= '0';
|
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inval <= '0';
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|
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irq_in.exc_int <= '0';
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-- disable interrupts on a taken interrupt or excption
|
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if irq_out.ack_irq='1' or irq_out.ack_exc='1' then
|
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int_ena <= '0';
|
|
end if;
|
|
|
|
-- exceptions from core or memory
|
if exc_req.spov='1' then
|
if exc_req.spov='1' then
|
exc_type(2 downto 0) <= EXC_SPOV;
|
exc_type(2 downto 0) <= EXC_SPOV;
|
irq_in.exc_int <= '1';
|
exc_pend <= '1';
|
end if;
|
end if;
|
if exc_req.np='1' then
|
if exc_req.np='1' then
|
exc_type(2 downto 0) <= EXC_NP;
|
exc_type(2 downto 0) <= EXC_NP;
|
irq_in.exc_int <= '1';
|
exc_pend <= '1';
|
end if;
|
end if;
|
if exc_req.ab='1' then
|
if exc_req.ab='1' then
|
exc_type(2 downto 0) <= EXC_AB;
|
exc_type(2 downto 0) <= EXC_AB;
|
irq_in.exc_int <= '1';
|
exc_pend <= '1';
|
end if;
|
end if;
|
|
|
if wr='1' then
|
if wr='1' then
|
case address(2 downto 0) is
|
case address(3 downto 0) is
|
when "000" =>
|
when "0000" =>
|
irq_in.irq_ena <= wr_data(0);
|
int_ena <= wr_data(0);
|
when "001" =>
|
when "0001" =>
|
irq_cnt <= wr_data;
|
timer_cnt <= wr_data;
|
int_ack <= '1';
|
when "0010" =>
|
when "010" =>
|
swreq(to_integer(unsigned(wr_data))) <= '1';
|
yield_int <= '1';
|
when "0011" =>
|
when "011" =>
|
|
wd <= wr_data(0);
|
wd <= wr_data(0);
|
when "100" =>
|
when "0100" =>
|
exc_type <= wr_data(7 downto 0);
|
exc_type <= wr_data(7 downto 0);
|
irq_in.exc_int <= '1';
|
exc_pend <= '1';
|
when "110" =>
|
when "0101" =>
|
|
sync_in.lock_req <= wr_data(0);
|
|
lock_reqest <= wr_data(0);
|
|
-- implicit cache invalidation on monitorenter
|
|
inval <= wr_data(0);
|
|
when "0110" =>
|
-- nothing, processor id is read only
|
-- nothing, processor id is read only
|
when others =>
|
when "0111" =>
|
-- when "111" =>
|
|
sync_in.s_in <= wr_data(0);
|
sync_in.s_in <= wr_data(0);
|
|
when "1000" =>
|
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mask <= wr_data(NUM_INT-1 downto 0);
|
|
when "1001" =>
|
|
clearall <= '1';
|
|
when "1010" =>
|
|
-- nothing, ram_counter is read only
|
|
when "1111" =>
|
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-- explicit cache invalidation
|
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inval <= '1';
|
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
-- remove the comment for RAM access counting
|
|
-- process(clk, reset)
|
|
-- begin
|
|
-- if reset = '1' then
|
|
-- ram_counter <= (others => '0');
|
|
-- elsif rising_edge(clk) then
|
|
-- if (ram_count='0') then
|
|
-- ram_counter <= std_logic_vector(unsigned(ram_counter) + 1);
|
|
-- end if;
|
|
-- end if;
|
|
-- end process;
|
|
|
end rtl;
|
end rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
