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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 41...	Line 41...






	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`configuration`
	`ctrl_default`


	`dest_dir`
	`io_ports`











Line 54...	Line 74...
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`configuration`
`ctrl_default`


`destination`	`destination`
`top.ctrl`	`top.ctrl`


`dest_dir`	`dest_dir`
Line 146...	Line 162...






`VEC_TABLE8'hff`









	`Hierarchical`


	`spirit:library="Mos6502"`
	`spirit:name="T6502"`
	`spirit:version="ctrl.design"/>`





`verilog`	`verilog`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
Line 210...	Line 235...








	`VEC_TABLE8'hff`



	`PG0_WIDTH8`
	`PG0_ADDR7`

	`PG0_WORDS128`

	`PG0_WRITETHRU0`


	`PG0_DEFAULT8'hff`

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