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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 129...	Line 129...







`elab_verilog`	`elab_verilog`
`103.0`	`102.1`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/elab_verilog`	`./tools/verilog/elab_verilog`





`trace_bus`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/trace_bus`


`path`	`configuration`
`root.cpu`	`default`


`bus_name`	`dest_dir`
`cpu`	`io_ports`









`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`configuration`
`default`


`destination`	`destination`
`top`	`top`


`dest_dir`	`dest_dir`
Line 256...	Line 238...







`CPU_ADD16`	`CPU_ADD16`
`RAM_WORDS2048`
`RAM_ADD11`
`ROM_WORDS4096`
`ROM_ADD12`
`PROG_ROM_WORDS4096`
`PROG_ROM_ADD12`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`UART_PRESCALE5'b01100`	`ROM_DEFAULT16'hffff`
`UART_PRE_SIZE5`	`BOOT_ROM_WIDTH16`
`UART_DIV0`	`ROM_WRITETHRU0`
`JTAG_SEL1`









`Hierarchical`	`Hierarchical`

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