URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 135 |
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Mos6502
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Mos6502
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core
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core
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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cpu
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addr
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addr
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150
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rdata
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rdata
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150
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wdata
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wdata
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70
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rd
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rd
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wr
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wr
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cpu
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addr
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addr
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150
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rdata
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rdata
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150
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wdata
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wdata
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70
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rd
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rd
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wr
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wr
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gen_verilog_sim
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gen_verilog_sim
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104.0
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104.0
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none
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none
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:*Simulation:*
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:*Simulation:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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core_def
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core_def
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gen_verilog_syn
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gen_verilog_syn
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104.0
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104.0
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none
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none
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:*Synthesis:*
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:*Synthesis:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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core_def
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core_def
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fs-sim
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fs-sim
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../verilog/copyright.v
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../verilog/copyright.v
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verilogSourceinclude
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verilogSourceinclude
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../verilog/sim/core_def
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../verilog/sim/core_def
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verilogSourcemodule
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verilogSourcemodule
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../verilog/defines
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../verilog/defines
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verilogSourceinclude
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verilogSourceinclude
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alu
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alu
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../verilog/alu
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../verilog/alu
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verilogSourcemodule
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verilogSourcemodule
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alu_logic
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alu_logic
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../verilog/alu_logic
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../verilog/alu_logic
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verilogSourcemodule
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verilogSourcemodule
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control
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control
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../verilog/control
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../verilog/control
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verilogSourcemodule
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verilogSourcemodule
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inst_decode
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inst_decode
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../verilog/inst_decode
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../verilog/inst_decode
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verilogSourcemodule
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verilogSourcemodule
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sequencer
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sequencer
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../verilog/sequencer
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../verilog/sequencer
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verilogSourcemodule
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verilogSourcemodule
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state_fsm
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state_fsm
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../verilog/state_fsm
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../verilog/state_fsm
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verilogSourcemodule
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verilogSourcemodule
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../verilog/top.sim
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../verilog/top.sim
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verilogSourcefragment
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verilogSourcefragment
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../verilog/top.body
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../verilog/top.body
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verilogSourcefragment
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verilogSourcefragment
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fs-syn
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fs-syn
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../verilog/copyright.v
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../verilog/copyright.v
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verilogSourceinclude
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verilogSourceinclude
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../verilog/syn/core_def
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../verilog/syn/core_def
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verilogSourcemodule
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verilogSourcemodule
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../verilog/defines
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../verilog/defines
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verilogSourceinclude
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verilogSourceinclude
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alu
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alu
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../verilog/alu
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../verilog/alu
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verilogSourcemodule
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verilogSourcemodule
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alu_logic
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alu_logic
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../verilog/alu_logic
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../verilog/alu_logic
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verilogSourcemodule
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verilogSourcemodule
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control
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control
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../verilog/control
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../verilog/control
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verilogSourcemodule
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verilogSourcemodule
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inst_decode
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inst_decode
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../verilog/inst_decode
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../verilog/inst_decode
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verilogSourcemodule
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verilogSourcemodule
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sequencer
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sequencer
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../verilog/sequencer
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../verilog/sequencer
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verilogSourcemodule
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verilogSourcemodule
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state_fsm
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state_fsm
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../verilog/state_fsm
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../verilog/state_fsm
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verilogSourcemodule
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verilogSourcemodule
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../verilog/top.body
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../verilog/top.body
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verilogSourcefragment
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verilogSourcefragment
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verilog
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verilog
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spirit:library="Testbench"
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ipxact:library="Testbench"
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spirit:name="toolflow"
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ipxact:name="toolflow"
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spirit:version="verilog"/>
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ipxact:version="verilog"/>
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sim:*Simulation:*
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sim:*Simulation:*
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Verilog
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Verilog
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fs-sim
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fs-sim
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syn:*Synthesis:*
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syn:*Synthesis:*
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Verilog
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Verilog
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fs-syn
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fs-syn
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doc
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doc
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spirit:library="Testbench"
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ipxact:library="Testbench"
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spirit:name="toolflow"
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ipxact:name="toolflow"
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spirit:version="documentation"/>
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ipxact:version="documentation"/>
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:*Documentation:*
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:*Documentation:*
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Verilog
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Verilog
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VEC_TABLE8'hff
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BOOT_VEC8'hfc
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clk
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wire
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in
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enable
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reset
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wire
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wire
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in
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in
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enable
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wire
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in
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nmi
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addr
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wire
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wire
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in
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out
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vec_int
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wire
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in
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70
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wdata
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wire
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out
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prog_data
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wire
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in
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150
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rdata
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wire
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in
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pg0_data
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wire
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in
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70
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alu_status
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wire
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out
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70
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prog_counter
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rd
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wire
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wire
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out
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out
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150
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pg0_add
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wr
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wire
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wire
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out
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out
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70
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pg0_rd
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wire
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out
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pg0_wr
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nmi
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wire
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wire
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out
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in
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vec_int
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wire
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in
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70
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stk_push
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wire
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out
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stk_push_data
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prog_data
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wire
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wire
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out
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in
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150
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150
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stk_pull
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wire
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out
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stk_pull_data
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pg0_data
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wire
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wire
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in
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in
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150
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70
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alu_status
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wire
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out
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70
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prog_counter
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wire
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out
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150
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pg0_add
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wire
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out
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70
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pg0_rd
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wire
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out
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pg0_wr
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wire
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out
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stk_push
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wire
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out
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stk_push_data
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wire
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out
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150
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stk_pull
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wire
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out
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stk_pull_data
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wire
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in
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150
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© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.