URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 134 |
Rev 135 |
| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
Mos6502
|
Mos6502
|
cpu
|
cpu
|
def default
|
def
|
|
|
|
|
|
|
slave_clk
|
slave_clk
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
clk
|
clk
|
|
clk
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
reset
|
reset
|
|
reset
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cpu
|
|
|
|
|
|
|
|
|
cpu
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
addr
|
|
150
|
|
|
|
|
|
|
|
rdata
|
|
rdata
|
|
150
|
|
|
|
|
|
|
|
wdata
|
|
wdata
|
|
70
|
|
|
|
|
|
|
|
rd
|
|
rd
|
|
|
|
|
|
|
|
wr
|
|
wr
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
addr
|
|
150
|
|
|
|
|
|
|
|
rdata
|
|
rdata
|
|
150
|
|
|
|
|
|
|
|
wdata
|
|
wdata
|
|
70
|
|
|
|
|
|
|
|
rd
|
|
rd
|
|
|
|
|
|
|
|
wr
|
|
wr
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cpu
|
cpu
|
0x10000
|
0x10000
|
8
|
8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
gen_verilog_sim
|
104.0
|
104.0
|
none
|
none
|
:*Simulation:*
|
:*Simulation:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
cpu_def
|
cpu_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
../verilog/sim/cpu_def
|
../verilog/sim/cpu_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
../verilog/
|
../verilog/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
../verilog/sim/cpu_def
|
../verilog/sim/cpu_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
../verilog/
|
../verilog/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
spirit:library="Mos6502"
|
|
spirit:name="cpu"
|
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
Hierarchical
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
doc
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
spirit:library="Testbench"
|
fs-syn
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
VEC_TABLE8'hff
|
|
BOOT_VEC8'hfc
|
|
CPU_ADD16
|
|
PROG_ROM_ADD0
|
|
PROG_ROM_WORDS0
|
|
PROG_ROM_WIDTH16
|
|
STACK_RAM_SIZE8
|
|
STACK_RAM_WORDS256
|
|
STACK_RAM_WIDTH16
|
|
|
|
|
|
|
|
|
|
|
|
|
PROG_ROM_WIDTH16
|
|
STACK_RAM_SIZE8
|
|
STACK_RAM_WORDS256
|
|
STACK_RAM_WIDTH16
|
|
|
|
|
|
|
|
|
|
|
enable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
nmi
|
clk
|
wire
|
wire
|
in
|
in
|
|
|
|
|
vec_int
|
reset
|
wire
|
wire
|
in
|
in
|
70
|
|
|
|
|
|
|
enable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
addr
|
|
wire
|
|
out
|
|
|
|
|
pg0_data
|
|
wire
|
|
in
|
|
70
|
|
|
|
|
|
alu_status
|
wdata
|
wire
|
wire
|
out
|
out
|
70
|
|
|
|
|
|
|
rdata
|
|
wire
|
|
in
|
|
|
|
|
pg0_add
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
pg0_rd
|
rd
|
wire
|
wire
|
out
|
out
|
|
|
|
|
pg0_wr
|
|
wire
|
|
out
|
|
|
|
|
|
|
wr
|
|
wire
|
|
out
|
|
|
|
|
|
nmi
|
|
wire
|
|
in
|
|
|
|
|
|
vec_int
|
|
wire
|
|
in
|
|
70
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pg0_data
|
|
wire
|
|
in
|
|
70
|
|
|
|
|
|
alu_status
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
|
|
pg0_add
|
|
wire
|
|
out
|
|
70
|
|
|
|
|
|
pg0_rd
|
|
wire
|
|
out
|
|
|
|
|
|
pg0_wr
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.