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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_bytefifo.v] - Diff between revs 131 and 133

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Rev 131 Rev 133
Line 55... Line 55... 
//
 
//
 
// Ports:
 
// Ports:
 
// CLK:  Clock for all synchronous elements
 
// CLK:  Clock for all synchronous elements
 
// RST:  Zeros the counter and all registers asynchronously
 
// RST:  Zeros the counter and all registers asynchronously
 
// DATA_IN: Data to be pushed into the FIFO
 
// DATA_IN: Data to be pushed into the FIFO
 
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
 
// DATA_OUT: Always shows the data at the head of the FIFO, '00' if empty
 
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
 
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
 
//            FIFO and the count will be incremented at the next posedge
 
//            FIFO and the count will be incremented at the next posedge
 
//            of CLK (assuming the FIFO is not full).  When low (and EN
 
//            of CLK (assuming the FIFO is not full).  When low (and EN
 
//            is high), the count will be decremented and the output changed
 
//            is high), the count will be decremented and the output changed
 
//            to the next value in the FIFO (assuming FIFO not empty).
 
//            to the next value in the FIFO (assuming FIFO not empty).
Line 215... Line 215... 
          4'h4:     DATA_OUT = reg3;
 
          4'h4:     DATA_OUT = reg3;
 
          4'h5:     DATA_OUT = reg4;
 
          4'h5:     DATA_OUT = reg4;
 
          4'h6:     DATA_OUT = reg5;
 
          4'h6:     DATA_OUT = reg5;
 
          4'h7:     DATA_OUT = reg6;
 
          4'h7:     DATA_OUT = reg6;
 
          4'h8:     DATA_OUT = reg7;
 
          4'h8:     DATA_OUT = reg7;
 
          default:  DATA_OUT = 8'hXX;
 
          default:  DATA_OUT = 8'h00;
 
        endcase
 
        endcase
 
     end
 
     end
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule

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