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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_jfifo_tb.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 28...	Line 28...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.tb`	`top.tb.jfifo`


`dest_dir`	`dest_dir`
`../verilog`	`../verilog`

Line 188...	Line 188...





`../verilog/common/top.tb`	`../verilog/common/top.tb.jfifo`
`verilogSourcemodule`	`verilogSourcemodule`




Line 202...	Line 202...


`fs-lint`	`fs-lint`


`../verilog/common/top.tb`	`../verilog/common/top.tb.jfifo`
`verilogSourcemodule`	`verilogSourcemodule`

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