URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_dut.params.xml] - Diff between revs 131 and 133

Rev 131	Rev 133
Line 1...	Line 1...


`// //`	`// //`
`// Generated File Do Not EDIT //`
`// //`	`// //`
`// regen by adding -tb to gen_verilog script //`	`// //`
	`// //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
Line 24...	Line 24...
`Dut`	`Dut`


`spirit:library="fpgas"`	`spirit:library="fpgas"`
`spirit:name="Nexys2_T6502"`	`spirit:name="Nexys2_T6502"`
`spirit:version="default_dutg.design"/>`	`spirit:version="default_duth.design"/>`



`RAM_WORDS2048`	`RAM_WORDS2048`
`RAM_ADD11`	`RAM_ADD11`
Line 48...	Line 48...
`CLOCK_SRC0`	`CLOCK_SRC0`
`RESET_SENSE0`	`RESET_SENSE0`
`UART_PRESCALE5'b01100`	`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`	`UART_PRE_SIZE5`
`UART_DIV0`	`UART_DIV0`
`JTAG_SEL1`
`JTAG_USER1_WIDTH8`	`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET8'h12`	`JTAG_USER1_RESET8'h12`