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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Diff between revs 131 and 133

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`elab_verilog`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`



`trace_bus`
`103.0`
`none`
`:Simulation:`
`./tools/verilog/trace_bus`


`path`
`root.dut.core.T6502.cpu`


`bus_name`
`cpu`









`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


	`configuration`
	`default`


`destination`	`destination`
`top.T6502_tb`	`top.T6502_tb`


`dest_dir`	`dest_dir`

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