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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Diff between revs 131 and 133

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Rev 131 Rev 133
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         addr
 
         addr
 
         
         
         mem_addr
 
         mem_addr
 
           150
 
           130
 
         
         
       
       
 
 
 
 
        
        
         cs
 
         cs
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  elab_verilog
 
 
 
  102.1
 
 
 
  none
 
 
 
  :*Simulation:*
 
 
 
  ./tools/verilog/elab_verilog
 
 
 
    
 
 
    
 
 
      configuration
 
 
 
      default
 
 
 
    
 
 
    
 
 
      dest_dir
 
 
 
      io_ports
 
 
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_registers
 
  gen_registers
 
  103.0
 
  102.1
 
  common
 
  common
 
  none
 
  none
 
  ./tools/regtool/gen_registers
 
  ./tools/regtool/gen_registers
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BASE_ADDR4'h0
 
 
 
BASE_WIDTH4
 
 
 
ADDR_WIDTH8
 
 
 
MEM_WIDTH23
 
 
 
MEM_FRAME10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
enable
 
enable
 
wire
 
wire

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