URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [sim/] [testbenches/] [xml/] [io_ext_mem_interface_def_duth.design.xml] - Diff between revs 134 and 135

-Rev 134
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                                                                         //
 //                                                                                                    //
 // ./tools/verilog/gen_tb -vendor opencores.org -library io  -component io_ext_mem_interface  -version def //
 //                                                                                                    //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 io
 io_ext_mem_interface
 def_duth.design
 addr
 bank
 clk
 cs
 enable
 ext_add
 ext_cs
 ext_lb
 ext_rd
 ext_rdata
 ext_stb
 ext_ub
 ext_wait
 ext_wdata
 ext_wr
 mem_addr
 mem_cs
 mem_rd
 mem_rdata
 mem_wait
 mem_wdata
 mem_wr
 rd
 rdata
 reset
 wait_st
 wdata
 wr
 dut
  ADDR_WIDTH
  BASE_ADDR
  BASE_WIDTH
  MEM_FRAME
  MEM_WIDTH