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Line 1... |
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reg mem_cs_r;
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:8] == 8'h00) mem_cs = 1'b1;
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if(addr_in[15:8] == 8'h00) mem_cs = 1'b1;
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else mem_cs = 1'b0;
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else mem_cs = 1'b0;
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end
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end
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reg CS0_r;
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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CS0_r <= mem_cs;
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mem_cs_r <= mem_cs;
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end
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end
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assign mem_addr = addr_in;
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assign mem_rd = rd_in;
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assign mem_wr = wr_in;
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assign mem_wdata = {wdata_in,wdata_in};
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assign enable = ~( ext_mem_wait || io_reg_wait );
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reg mem_cs2;
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reg CSP_r;
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always@(*)
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begin
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if(addr_in[15:12] == 4'b1111) mem_cs2 = 1'b1;
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else mem_cs2 = 1'b0;
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end
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always@(posedge clk)
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begin
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CSP_r <= mem_cs2;
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end
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reg mem_cs3;
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reg data_cs_r;
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reg CSI_r;
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:12] == 4'b1000) mem_cs3 = 1'b1;
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if(addr_in[15:12] == 4'b0000) data_cs = 1'b1;
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else mem_cs3 = 1'b0;
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else data_cs = 1'b0;
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end
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end
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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CSI_r <= mem_cs3 ;
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data_cs_r <= data_cs;
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end
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end
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assign data_addr = addr_in[11:1];
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assign data_rd = rd_in;
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assign data_wr = wr_in;
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assign data_wdata = {wdata_in,wdata_in};
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assign data_be[0] = !addr_in[0];
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assign data_be[1] = addr_in[0];
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reg mem_cs4;
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reg CSB_r;
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reg io_reg_cs_r;
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:12] == 4'b1100) mem_cs4 = 1'b1;
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if(addr_in[15:8] == 8'b10000000) io_reg_cs = 1'b1;
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else mem_cs4 = 1'b0;
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else io_reg_cs = 1'b0;
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end
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end
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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CSB_r <= mem_cs4;
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io_reg_cs_r <= io_reg_cs;
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end
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end
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assign io_reg_addr = addr_in[7:0];
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assign io_reg_rd = rd_in;
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assign io_reg_wr = wr_in;
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assign io_reg_wdata = wdata_in;
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reg mem_cs5;
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reg ext_mem_cs_r;
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reg CSE_r;
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:14] == 2'b01) mem_cs5 = 1'b1;
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if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1;
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else mem_cs5 = 1'b0;
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else ext_mem_cs = 1'b0;
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end
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end
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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CSE_r <= mem_cs5;
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ext_mem_cs_r <= ext_mem_cs;
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end
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end
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assign ext_mem_addr = addr_in[13:0];
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assign ext_mem_rd = rd_in;
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assign ext_mem_wr = wr_in;
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assign ext_mem_wdata = {wdata_in,wdata_in};
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reg prog_rom_mem_cs_r;
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assign mem_addr = addr_in;
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assign mem_rd = rd_in;
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assign mem_wr = wr_in;
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assign mem_wdata = {wdata_in,wdata_in};
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assign enable = ~( ext_mem_wait || io_reg_wait );
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reg data_cs_r;
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:12] == 4'b0000) data_cs = 1'b1;
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if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1;
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else data_cs = 1'b0;
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else prog_rom_mem_cs = 1'b0;
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end
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end
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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data_cs_r <= data_cs;
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prog_rom_mem_cs_r <= prog_rom_mem_cs;
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end
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end
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assign data_addr = addr_in[11:1];
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assign data_rd = rd_in;
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assign data_wr = wr_in;
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assign data_wdata = {wdata_in,wdata_in};
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assign data_be[0] = !addr_in[0];
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assign data_be[1] = addr_in[0];
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assign prog_rom_mem_addr = addr_in[11:0];
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assign prog_rom_mem_rd = rd_in;
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assign prog_rom_mem_wr = wr_in;
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assign prog_rom_mem_wdata = {wdata_in,wdata_in};
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always@(*)
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begin
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if(addr_in[15:12] == 4'b1000) io_reg_cs = 1'b1;
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else io_reg_cs = 1'b0;
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end
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assign io_reg_addr = addr_in[11:0];
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assign io_reg_rd = rd_in;
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assign io_reg_wr = wr_in;
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assign io_reg_wdata = wdata_in;
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always@(*)
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begin
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if(addr_in[15:14] == 2'b01) ext_mem_cs = 1'b1;
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else ext_mem_cs = 1'b0;
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end
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assign ext_mem_addr = addr_in[13:0];
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assign ext_mem_rd = rd_in;
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assign ext_mem_wr = wr_in;
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assign ext_mem_wdata = {wdata_in,wdata_in};
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always@(*)
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reg sh_prog_rom_mem_cs_r;
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begin
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if(addr_in[15:12] == 4'b1100) prog_rom_mem_cs = 1'b1;
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else prog_rom_mem_cs = 1'b0;
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end
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assign prog_rom_mem_addr = addr_in[11:0];
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assign prog_rom_mem_rd = rd_in;
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assign prog_rom_mem_wr = wr_in;
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assign prog_rom_mem_wdata = {wdata_in,wdata_in};
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always@(*)
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always@(*)
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begin
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begin
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if(addr_in[15:12] == 4'b1111) sh_prog_rom_mem_cs = 1'b1;
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if(addr_in[15:12] == 4'b1111) sh_prog_rom_mem_cs = 1'b1;
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else sh_prog_rom_mem_cs = 1'b0;
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else sh_prog_rom_mem_cs = 1'b0;
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end
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end
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always@(posedge clk)
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begin
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sh_prog_rom_mem_cs_r <= sh_prog_rom_mem_cs;
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end
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assign sh_prog_rom_mem_addr = addr_in[11:0];
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assign sh_prog_rom_mem_addr = addr_in[11:0];
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assign sh_prog_rom_mem_rd = rd_in;
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assign sh_prog_rom_mem_rd = rd_in;
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assign sh_prog_rom_mem_wr = wr_in;
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assign sh_prog_rom_mem_wr = wr_in;
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assign sh_prog_rom_mem_wdata = {wdata_in,wdata_in};
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assign sh_prog_rom_mem_wdata = {wdata_in,wdata_in};
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always@(*)
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always@(*)
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if ( CS0_r ) rdata_out = mem_rdata;
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if ( mem_cs_r ) rdata_out = mem_rdata;
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else
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else
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if ( data_cs_r ) rdata_out = data_rdata;
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if ( data_cs_r ) rdata_out = data_rdata;
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else
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else
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if ( CSB_r ) rdata_out = prog_rom_mem_rdata;
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if ( prog_rom_mem_cs_r ) rdata_out = prog_rom_mem_rdata;
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else
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else
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if ( CSI_r ) rdata_out = io_reg_rdata;
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if ( io_reg_cs_r ) rdata_out = io_reg_rdata;
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else
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else
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if ( CSP_r ) rdata_out = sh_prog_rom_mem_rdata;
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if ( sh_prog_rom_mem_cs_r ) rdata_out = sh_prog_rom_mem_rdata;
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else rdata_out = ext_mem_rdata;
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else rdata_out = ext_mem_rdata;
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