Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
wishbone
|
wishbone
|
wb_memory
|
wb_memory
|
def default
|
def
|
|
|
|
|
|
|
|
|
|
|
|
|
slave_clk
|
slave_clk
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
clk_i
|
clk
|
|
clk_i
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
rst_i
|
reset
|
|
rst_i
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
wb
|
wb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
adr
|
adr
|
|
|
adr_i
|
adr_i
|
wb_addr_width-10
|
wb_addr_width-10
|
|
|
|
|
|
|
|
|
|
|
|
|
wdata
|
wdata
|
|
|
dat_i
|
dat_i
|
wb_data_width-10
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
|
|
rdata
|
rdata
|
|
|
dat_o
|
dat_o
|
wb_data_width-10
|
wb_data_width-10
|
|
|
|
|
|
|
|
|
|
|
sel
|
sel
|
|
|
sel_i
|
sel_i
|
wb_byte_lanes-10
|
wb_byte_lanes-10
|
|
|
|
|
|
|
|
|
|
|
we
|
we
|
|
|
we_i
|
we_i
|
|
|
|
|
|
|
|
|
|
|
cyc
|
cyc
|
|
|
cyc_i
|
cyc_i
|
|
|
|
|
|
|
|
|
|
|
stb
|
stb
|
|
|
stb_i
|
stb_i
|
|
|
|
|
|
|
|
|
|
|
ack
|
ack
|
|
|
ack_o
|
ack_o
|
reg
|
reg
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
wb_memory_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
wb_memory_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
spirit:library="wishbone"
|
|
spirit:name="wb_memory"
|
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
common:*common:*
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
Verilog
|
syn:*Synthesis:*
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
doc
|
syn:*Synthesis:*
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
wb_addr_width24
|
|
wb_data_width32
|
|
wb_byte_lanes4
|
|
dat_width32
|
|
adr_width14
|
|
mem_size16384
|
|
SRAM_MEM_0_FILE"NONE"
|
|
SRAM_MEM_1_FILE"NONE"
|
|
SRAM_MEM_2_FILE"NONE"
|
|
SRAM_MEM_3_FILE"NONE"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
wb_addr_width24
|
|
wb_data_width32
|
|
wb_byte_lanes4
|
|
dat_width32
|
|
adr_width14
|
|
mem_size16384
|
|
SRAM_MEM_0_FILE"NONE"
|
|
SRAM_MEM_1_FILE"NONE"
|
|
SRAM_MEM_2_FILE"NONE"
|
|
SRAM_MEM_3_FILE"NONE"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
fs-sim
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/wb_memory_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
fs-sim
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/wb_memory_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/wb_memory_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
fs-syn
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/wb_memory_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|