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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 45...	Line 45...








	`elab_verilog`
	`103.0`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`dest_dir`
	`io_ports`









`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`top.in.sim`


`dest_dir`	`dest_dir`
`../verilog`	`../verilog`

Line 72...	Line 92...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`top.in.syn`


`dest_dir`	`dest_dir`
`../verilog`	`../verilog`

Line 136...	Line 156...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/sim/top.out.sim`	`../verilog/sim/top.in.sim`
`verilogSourcemodule`	`verilogSourcemodule`




Line 170...	Line 190...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/syn/top.out.syn`	`../verilog/syn/top.in.syn`
`verilogSourcemodule`	`verilogSourcemodule`



`dest_dir../views/syn/`	`dest_dir../views/syn/`

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