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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 54...	Line 54...


`addr`	`addr`

`addr`	`addr`
`ADDR_WIDTH-10`	`addr_width-10`




`wdata`	`wdata`
Line 102...	Line 102...







	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`dest_dir`
	`io_ports`








	`gen_verilog_sim`
	`104.0`
	`none`
	`:Simulation:`
	`./tools/verilog/gen_verilog`


	`destination`
	`top`


	`dest_dir`
	`../verilog`








	`gen_verilog_syn`
	`104.0`
	`none`
	`:Synthesis:`
	`./tools/verilog/gen_verilog`


	`destination`
	`top`


	`dest_dir`
	`../verilog`










`gen_verilogLib_sim`	`gen_verilogLib_sim`
`105.0`	`105.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
Line 157...	Line 219...




`../verilog/top.sim`	`../verilog/top.sim`
	`verilogSourcefragment`




	`../verilog/sim/top`
`verilogSourcemodule`	`verilogSourcemodule`



`dest_dir../views/sim/`	`dest_dir../views/sim/`
Line 184...	Line 252...




`../verilog/top.syn`	`../verilog/top.syn`
	`verilogSourcefragment`




	`../verilog/syn/top`
`verilogSourcemodule`	`verilogSourcemodule`






`dest_dir../views/syn/`	`dest_dir../views/syn/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`


Line 209...	Line 286...

`Hierarchical`	`Hierarchical`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="io_probe"`	`spirit:name="micro_bus_model"`
`spirit:version="in.design"/>`	`spirit:version="def.design"/>`



`sim:Simulation:`	`sim:Simulation:`

Line 310...	Line 387...
`70`	`70`



`cs`	`cs`
`wire`	`reg`
`out`	`out`

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