URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.sim] - Diff between revs 131 and 133

Rev 131	Rev 133
Line 2...	Line 2...

`module mt45w8mw12_def`	`module mt45w8mw12_def`
`#(`	`#(`
`parameter ADDR_BITS = 23,`	`parameter ADDR_BITS = 23,`
`parameter DQ_BITS = 16,`	`parameter DQ_BITS = 16,`
`parameter MEM_BITS = 16,`	`parameter MEM_BITS = 16`
`parameter INIT_FILE_E = "NONE",`
`parameter INIT_FILE_O = "NONE"`

`)`	`)`

`(`	`(`
`input wire clk,`	`input wire clk,`
`input wire adv_n,`	`input wire adv_n,`
Line 27...	Line 24...
`reg [7:0] memoryl [1<`	`reg [7:0] memoryl [1<`
`reg [7:0] memoryu [1<`	`reg [7:0] memoryu [1<`

`reg [DQ_BITS-1 : 0] dq_out;`	`reg [DQ_BITS-1 : 0] dq_out;`

`// Load any rom images`

`initial`
`begin`
`if( INIT_FILE_E == "NONE")`
`begin`
`end`
`else $readmemh(INIT_FILE_E, memoryl);`
`end`

`initial`
`begin`
`if( INIT_FILE_O == "NONE")`
`begin`
`end`
`else $readmemh(INIT_FILE_O, memoryu);`
`end`



`// Write Memory`	`// Write Memory`