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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_hysteresis.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
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-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
cde
cde
sync
sync
with_hysteresis  default
with_hysteresis
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  :*common:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      sync_with_hysteresis
      sync_with_hysteresis
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
              
                
 
                        
 
                                verilog
 
                                verilog
 
                                cde_sync_with_hysteresis
 
                                
 
                                        
 
                                                WIDTH
 
                                                8
 
                                        
 
                                
 
                                
 
                                        fs-sim
 
                                
 
                        
 
                
 
 
              
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
              
 
 
 
 
              
        
              commoncommon
        rtl
              Verilog
        verilog:Kactus2:
              
        verilog
                     
        
                            fs-common
 
                     
 
              
 
 
 
 
              
 
              verilog
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="verilog"/>
 
              
 
              
 
 
 
 
              
 
              sim:*Simulation:*
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
              
              syn:*Synthesis:*
              common:*common:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-syn
                            fs-common
                     
                     
              
              
 
 
 
 
              
 
              doc
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
              
 
              sim:*Simulation:*
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
 
              syn:*Synthesis:*
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
 
 
 
              
 
              doc
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
              
 
 
 
 
 
 
 
WIDTH1
 
DEBOUNCE_SIZE4
 
DEBOUNCE_DELAY4'b1111
 
 
 
 
 
 
 
 
 
clk
              
wire
 
in
 
 
 
 
 
reset
 
wire
 
in
 
 
 
 
 
data_in
 
wire
WIDTH1
in
DEBOUNCE_SIZE4
WIDTH-10
DEBOUNCE_DELAY4'b1111
 
 
 
 
data_out
 
reg
 
out
 
WIDTH-10
 
 
 
 
 
data_rise
clk
reg
wire
out
in
WIDTH-10
 
 
 
 
 
data_fall
reset
reg
wire
out
in
WIDTH-10
 
 
 
 
 
 
data_in
 
wire
 
in
 
WIDTH-10
 
 
 
 
 
data_out
 
reg
 
out
 
WIDTH-10
 
 
 
 
 
data_rise
 
reg
 
out
 
WIDTH-10
 
 
 
 
 
data_fall
 
reg
 
out
 
WIDTH-10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/sync_with_hysteresis
 
        verilogSourcefragment
 
      
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/sync_with_hysteresis
 
        verilogSourcefragment
 
      
 
 
   
 
 
 
 
 
   
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
   
 
 
      
 
        
 
        ../verilog/common/sync_with_hysteresis
 
        verilogSourcemodule
 
      
 
 
 
 
   
 
      fs-sim
 
 
      
      
        dest_dir
        
        ../views/sim/
        ../verilog/copyright
        verilogSourcelibraryDir
        verilogSourceinclude
      
      
 
 
  
 
 
 
 
      
 
        
 
        ../verilog/common/sync_with_hysteresis
 
        verilogSourcemodule
 
      
 
 
   
 
      fs-syn
 
 
 
 
      
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
      
  
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
   
        
      fs-syn
        ../verilog/common/sync_with_hysteresis
 
        verilogSourcemodule
 
      
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
   
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/sync_with_hysteresis
 
        verilogSourcemodule
 
      
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
   
   
      fs-lint
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
   
 
 
 
 
 
 
   
 
      fs-lint
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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