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[/] [socgen/] [trunk/] [tools/] [sys/] [workspace] - Diff between revs 127 and 128

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Rev 127 Rev 128
Line 178... Line 178...
      my($chip_name)  = $i_name ->findnodes('./text()')->to_literal ;
      my($chip_name)  = $i_name ->findnodes('./text()')->to_literal ;
      my($chip_target)  = $i_name ->findnodes('../socgen:target/socgen:library/text()')->to_literal ;
      my($chip_target)  = $i_name ->findnodes('../socgen:target/socgen:library/text()')->to_literal ;
      my($chip_part)  = $i_name ->findnodes('../socgen:target/socgen:part/text()')->to_literal ;
      my($chip_part)  = $i_name ->findnodes('../socgen:target/socgen:part/text()')->to_literal ;
      $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/Makefile";
      $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/Makefile";
      open  MAKSYNFILE,">$outfile" or die "unable to open $outfile";
      open  MAKSYNFILE,">$outfile" or die "unable to open $outfile";
      print MAKSYNFILE  "include ../../../../../bin/Makefile.root\n";
      print MAKSYNFILE  "include ${home}/tools/bin/Makefile.root\n";
      print MAKSYNFILE  "Part=${chip_part}\n";
      print MAKSYNFILE  "Part=${chip_part}\n";
      print MAKSYNFILE  "board=${chip_target}\n";
      print MAKSYNFILE  "board=${chip_target}\n";
      print MAKSYNFILE  "Design=${chip_name}\n";
      print MAKSYNFILE  "Design=${chip_name}\n";
      my $path  = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/target";
      my $path  = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/target";
      mkdir $path,0755          unless( -e $path );
      mkdir $path,0755          unless( -e $path );
      &sys::lib::link_dir( "${home}/tools/synthesys/targets/ip/${chip_target}", "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/target"  );
      &sys::lib::link_dir( "${home}/tools/synthesys/targets/ip/${chip_target}", "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/target"  );
      &sys::lib::link_dir( "${home}/tools/Jtag_programmers/debug", "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}/syn/ise/${chip_name}/debug"  );
 
      }
      }
   }
   }
 
 
 
 
 
 

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