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https://opencores.org/ocsvn/socgen/socgen/trunk
[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilog] - Diff between revs 123 and 124
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| Rev 123 |
Rev 124 |
| Line 113... |
Line 113... |
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my $path ="${home}/projects/${vendor}/${project}/ip/${component}/sim";
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my $path ="${home}/projects/${vendor}/${project}/ip/${component}/sim";
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mkdir $path,0755 unless( -e $path );
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mkdir $path,0755 unless( -e $path );
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$path ="${home}/projects/${vendor}/${project}/ip/${component}/sim/xml";
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my $path ="${home}/projects/${vendor}/${project}/ip/${component}/sim/testbenches";
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mkdir $path,0755 unless( -e $path );
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$path ="${home}/projects/${vendor}/${project}/ip/${component}/sim/testbenches/xml";
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mkdir $path,0755 unless( -e $path );
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mkdir $path,0755 unless( -e $path );
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$outfile ="${home}/projects/${vendor}/${project}/ip/${component}/sim/xml/${variant}_dut.params.xml";
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$outfile ="${home}/projects/${vendor}/${project}/ip/${component}/sim/testbenches/xml/${variant}_dut.params.xml";
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open TB_COMP_FILE,">$outfile" or die "unable to open $outfile";
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open TB_COMP_FILE,">$outfile" or die "unable to open $outfile";
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$outfile ="${home}/projects/${vendor}/${project}/ip/${component}/sim/xml/${variant}_dutg.design.xml";
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$outfile ="${home}/projects/${vendor}/${project}/ip/${component}/sim/testbenches/xml/${variant}_dutg.design.xml";
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open TB_DESIGN_FILE,">$outfile" or die "unable to open $outfile";
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open TB_DESIGN_FILE,">$outfile" or die "unable to open $outfile";
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print TB_COMP_FILE "\n";
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print TB_COMP_FILE "\n";
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print TB_COMP_FILE "
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