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//////////////////////////////////////////////////////////////////////////////
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// //
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// 1-wire (owr) slave model //
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// //
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// Copyright (C) 2010 Iztok Jeras //
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// //
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//////////////////////////////////////////////////////////////////////////////
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// //
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// This RTL is free hardware: you can redistribute it and/or modify //
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// it under the terms of the GNU Lesser General Public License //
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// as published by the Free Software Foundation, either //
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// version 3 of the License, or (at your option) any later version. //
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// //
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// This RTL is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with this program. If not, see <http://www.gnu.org/licenses/>. //
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// //
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1us / 1ns
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module onewire_slave_model #(
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// time slot (min=15.0, typ=30.0, max=60.0)
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parameter TS = 30.0
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)(
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// configuration
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input wire ena, // response enable
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input wire ovd, // overdrive mode select
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input wire dat_r, // read data
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output wire dat_w, // write data
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// 1-wire
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inout wire owr
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);
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// IO
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reg pul;
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reg dat;
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// events
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event sample_dat;
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event sample_rst;
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//////////////////////////////////////////////////////////////////////////////
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// IO
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//////////////////////////////////////////////////////////////////////////////
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// onewire open collector signal
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assign owr = pul & ena ? 1'b0 : 1'bz;
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// read data output
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assign dat_w = ena ? dat : 1'bz;
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//////////////////////////////////////////////////////////////////////////////
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// events inside a cycle
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//////////////////////////////////////////////////////////////////////////////
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// power up state
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initial pul <= 1'b0;
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always @ (negedge owr) if (ena) transfer (ovd, dat_r, dat);
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task automatic transfer (
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input ovd,
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input dat_r,
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output dat_w
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); begin
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// provide read data response
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pul = ~dat_r;
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// wait 1 time slot
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if (ovd) #(1*TS/8);
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else #(1*TS);
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// write data is sampled here
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-> sample_dat;
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dat_w = owr;
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// release the wire
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pul = 1'b0;
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// fork into data or reset cycle
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fork
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// transfer data
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begin : transfer_dat
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// if cycle ends before reset is detected
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if (~owr) @ (posedge owr);
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// disable reset path
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disable transfer_rst;
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end
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// transfer reset
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begin : transfer_rst
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// wait 7 time slots
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if (ovd) #(7*TS/8);
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else #(7*TS);
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// reset is sampled here
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-> sample_rst;
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// if reset is detected disable data path
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if (~owr) disable transfer_dat;
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// wait for reset low to end
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@ (posedge owr)
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// wait 1 time slot
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if (ovd) #(1*TS/8);
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else #(1*TS);
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// provide presence pulse
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pul = 1'b1;
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// wait 4 time slot
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if (ovd) #(4*TS/8);
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else #(4*TS);
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// release the wire
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pul = 1'b0;
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end
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join
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end endtask
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endmodule
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